OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [RX600_RX62N-RSK_GNURX/] [RTOSDemo/] [GNU-Files/] [hwinit.c] - Blame information for rev 588

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 585 jeremybenn
/***********************************************************************/
2
/*                                                                     */
3
/*  FILE        :hwinit.c                                              */
4
/*  DATE        :Wed, Aug 25, 2010                                     */
5
/*  DESCRIPTION :Hardware Setup file                                   */
6
/*  CPU TYPE    :Other                                                 */
7
/*                                                                     */
8
/*  This file is generated by KPIT GNU Project Generator.              */
9
/*                                                                     */
10
/***********************************************************************/
11
 
12
 
13
 
14
#include "iodefine.h"
15
#ifdef __cplusplus
16
extern "C" {
17
#endif
18
extern void hw_initialise(void);
19
#ifdef __cplusplus
20
}
21
#endif
22
 
23
void hw_initialise(void)
24
{
25
/*
26
  SCI.SMR.BYTE = 0;
27
  SCI.SMR.BIT.CA   = 1;
28
  SCI.SMR.BIT.CHR  = 1;
29
  SCI.SMR.BIT.OE   = 1;
30
  SCI.SMR.BIT.STOP = 1;
31
  SCI.SMR.BIT.MP   = 1;
32
  SCI.SMR.BIT.CKS  = 3;
33
  SCI.BRR = 0;
34
  SCI.SCR.BYTE = 0;
35
  SCI.SCR.BIT.TIE  = 1;
36
  SCI.SCR.BIT.RIE  = 1;
37
  SCI.SCR.BIT.TE   = 1;
38
  SCI.SCR.BIT.RE   = 1;
39
  SCI.SCR.BIT.MPIE = 1;
40
  SCI.SCR.BIT.TEIE = 1;
41
  SCI.SCR.BIT.CKE  = 3;
42
  SCI.TDR = 0;
43
  SCI.SSR.BYTE = 0;
44
  SCI.SSR.BIT.TDRE = 1;
45
  SCI.SSR.BIT.RDRF = 1;
46
  SCI.SSR.BIT.ORER = 1;
47
  SCI.SSR.BIT.FER  = 1;
48
  SCI.SSR.BIT.PER  = 1;
49
  SCI.SSR.BIT.TEND = 1;
50
  SCI.SSR.BIT.MPB  = 1;
51
  SCI.SSR.BIT.MPBT = 1;
52
  SCI.RDR = 0;
53
 
54
*/
55
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.