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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [RX600_RX62N-RSK_GNURX/] [RTOSDemo/] [vects.c] - Blame information for rev 615

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Line No. Rev Author Line
1 585 jeremybenn
/***********************************************************************/
2
/*                                                                     */
3
/*  FILE        :vects.c                                               */
4
/*  DATE        :Wed, Aug 25, 2010                                     */
5
/*  DESCRIPTION :Vector Table                                          */
6
/*  CPU TYPE    :Other                                                 */
7
/*                                                                     */
8
/*  This file is generated by KPIT GNU Project Generator.              */
9
/*                                                                     */
10
/***********************************************************************/
11
 
12
 
13
 
14
 
15
#include "inthandler.h"
16
 
17
typedef void (*fp) (void);
18
extern void start(void);
19
extern void stack (void);
20
extern void vTickISR( void );
21
extern void vSoftwareInterruptISR( void );
22
extern void vT0_1_ISR_Handler( void );
23
extern void vT2_3_ISR_Handler( void );
24
extern void vEMAC_ISR_Handler( void );
25
extern void vTimer2_ISR_Handler( void );
26
 
27
#define FVECT_SECT          __attribute__ ((section (".fvectors")))
28
 
29
const fp HardwareVectors[] FVECT_SECT  = {
30
//;0xffffff80  Reserved
31
    (fp)0,
32
//;0xffffff84  Reserved
33
    (fp)0,
34
//;0xffffff88  Reserved
35
    (fp)0,
36
//;0xffffff8C  Reserved
37
    (fp)0,
38
//;0xffffff90  Reserved
39
    (fp)0,
40
//;0xffffff94  Reserved
41
    (fp)0,
42
//;0xffffff98  Reserved
43
    (fp)0,
44
//;0xffffff9C  Reserved
45
    (fp)0,
46
//;0xffffffA0  Reserved
47
    (fp)0,
48
//;0xffffffA4  Reserved
49
    (fp)0,
50
//;0xffffffA8  Reserved
51
    (fp)0,
52
//;0xffffffAC  Reserved
53
    (fp)0,
54
//;0xffffffB0  Reserved
55
    (fp)0,
56
//;0xffffffB4  Reserved
57
    (fp)0,
58
//;0xffffffB8  Reserved
59
    (fp)0,
60
//;0xffffffBC  Reserved
61
    (fp)0,
62
//;0xffffffC0  Reserved
63
    (fp)0,
64
//;0xffffffC4  Reserved
65
    (fp)0,
66
//;0xffffffC8  Reserved
67
    (fp)0,
68
//;0xffffffCC  Reserved
69
    (fp)0,
70
//;0xffffffd0  Exception(Supervisor Instruction)
71
    INT_Excep_SuperVisorInst,
72
//;0xffffffd4  Reserved
73
    (fp)0,
74
//;0xffffffd8  Reserved
75
    (fp)0,
76
//;0xffffffdc  Exception(Undefined Instruction)
77
    INT_Excep_UndefinedInst,
78
//;0xffffffe0  Reserved
79
    (fp)0,
80
//;0xffffffe4  Exception(Floating Point)
81
    INT_Excep_FloatingPoint,
82
//;0xffffffe8  Reserved
83
    (fp)0,
84
//;0xffffffec  Reserved
85
    (fp)0,
86
//;0xfffffff0  Reserved
87
    (fp)0,
88
//;0xfffffff4  Reserved
89
    (fp)0,
90
//;0xfffffff8  NMI
91
    INT_NonMaskableInterrupt,
92
//;0xfffffffc  RESET
93
//;<<VECTOR DATA START (POWER ON RESET)>>
94
//;Power On Reset PC
95
    start
96
//;<<VECTOR DATA END (POWER ON RESET)>>
97
};
98
 
99
#define RVECT_SECT          __attribute__ ((section (".rvectors")))
100
 
101
const fp RelocatableVectors[] RVECT_SECT  = {
102
//;0x0000  Reserved
103
    (fp)0,
104
//;0x0004  Reserved
105
    (fp)0,
106
//;0x0008  Reserved
107
    (fp)0,
108
//;0x000C  Reserved
109
    (fp)0,
110
//;0x0010  Reserved
111
    (fp)0,
112
//;0x0014  Reserved
113
    (fp)0,
114
//;0x0018  Reserved
115
    (fp)0,
116
//;0x001C  Reserved
117
    (fp)0,
118
//;0x0020  Reserved
119
    (fp)0,
120
//;0x0024  Reserved
121
    (fp)0,
122
//;0x0028  Reserved
123
    (fp)0,
124
//;0x002C  Reserved
125
    (fp)0,
126
//;0x0030  Reserved
127
    (fp)0,
128
//;0x0034  Reserved
129
    (fp)0,
130
//;0x0038  Reserved
131
    (fp)0,
132
//;0x003C  Reserved
133
    (fp)0,
134
//;0x0040  BUSERR
135
        (fp)INT_Excep_BUSERR,
136
//;0x0044  Reserved
137
    (fp)0,
138
//;0x0048  Reserved
139
    (fp)0,
140
//;0x004C  Reserved
141
    (fp)0,
142
//;0x0050  Reserved
143
    (fp)0,
144
//;0x0054 FCUERR
145
        (fp)INT_Excep_FCU_FCUERR,
146
//;0x0058  Reserved
147
    (fp)0,
148
//;0x005C  FRDYI
149
        (fp)INT_Excep_FCU_FRDYI,
150
//;0x0060  Reserved
151
    (fp)0,
152
//;0x0064  Reserved
153
    (fp)0,
154
//;0x0068  Reserved
155
    (fp)0,
156
//;0x006C  Reserved
157
    (fp)vSoftwareInterruptISR,
158
//;0x0070  CMTU0_CMT0
159
        (fp)vTickISR,
160
//;0x0074  CMTU0_CMT1
161
        (fp)INT_Excep_CMTU0_CMT1,
162
//;0x0078  CMTU1_CMT2
163
        (fp)vTimer2_ISR_Handler,
164
//;0x007C  CMTU1_CMT3
165
        (fp)INT_Excep_CMTU1_CMT3,
166
//;0x0080  Ether
167
    (fp)vEMAC_ISR_Handler,
168
//;0x0084  Reserved
169
    (fp)0,
170
//;0x0088  Reserved
171
    (fp)0,
172
//;0x008C  Reserved
173
    (fp)0,
174
//;0x0090  Reserved
175
    (fp)0,
176
//;0x0094  Reserved
177
    (fp)0,
178
//;0x0098  Reserved
179
    (fp)0,
180
//;0x009C  Reserved
181
    (fp)0,
182
//;0x00A0  Reserved
183
    (fp)0,
184
//;0x00A4  Reserved
185
    (fp)0,
186
//;0x00A8  Reserved
187
    (fp)0,
188
//;0x00AC  Reserved
189
    (fp)0,
190
//;0x00B0  Reserved
191
    (fp)0,
192
//;0x00B4  Reserved
193
    (fp)0,
194
//;0x00B8  Reserved
195
    (fp)0,
196
//;0x00BC  Reserved
197
    (fp)0,
198
//;0x00C0  Reserved
199
    (fp)0,
200
//;0x00C4  Reserved
201
    (fp)0,
202
//;0x00C8  Reserved
203
    (fp)0,
204
//;0x00CC  Reserved
205
    (fp)0,
206
//;0x00D0  Reserved
207
    (fp)0,
208
//;0x00D4  Reserved
209
    (fp)0,
210
//;0x00D8  Reserved
211
    (fp)0,
212
//;0x00DC  Reserved
213
    (fp)0,
214
//;0x00E0  Reserved
215
    (fp)0,
216
//;0x00E4  Reserved
217
    (fp)0,
218
//;0x00E8  Reserved
219
    (fp)0,
220
//;0x00EC  Reserved
221
    (fp)0,
222
//;0x00F0  Reserved
223
    (fp)0,
224
//;0x00F4  Reserved
225
    (fp)0,
226
//;0x00F8  Reserved
227
    (fp)0,
228
//;0x00FC  Reserved
229
    (fp)0,
230
//;0x0100  IRQ0
231
    (fp)INT_Excep_IRQ0,
232
//;0x0104 IRQ1
233
    (fp)INT_Excep_IRQ1,
234
//;0x0108 IRQ2
235
    (fp)INT_Excep_IRQ2,
236
//;0x010C IRQ3
237
    (fp)INT_Excep_IRQ3,
238
//;0x0110 IRQ4
239
    (fp)INT_Excep_IRQ4,
240
//;0x0114 IRQ5
241
    (fp)INT_Excep_IRQ5,
242
//;0x0118 IRQ6
243
    (fp)INT_Excep_IRQ6,
244
//;0x011C IRQ7
245
    (fp)INT_Excep_IRQ7,
246
//;0x0120 IRQ8
247
    (fp)INT_Excep_IRQ8,
248
//;0x0124 IRQ9
249
    (fp)INT_Excep_IRQ9,
250
//;0x0128 IRQ10
251
    (fp)INT_Excep_IRQ10,
252
//;0x012C IRQ11
253
    (fp)INT_Excep_IRQ11,
254
//;0x0130 IRQ12
255
    (fp)INT_Excep_IRQ12,
256
//;0x0134 IRQ13
257
    (fp)INT_Excep_IRQ13,
258
//;0x0138 IRQ14
259
    (fp)INT_Excep_IRQ14,
260
//;0x013C IRQ15
261
    (fp)INT_Excep_IRQ15,
262
//;0x0140  Reserved
263
    (fp)0,
264
//;0x0144  Reserved
265
    (fp)0,
266
//;0x0148  Reserved
267
    (fp)0,
268
//;0x014C  Reserved
269
    (fp)0,
270
//;0x0150  Reserved
271
    (fp)0,
272
//;0x0154  Reserved
273
    (fp)0,
274
//;0x0158  Reserved
275
    (fp)0,
276
//;0x015C  Reserved
277
    (fp)0,
278
//;0x0160  Reserved
279
    (fp)0,
280
//;0x0164  Reserved
281
    (fp)0,
282
//;0x0168  Reserved
283
    (fp)0,
284
//;0x016C  Reserved
285
    (fp)0,
286
//;0x0170  Reserved
287
    (fp)0,
288
//;0x0174  Reserved
289
    (fp)0,
290
//;0x0178  Reserved
291
    (fp)0,
292
//;0x017C  Reserved
293
    (fp)0,
294
//;0x0180  WDT_WOVI
295
    (fp)INT_Excep_WDT_WOVI,
296
//;0x0184  Reserved
297
    (fp)0,
298
//;0x0188  AD0_ADI0
299
    (fp)INT_Excep_AD0_ADI0,
300
//;0x018C  AD1_ADI1
301
    (fp)INT_Excep_AD1_ADI1,
302
//;0x0190  AD2_ADI2
303
    (fp)INT_Excep_AD2_ADI2,
304
//;0x0194  AD3_ADI3
305
    (fp)INT_Excep_AD3_ADI3,
306
//;0x0198  Reserved
307
    (fp)0,
308
//;0x019C  Reserved
309
    (fp)0,
310
//;0x01A0  TPU0_TGI0A
311
        (fp)INT_Excep_TPU0_TGI0A,
312
//;0x01A4  TPU0_TGI0B
313
    (fp)INT_Excep_TPU0_TGI0B,
314
//;0x01A8  TPU0_TGI0C
315
    (fp)INT_Excep_TPU0_TGI0C,
316
//;0x01AC  TPU0_TGI0D
317
    (fp)INT_Excep_TPU0_TGI0D,
318
//;0x01B0  TPU0_TCI0V
319
    (fp)INT_Excep_TPU0_TCI0V,
320
//;0x01B4  Reserved
321
    (fp)0,
322
//;0x01B8  Reserved
323
    (fp)0,
324
//;0x01BC  TPU1_TGI1A
325
        (fp)INT_Excep_TPU1_TGI1A,
326
//;0x01C0  TPU1_TGI1B
327
    (fp)INT_Excep_TPU1_TGI1B,
328
//;0x01C4  Reserved
329
    (fp)0,
330
//;0x01C8  Reserved
331
    (fp)0,
332
//;0x01CC  TPU1_TCI1V
333
    (fp)INT_Excep_TPU1_TCI1V,
334
//;0x01D0  TPU1_TCI1U
335
    (fp)INT_Excep_TPU1_TCI1U,
336
//;0x01D4  TPU2_TGI2A
337
        (fp)INT_Excep_TPU2_TGI2A,
338
//;0x01D8  TPU2_TGI2B
339
    (fp)INT_Excep_TPU2_TGI2B,
340
//;0x01DC  Reserved
341
    (fp)0,
342
//;0x01E0  TPU2_TCI2V
343
    (fp)INT_Excep_TPU2_TCI2V,
344
//;0x01E4  TPU2_TCI2U
345
    (fp)INT_Excep_TPU2_TCI2U,
346
//;0x01E8  TPU3_TGI3A
347
    (fp)INT_Excep_TPU3_TGI3A,
348
//;0x01EC  TPU3_TGI3B
349
    (fp)INT_Excep_TPU3_TGI3B,
350
//;0x01F0  TPU3_TGI3C
351
    (fp)INT_Excep_TPU3_TGI3C,
352
//;0x01F4  TPU3_TGI3D
353
    (fp)INT_Excep_TPU3_TGI3D,
354
//;0x01F8  TPU3_TCI3V
355
    (fp)INT_Excep_TPU3_TCI3V,
356
//;0x01FC  TPU4_TGI4A
357
    (fp)INT_Excep_TPU4_TGI4A,
358
//;0x0200  TPU4_TGI4B
359
    (fp)INT_Excep_TPU4_TGI4B,
360
//;0x0204  Reserved
361
    (fp)0,
362
//;0x0208  Reserved
363
    (fp)0,
364
//;0x020C TPU4_TCI4V
365
    (fp)INT_Excep_TPU4_TCI4V,
366
//;0x0210 TPU4_TCI4U
367
    (fp)INT_Excep_TPU4_TCI4U,
368
//;0x0214  TPU5_TGI5A
369
    (fp)INT_Excep_TPU5_TGI5A,
370
//;0x0218  TPU5_TGI5B
371
    (fp)INT_Excep_TPU5_TGI5B,
372
//;0x021C  Reserved
373
    (fp)0,
374
//;0x0220  TPU5_TCI5V
375
    (fp)INT_Excep_TPU5_TCI5V,
376
//;0x0224  TPU5_TCI5U
377
    (fp)INT_Excep_TPU5_TCI5U,
378
//;0x0228  TPU6_TGI6A
379
    (fp)INT_Excep_TPU6_TGI6A,
380
//;0x022C  TPU6_TGI6B
381
    (fp)INT_Excep_TPU6_TGI6B,
382
//;0x0230  TPU6_TGI6C
383
    (fp)INT_Excep_TPU6_TGI6C,
384
//;0x0234  TPU6_TGI6D
385
    (fp)INT_Excep_TPU6_TGI6D,
386
//;0x0238  TPU6_TCI6V
387
    (fp)INT_Excep_TPU6_TCI6V,
388
//;0x023C  Reserved
389
    (fp)0,
390
//;0x0240  Reserved
391
    (fp)0,
392
//;0x0244  TPU7_TGI7A
393
    (fp)INT_Excep_TPU7_TGI7A,
394
//;0x0248  TPU7_TGI7B
395
    (fp)INT_Excep_TPU7_TGI7B,
396
//;0x024C  Reserved
397
    (fp)0,
398
//;0x0250  Reserved
399
    (fp)0,
400
//;0x0254  TPU7_TCI7V
401
    (fp)INT_Excep_TPU7_TCI7V,
402
//;0x0258  TPU7_TCI7U
403
    (fp)INT_Excep_TPU7_TCI7U,
404
//;0x025C  TPU8_TGI8A
405
    (fp)INT_Excep_TPU8_TGI8A,
406
//;0x0260  TPU8_TGI8B
407
    (fp)INT_Excep_TPU8_TGI8B,
408
//;0x0264  Reserved
409
    (fp)0,
410
//;0x0268  TPU8_TCI8V
411
    (fp)INT_Excep_TPU8_TCI8V,
412
//;0x026C  TPU8_TCI8U
413
    (fp)INT_Excep_TPU8_TCI8U,
414
//;0x0270  TPU9_TGI9A
415
    (fp)INT_Excep_TPU9_TGI9A,
416
//;0x0274  TPU9_TGI9B
417
    (fp)INT_Excep_TPU9_TGI9B,
418
//;0x0278  TPU9_TGI9C
419
    (fp)INT_Excep_TPU9_TGI9C,
420
//;0x027C  TPU9_TGI9D
421
    (fp)INT_Excep_TPU9_TGI9D,
422
//;0x0280  TPU9_TCI9V
423
    (fp)INT_Excep_TPU9_TCI9V,
424
//;0x0284  TPU10_TGI10A
425
    (fp)INT_Excep_TPU10_TGI10A,
426
//;0x0288  TPU10_TGI10B
427
    (fp)INT_Excep_TPU10_TGI10B,
428
//;0x028C  Reserved
429
    (fp)0,
430
//;0x0290  Reserved
431
    (fp)0,
432
//;0x0294  TPU10_TCI10V
433
    (fp)INT_Excep_TPU10_TCI10V,
434
//;0x0298  TPU10_TCI10U
435
    (fp)INT_Excep_TPU10_TCI10U,
436
//;0x029C  TPU11_TGI11A
437
    (fp)INT_Excep_TPU11_TGI11A,
438
//;0x02A0  TPU11_TGI11B
439
    (fp)INT_Excep_TPU11_TGI11B,
440
//;0x02A4  Reserved
441
    (fp)0,
442
//;0x02A8  TPU11_TCI11V
443
    (fp)INT_Excep_TPU11_TCI11V,
444
//;0x02AC  TPU11_TCI11U
445
    (fp)INT_Excep_TPU11_TCI11U,
446
//;0x02B0  Reserved
447
    (fp)0,
448
//;0x02B4  Reserved
449
    (fp)0,
450
//;0x02B8  TMR0_CMI0A
451
    (fp)vT0_1_ISR_Handler,
452
//;0x02BC  TMR0_CMI0B
453
    (fp)INT_Excep_TMR0_CMI0B,
454
//;0x02C0  TMR0_OV0I
455
    (fp)INT_Excep_TMR0_OV0I,
456
//;0x02C4  TMR1_CMI1A
457
    (fp)INT_Excep_TMR1_CMI1A,
458
//;0x02C8  TMR1_CMI1B
459
    (fp)INT_Excep_TMR1_CMI1B,
460
//;0x02CC  TMR1_OV1I
461
    (fp)INT_Excep_TMR1_OV1I,
462
//;0x02D0 TMR2_CMI2A
463
    (fp)vT2_3_ISR_Handler,
464
//;0x02D4  TMR2_CMI2B
465
    (fp)INT_Excep_TMR2_CMI2B,
466
//;0x02D8  TMR2_OV2I
467
    (fp)INT_Excep_TMR2_OV2I,
468
//;0x02DC  TMR3_CMI3A
469
    (fp)INT_Excep_TMR3_CMI3A,
470
//;0x02E0 TMR3_CMI3B
471
    (fp)INT_Excep_TMR3_CMI3B,
472
//;0x02E4  TMR3_OV3I
473
    (fp)INT_Excep_TMR3_OV3I,
474
//;0x02E8  Reserved
475
    (fp)0,
476
//;0x02EC  Reserved
477
    (fp)0,
478
//;0x02F0  Reserved
479
    (fp)0,
480
//;0x02F4  Reserved
481
    (fp)0,
482
//;0x02F8  Reserved
483
    (fp)0,
484
//;0x02FC  Reserved
485
    (fp)0,
486
//;0x0300  Reserved
487
    (fp)0,
488
//;0x0304  Reserved
489
    (fp)0,
490
//;0x0308  Reserved
491
    (fp)0,
492
//;0x030C  Reserved
493
    (fp)0,
494
//;0x0310  Reserved
495
    (fp)0,
496
//;0x0314  Reserved
497
    (fp)0,
498
//;0x0318  DMAC_DMTEND0
499
    (fp)INT_Excep_DMAC_DMTEND0,
500
//;0x031C  DMAC_DMTEND1
501
    (fp)INT_Excep_DMAC_DMTEND1,
502
//;0x0320  DMAC_DMTEND2
503
    (fp)INT_Excep_DMAC_DMTEND2,
504
//;0x0324  DMAC_DMTEND3
505
    (fp)INT_Excep_DMAC_DMTEND3,
506
//;0x0328  Reserved
507
    (fp)0,
508
//;0x032C  Reserved
509
    (fp)0,
510
//;0x0330  Reserved
511
    (fp)0,
512
//;0x0334  Reserved
513
    (fp)0,
514
//;0x0338  Reserved
515
    (fp)0,
516
//;0x033C  Reserved
517
    (fp)0,
518
//;0x0340  Reserved
519
    (fp)0,
520
//;0x0344  Reserved
521
    (fp)0,
522
//;0x0348  Reserved
523
    (fp)0,
524
//;0x034C  Reserved
525
    (fp)0,
526
//;0x0350  Reserved
527
    (fp)0,
528
//;0x0354  Reserved
529
    (fp)0,
530
//;0x0358  SCI0_ERI0
531
    (fp)INT_Excep_SCI0_ERI0,
532
//;0x035C  SCI0_RXI0
533
    (fp)INT_Excep_SCI0_RXI0,
534
//;0x0360  SCI0_TXI0
535
    (fp)INT_Excep_SCI0_TXI0,
536
//;0x0364  SCI0_TEI0
537
    (fp)INT_Excep_SCI0_TEI0,
538
//;0x0368  SCI1_ERI1
539
    (fp)INT_Excep_SCI1_ERI1,
540
//;0x036C  SCI1_RXI1
541
    (fp)INT_Excep_SCI1_RXI1,
542
//;0x0370  SCI1_TXI1
543
    (fp)INT_Excep_SCI1_TXI1,
544
//;0x0374  SCI1_TEI1
545
    (fp)INT_Excep_SCI1_TEI1,
546
//;0x0378  SCI2_ERI2
547
    (fp)INT_Excep_SCI2_ERI2,
548
//;0x037C  SCI2_RXI2
549
    (fp)INT_Excep_SCI2_RXI2,
550
//;0x0380  SCI2_TXI2
551
    (fp)INT_Excep_SCI2_TXI2,
552
//;0x0384  SCI2_TEI2
553
    (fp)INT_Excep_SCI2_TEI2,
554
//;0x0388  SCI3_ERI3
555
    (fp)INT_Excep_SCI3_ERI3,
556
//;0x038C  SCI3_RXI3
557
    (fp)INT_Excep_SCI3_RXI3,
558
//;0x0390  SCI3_TXI3
559
    (fp)INT_Excep_SCI3_TXI3,
560
//;0x0394  SCI3_TEI3
561
    (fp)INT_Excep_SCI3_TEI3,
562
//;0x0398  SCI4_ERI4
563
    (fp)INT_Excep_SCI4_ERI4,
564
//;0x039C  SCI4_RXI4
565
    (fp)INT_Excep_SCI4_RXI4,
566
//;0x03A0  SCI4_TXI4
567
    (fp)INT_Excep_SCI4_TXI4,
568
//;0x03A4  SCI4_TEI4
569
    (fp)INT_Excep_SCI4_TEI4,
570
//;0x03A8  SCI5_ERI5
571
    (fp)INT_Excep_SCI5_ERI5,
572
//;0x03AC  SCI5_RXI5
573
    (fp)INT_Excep_SCI5_RXI5,
574
//;0x03B0  SCI5_TXI5
575
    (fp)INT_Excep_SCI5_TXI5,
576
//;0x03B4  SCI5_TEI5
577
    (fp)INT_Excep_SCI5_TEI5,
578
//;0x03B8  SCI6_ERI6
579
    (fp)INT_Excep_SCI6_ERI6,
580
//;0x03BC  SCI6_RXI6
581
    (fp)INT_Excep_SCI6_RXI6,
582
//;0x03C0  SCI6_TXI6
583
    (fp)INT_Excep_SCI6_TXI6,
584
//;0x03C4  SCI6_TEI6
585
    (fp)INT_Excep_SCI6_TEI6,
586
//;0x03C8  Reserved
587
    (fp)0,
588
//;0x03CC  Reserved
589
    (fp)0,
590
//;0x03D0  Reserved
591
    (fp)0,
592
//;0x03D4  Reserved
593
    (fp)0,
594
//;0x03D8  RIIC0_EEI0
595
    (fp)INT_Excep_RIIC0_EEI0,
596
//;0x03DC  RIIC0_RXI0
597
    (fp)INT_Excep_RIIC0_RXI0,
598
//;0x03E0  RIIC0_TXI0
599
    (fp)INT_Excep_RIIC0_TXI0,
600
//;0x03E4  RIIC0_TEI0
601
    (fp)INT_Excep_RIIC0_TEI0,
602
//;0x03E8  RIIC1_EEI1
603
    (fp)INT_Excep_RIIC1_EEI1,
604
//;0x03EC  RIIC1_RXI1
605
    (fp)INT_Excep_RIIC1_RXI1,
606
//;0x03F0  RIIC1_TXI1
607
    (fp)INT_Excep_RIIC1_TXI1,
608
//;0x03F4  RIIC1_TEI1
609
    (fp)INT_Excep_RIIC1_TEI1,
610
//;0x03F8  Reserved
611
    (fp)0,
612
//;0x03FC  Reserved
613
    (fp)0,
614
};

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