OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [SuperH_SH7216_Renesas/] [RTOSDemo/] [dbsct.c] - Blame information for rev 724

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 585 jeremybenn
/***********************************************************************/
2
/*                                                                     */
3
/*  FILE        :dbsct.c                                               */
4
/*  DATE        :Sun, Dec 27, 2009                                     */
5
/*  DESCRIPTION :Setting of B,R Section                                */
6
/*  CPU TYPE    :Other                                                 */
7
/*                                                                     */
8
/*  This file is generated by Renesas Project Generator (Ver.4.16).    */
9
/*                                                                     */
10
/***********************************************************************/
11
 
12
 
13
 
14
#include "typedefine.h"
15
 
16
#pragma section $DSEC
17
static const struct {
18
    _UBYTE *rom_s;       /* Start address of the initialized data section in ROM */
19
    _UBYTE *rom_e;       /* End address of the initialized data section in ROM   */
20
    _UBYTE *ram_s;       /* Start address of the initialized data section in RAM */
21
}   DTBL[] = {
22
    { __sectop("D"), __secend("D"), __sectop("R") }
23
};
24
#pragma section $BSEC
25
static const struct {
26
    _UBYTE *b_s;         /* Start address of non-initialized data section */
27
    _UBYTE *b_e;         /* End address of non-initialized data section */
28
}   BTBL[] = {
29
    { __sectop("B"), __secend("B") }
30
};

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.