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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [SuperH_SH7216_Renesas/] [RTOSDemo/] [dbsct.c] - Blame information for rev 612

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Line No. Rev Author Line
1 585 jeremybenn
/***********************************************************************/
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/*                                                                     */
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/*  FILE        :dbsct.c                                               */
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/*  DATE        :Sun, Dec 27, 2009                                     */
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/*  DESCRIPTION :Setting of B,R Section                                */
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/*  CPU TYPE    :Other                                                 */
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/*                                                                     */
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/*  This file is generated by Renesas Project Generator (Ver.4.16).    */
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/*                                                                     */
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/***********************************************************************/
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#include "typedefine.h"
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#pragma section $DSEC
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static const struct {
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    _UBYTE *rom_s;       /* Start address of the initialized data section in ROM */
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    _UBYTE *rom_e;       /* End address of the initialized data section in ROM   */
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    _UBYTE *ram_s;       /* Start address of the initialized data section in RAM */
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}   DTBL[] = {
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    { __sectop("D"), __secend("D"), __sectop("R") }
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};
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#pragma section $BSEC
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static const struct {
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    _UBYTE *b_s;         /* Start address of non-initialized data section */
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    _UBYTE *b_e;         /* End address of non-initialized data section */
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}   BTBL[] = {
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    { __sectop("B"), __secend("B") }
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};

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