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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [SuperH_SH7216_Renesas/] [RTOSDemo/] [intprg.c] - Blame information for rev 609

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Line No. Rev Author Line
1 585 jeremybenn
/***********************************************************************/
2
/*                                                                     */
3
/*  FILE        :intprg.c                                              */
4
/*  DATE        :Sun, Dec 27, 2009                                     */
5
/*  DESCRIPTION :Interrupt Program                                     */
6
/*  CPU TYPE    :Other                                                 */
7
/*                                                                     */
8
/*  This file is generated by Renesas Project Generator (Ver.4.16).    */
9
/*                                                                     */
10
/***********************************************************************/
11
 
12
 
13
 
14
#include <machine.h>
15
#include "vect.h"
16
#pragma section IntPRG
17
 
18
// 4 Illegal code
19
void INT_Illegal_code(void){for( ;; ); /* sleep(); */}
20
 
21
// 5 Reserved
22
 
23
// 6 Illegal slot
24
void INT_Illegal_slot(void){for( ;; ); /* sleep(); */}
25
// 7 Reserved
26
 
27
// 8 Reserved
28
 
29
// 9 CPU Address error
30
void INT_CPU_Address(void){for( ;; ); /* sleep(); */}
31
// 10 DMAC Address error
32
void INT_DMAC_Address(void){for( ;; ); /* sleep(); */}
33
// 11 NMI
34
void INT_NMI(void){for( ;; ); /* sleep(); */}
35
// 12 User breakpoint trap
36
void INT_User_Break(void){for( ;; ); /* sleep(); */}
37
// 13 Reserved
38
 
39
// 14 H-UDI
40
void INT_HUDI(void){for( ;; ); /* sleep(); */}
41
// 15 Register bank over
42
void INT_Bank_Overflow(void){for( ;; ); /* sleep(); */}
43
// 16 Register bank under
44
void INT_Bank_Underflow(void){for( ;; ); /* sleep(); */}
45
// 17 ZERO DIV
46
void INT_Divide_by_Zero(void){for( ;; ); /* sleep(); */}
47
// 18 OVER DIV
48
void INT_Divide_Overflow(void){for( ;; ); /* sleep(); */}
49
// 19 Reserved
50
 
51
// 20 Reserved
52
 
53
// 21 Reserved
54
 
55
// 22 Reserved
56
 
57
// 23 Reserved
58
 
59
// 24 Reserved
60
 
61
// 25 Reserved
62
 
63
// 26 Reserved
64
 
65
// 27 Reserved
66
 
67
// 28 Reserved
68
 
69
// 29 Reserved
70
 
71
// 30 Reserved
72
 
73
// 31 Reserved
74
 
75
// 32 TRAPA (User Vecter)
76
void INT_TRAPA32(void){ for( ;; ); /* sleep(); */ }
77
// 33 TRAPA (User Vecter)
78
void INT_TRAPA33(void){for( ;; ); /* sleep(); */}
79
// 34 TRAPA (User Vecter)
80
void INT_TRAPA34(void){for( ;; ); /* sleep(); */}
81
// 35 TRAPA (User Vecter)
82
void INT_TRAPA35(void){for( ;; ); /* sleep(); */}
83
// 36 TRAPA (User Vecter)
84
void INT_TRAPA36(void){for( ;; ); /* sleep(); */}
85
// 37 TRAPA (User Vecter)
86
void INT_TRAPA37(void){for( ;; ); /* sleep(); */}
87
// 38 TRAPA (User Vecter)
88
void INT_TRAPA38(void){for( ;; ); /* sleep(); */}
89
// 39 TRAPA (User Vecter)
90
void INT_TRAPA39(void){for( ;; ); /* sleep(); */}
91
// 40 TRAPA (User Vecter)
92
void INT_TRAPA40(void){for( ;; ); /* sleep(); */}
93
// 41 TRAPA (User Vecter)
94
void INT_TRAPA41(void){for( ;; ); /* sleep(); */}
95
// 42 TRAPA (User Vecter)
96
void INT_TRAPA42(void){for( ;; ); /* sleep(); */}
97
// 43 TRAPA (User Vecter)
98
void INT_TRAPA43(void){for( ;; ); /* sleep(); */}
99
// 44 TRAPA (User Vecter)
100
void INT_TRAPA44(void){for( ;; ); /* sleep(); */}
101
// 45 TRAPA (User Vecter)
102
void INT_TRAPA45(void){for( ;; ); /* sleep(); */}
103
// 46 TRAPA (User Vecter)
104
void INT_TRAPA46(void){for( ;; ); /* sleep(); */}
105
// 47 TRAPA (User Vecter)
106
void INT_TRAPA47(void){for( ;; ); /* sleep(); */}
107
// 48 TRAPA (User Vecter)
108
void INT_TRAPA48(void){for( ;; ); /* sleep(); */}
109
// 49 TRAPA (User Vecter)
110
void INT_TRAPA49(void){for( ;; ); /* sleep(); */}
111
// 50 TRAPA (User Vecter)
112
void INT_TRAPA50(void){for( ;; ); /* sleep(); */}
113
// 51 TRAPA (User Vecter)
114
void INT_TRAPA51(void){for( ;; ); /* sleep(); */}
115
// 52 TRAPA (User Vecter)
116
void INT_TRAPA52(void){for( ;; ); /* sleep(); */}
117
// 53 TRAPA (User Vecter)
118
void INT_TRAPA53(void){for( ;; ); /* sleep(); */}
119
// 54 TRAPA (User Vecter)
120
void INT_TRAPA54(void){for( ;; ); /* sleep(); */}
121
// 55 TRAPA (User Vecter)
122
void INT_TRAPA55(void){for( ;; ); /* sleep(); */}
123
// 56 TRAPA (User Vecter)
124
void INT_TRAPA56(void){for( ;; ); /* sleep(); */}
125
// 57 TRAPA (User Vecter)
126
void INT_TRAPA57(void){for( ;; ); /* sleep(); */}
127
// 58 TRAPA (User Vecter)
128
void INT_TRAPA58(void){for( ;; ); /* sleep(); */}
129
// 59 TRAPA (User Vecter)
130
void INT_TRAPA59(void){for( ;; ); /* sleep(); */}
131
// 60 TRAPA (User Vecter)
132
void INT_TRAPA60(void){for( ;; ); /* sleep(); */}
133
// 61 TRAPA (User Vecter)
134
void INT_TRAPA61(void){for( ;; ); /* sleep(); */}
135
// 62 TRAPA (User Vecter)
136
void INT_TRAPA62(void){for( ;; ); /* sleep(); */}
137
// 63 TRAPA (User Vecter)
138
void INT_TRAPA63(void){for( ;; ); /* sleep(); */}
139
// 64 Interrupt IRQ0
140
void INT_IRQ0(void){for( ;; ); /* sleep(); */}
141
// 65 Interrupt IRQ1
142
void INT_IRQ1(void){for( ;; ); /* sleep(); */}
143
// 66 Interrupt IRQ2
144
void INT_IRQ2(void){for( ;; ); /* sleep(); */}
145
// 67 Interrupt IRQ3
146
void INT_IRQ3(void){for( ;; ); /* sleep(); */}
147
// 68 Interrupt IRQ4
148
void INT_IRQ4(void){for( ;; ); /* sleep(); */}
149
// 69 Interrupt IRQ5
150
void INT_IRQ5(void){for( ;; ); /* sleep(); */}
151
// 70 Interrupt IRQ6
152
void INT_IRQ6(void){for( ;; ); /* sleep(); */}
153
// 71 Interrupt IRQ7
154
void INT_IRQ7(void){for( ;; ); /* sleep(); */}
155
// 72 Reserved
156
 
157
// 73 Reserved
158
 
159
// 74 Reserved
160
 
161
// 75 Reserved
162
 
163
// 76 Reserved
164
 
165
// 77 Reserved
166
 
167
// 78 Reserved
168
 
169
// 79 Reserved
170
 
171
// 80 Interrupt PINT0
172
void INT_PINT0(void){for( ;; ); /* sleep(); */}
173
// 81 Interrupt PINT1
174
void INT_PINT1(void){for( ;; ); /* sleep(); */}
175
// 82 Interrupt PINT2
176
void INT_PINT2(void){for( ;; ); /* sleep(); */}
177
// 83 Interrupt PINT3
178
void INT_PINT3(void){for( ;; ); /* sleep(); */}
179
// 84 Interrupt PINT4
180
void INT_PINT4(void){for( ;; ); /* sleep(); */}
181
// 85 Interrupt PINT5
182
void INT_PINT5(void){for( ;; ); /* sleep(); */}
183
// 86 Interrupt PINT6
184
void INT_PINT6(void){for( ;; ); /* sleep(); */}
185
// 87 Interrupt PINT7
186
void INT_PINT7(void){for( ;; ); /* sleep(); */}
187
// 88 Reserved
188
 
189
// 89 Reserved
190
 
191
// 90 Reserved
192
 
193
// 91 ROM FIFE
194
void INT_ROM_FIFE(void){for( ;; ); /* sleep(); */}
195
// 92 A/D ADI0
196
void INT_AD_ADI0(void){for( ;; ); /* sleep(); */}
197
// 93 Reserved
198
 
199
// 94 Reserved
200
 
201
// 95 Reserved
202
 
203
// 96 A/D ADI1
204
void INT_AD_ADI1(void){for( ;; ); /* sleep(); */}
205
// 97 Reserved
206
 
207
// 98 Reserved
208
 
209
// 99 Reserved
210
 
211
// 100 Reserved
212
 
213
// 101 Reserved
214
 
215
// 102 Reserved
216
 
217
// 103 Reserved
218
 
219
// 104 RCANET0 ERS_0
220
void INT_RCANET0_ERS_0(void){for( ;; ); /* sleep(); */}
221
// 105 RCANET0 OVR_0
222
void INT_RCANET0_OVR_0(void){for( ;; ); /* sleep(); */}
223
// 106 RCANET0 RM01_0
224
void INT_RCANET0_RM01_0(void){for( ;; ); /* sleep(); */}
225
// 107 RCANET0 SLE_0
226
void INT_RCANET0_SLE_0(void){for( ;; ); /* sleep(); */}
227
// 108 DMAC0 DEI0
228
void INT_DMAC0_DEI0(void){for( ;; ); /* sleep(); */}
229
// 109 DMAC0 HEI0
230
void INT_DMAC0_HEI0(void){for( ;; ); /* sleep(); */}
231
// 110 Reserved
232
 
233
// 111 Reserved
234
 
235
// 112 DMAC1 DEI1
236
void INT_DMAC1_DEI1(void){for( ;; ); /* sleep(); */}
237
// 113 DMAC1 HEI1
238
void INT_DMAC1_HEI1(void){for( ;; ); /* sleep(); */}
239
// 114 Reserved
240
 
241
// 115 Reserved
242
 
243
// 116 DMAC2 DEI2
244
void INT_DMAC2_DEI2(void){for( ;; ); /* sleep(); */}
245
// 117 DMAC2 HEI2
246
void INT_DMAC2_HEI2(void){for( ;; ); /* sleep(); */}
247
// 118 Reserved
248
 
249
// 119 Reserved
250
 
251
// 120 DMAC3 DEI3
252
void INT_DMAC3_DEI3(void){for( ;; ); /* sleep(); */}
253
// 121 DMAC3 HEI3
254
void INT_DMAC3_HEI3(void){for( ;; ); /* sleep(); */}
255
// 122 Reserved
256
 
257
// 123 Reserved
258
 
259
// 124 DMAC4 DEI4
260
void INT_DMAC4_DEI4(void){for( ;; ); /* sleep(); */}
261
// 125 DMAC4 HEI4
262
void INT_DMAC4_HEI4(void){for( ;; ); /* sleep(); */}
263
// 126 Reserved
264
 
265
// 127 Reserved
266
 
267
// 128 DMAC5 DEI5
268
void INT_DMAC5_DEI5(void){for( ;; ); /* sleep(); */}
269
// 129 DMAC5 HEI5
270
void INT_DMAC5_HEI5(void){for( ;; ); /* sleep(); */}
271
// 130 Reserved
272
 
273
// 131 Reserved
274
 
275
// 132 DMAC6 DEI6
276
void INT_DMAC6_DEI6(void){for( ;; ); /* sleep(); */}
277
// 133 DMAC6 HEI6
278
void INT_DMAC6_HEI6(void){for( ;; ); /* sleep(); */}
279
// 134 Reserved
280
 
281
// 135 Reserved
282
 
283
// 136 DMAC7 DEI7
284
void INT_DMAC7_DEI7(void){for( ;; ); /* sleep(); */}
285
// 137 DMAC7 HEI7
286
void INT_DMAC7_HEI7(void){for( ;; ); /* sleep(); */}
287
// 138 Reserved
288
 
289
// 139 Reserved
290
 
291
// 140 CMT CMI0
292
//void INT_CMT_CMI0(void){for( ;; ); /* sleep(); */}
293
// 141 Reserved
294
 
295
// 142 Reserved
296
 
297
// 143 Reserved
298
 
299
// 144 CMT CMI1
300
void INT_CMT_CMI1(void){for( ;; ); /* sleep(); */}
301
// 145 Reserved
302
 
303
// 146 Reserved
304
 
305
// 147 Reserved
306
 
307
// 148 BSC CMTI
308
void INT_BSC_CMTI(void){for( ;; ); /* sleep(); */}
309
// 149 Reserved
310
 
311
// 150 USB EP4FULL
312
void INT_USB_EP4FULL(void){for( ;; ); /* sleep(); */}
313
// 151 USB EP5EMPTY
314
void INT_USB_EP5EMPTY(void){for( ;; ); /* sleep(); */}
315
// 152 WDT ITI
316
void INT_WDT_ITI(void){for( ;; ); /* sleep(); */}
317
// 153 E-DMAC EINT0
318
void INT_EDMAC_EINT0(void){for( ;; ); /* sleep(); */}
319
// 154 USB EP1FULL
320
void INT_USB_EP1FULL(void){for( ;; ); /* sleep(); */}
321
// 155 USB EP2EMPTY
322
void INT_USB_EP2EMPTY(void){for( ;; ); /* sleep(); */}
323
// 156 MTU2 MTU0 TGI0A
324
void INT_MTU2_MTU0_TGI0A(void){for( ;; ); /* sleep(); */}
325
// 157 MTU2 MTU0 TGI0B
326
void INT_MTU2_MTU0_TGI0B(void){for( ;; ); /* sleep(); */}
327
// 158 MTU2 MTU0 TGI0C
328
void INT_MTU2_MTU0_TGI0C(void){for( ;; ); /* sleep(); */}
329
// 159 MTU2 MTU0 TGI0D
330
void INT_MTU2_MTU0_TGI0D(void){for( ;; ); /* sleep(); */}
331
// 160 MTU2 MTU0 TGI0V
332
void INT_MTU2_MTU0_TGI0V(void){for( ;; ); /* sleep(); */}
333
// 161 MTU2 MTU0 TGI0E
334
void INT_MTU2_MTU0_TGI0E(void){for( ;; ); /* sleep(); */}
335
// 162 MTU2 MTU0 TGI0F
336
void INT_MTU2_MTU0_TGI0F(void){for( ;; ); /* sleep(); */}
337
// 163 Reserved
338
 
339
// 164 MTU2 MTU1 TGI1A
340
void INT_MTU2_MTU1_TGI1A(void){for( ;; ); /* sleep(); */}
341
// 165 MTU2 MTU1 TGI1B
342
void INT_MTU2_MTU1_TGI1B(void){for( ;; ); /* sleep(); */}
343
// 166 Reserved 
344
 
345
// 167 Reserved
346
 
347
// 168 MTU2 MTU1 TGI1V
348
void INT_MTU2_MTU1_TGI1V(void){for( ;; ); /* sleep(); */}
349
// 169 MTU2 MTU1 TGI1U
350
void INT_MTU2_MTU1_TGI1U(void){for( ;; ); /* sleep(); */}
351
// 170 Reserved 
352
 
353
// 171 Reserved
354
 
355
// 172 MTU2 MTU2 TGI2A
356
void INT_MTU2_MTU2_TGI2A(void){for( ;; ); /* sleep(); */}
357
// 173 MTU2 MTU2 TGI2B
358
void INT_MTU2_MTU2_TGI2B(void){for( ;; ); /* sleep(); */}
359
// 174 Reserved 
360
 
361
// 175 Reserved
362
 
363
// 176 MTU2 MTU2 TGI2V
364
void INT_MTU2_MTU2_TGI2V(void){for( ;; ); /* sleep(); */}
365
// 177 MTU2 MTU2 TGI2U
366
void INT_MTU2_MTU2_TGI2U(void){for( ;; ); /* sleep(); */}
367
// 178 Reserved 
368
 
369
// 179 Reserved
370
 
371
// 180 MTU2 MTU3 TGI3A
372
void INT_MTU2_MTU3_TGI3A(void){for( ;; ); /* sleep(); */}
373
// 181 MTU2 MTU3 TGI3B
374
void INT_MTU2_MTU3_TGI3B(void){for( ;; ); /* sleep(); */}
375
// 182 MTU2 MTU3 TGI3C
376
void INT_MTU2_MTU3_TGI3C(void){for( ;; ); /* sleep(); */}
377
// 183 MTU2 MTU3 TGI3D
378
void INT_MTU2_MTU3_TGI3D(void){for( ;; ); /* sleep(); */}
379
// 184 MTU2 MTU3 TGI3V
380
void INT_MTU2_MTU3_TGI3V(void){for( ;; ); /* sleep(); */}
381
// 185 Reserved 
382
 
383
// 186 Reserved
384
 
385
// 187 Reserved 
386
 
387
// 188 MTU2 MTU4 TGI4A
388
void INT_MTU2_MTU4_TGI4A(void){for( ;; ); /* sleep(); */}
389
// 189 MTU2 MTU4 TGI4B
390
void INT_MTU2_MTU4_TGI4B(void){for( ;; ); /* sleep(); */}
391
// 190 MTU2 MTU4 TGI4C
392
void INT_MTU2_MTU4_TGI4C(void){for( ;; ); /* sleep(); */}
393
// 191 MTU2 MTU4 TGI4D
394
void INT_MTU2_MTU4_TGI4D(void){for( ;; ); /* sleep(); */}
395
// 192 MTU2 MTU4 TGI4V
396
void INT_MTU2_MTU4_TGI4V(void){for( ;; ); /* sleep(); */}
397
// 193 Reserved 
398
 
399
// 194 Reserved
400
 
401
// 195 Reserved 
402
 
403
// 196 MTU2 MTU5 TGI5U
404
void INT_MTU2_MTU5_TGI5U(void){for( ;; ); /* sleep(); */}
405
// 197 MTU2 MTU5 TGI5V
406
void INT_MTU2_MTU5_TGI5V(void){for( ;; ); /* sleep(); */}
407
// 198 MTU2 MTU5 TGI5W
408
void INT_MTU2_MTU5_TGI5W(void){for( ;; ); /* sleep(); */}
409
// 199 Reserved 
410
 
411
// 200 POE2 OEI1
412
void INT_POE2_OEI1(void){for( ;; ); /* sleep(); */}
413
// 201 POE2 OEI2 
414
void INT_POE2_OEI2(void){for( ;; ); /* sleep(); */}
415
// 202 Reserved 
416
 
417
// 203 Reserved
418
 
419
// 204 MTU2S MTU3S TGI3A 
420
void INT_MTU2S_MTU3S_TGI3A(void){for( ;; ); /* sleep(); */}
421
// 205 MTU2S MTU3S TGI3B
422
void INT_MTU2S_MTU3S_TGI3B(void){for( ;; ); /* sleep(); */}
423
// 206 MTU2S MTU3S TGI3C
424
void INT_MTU2S_MTU3S_TGI3C(void){for( ;; ); /* sleep(); */}
425
// 207 MTU2S MTU3S TGI3D 
426
void INT_MTU2S_MTU3S_TGI3D(void){for( ;; ); /* sleep(); */}
427
// 208 MTU2S MTU3S TGI3V
428
void INT_MTU2S_MTU3S_TGI3V(void){for( ;; ); /* sleep(); */}
429
// 209 Reserved 
430
 
431
// 210 Reserved 
432
 
433
// 211 Reserved
434
 
435
// 212 MTU2S MTU4S TGI4A 
436
void INT_MTU2S_MTU4S_TGI4A(void){for( ;; ); /* sleep(); */}
437
// 213 MTU2S MTU4S TGI4B 
438
void INT_MTU2S_MTU4S_TGI4B(void){for( ;; ); /* sleep(); */}
439
// 214 MTU2S MTU4S TGI4C 
440
void INT_MTU2S_MTU4S_TGI4C(void){for( ;; ); /* sleep(); */}
441
// 215 MTU2S MTU4S TGI4D 
442
void INT_MTU2S_MTU4S_TGI4D(void){for( ;; ); /* sleep(); */}
443
// 216 MTU2S MTU4S TGI4V 
444
void INT_MTU2S_MTU4S_TGI4V(void){for( ;; ); /* sleep(); */}
445
// 217 Reserved 
446
 
447
// 218 Reserved
448
 
449
// 219 Reserved 
450
 
451
// 220 MTU2S MTU5S TGI5U 
452
void INT_MTU2S_MTU5S_TGI5U(void){for( ;; ); /* sleep(); */}
453
// 221 MTU2S MTU5S TGI5V
454
void INT_MTU2S_MTU5S_TGI5V(void){for( ;; ); /* sleep(); */}
455
// 222 MTU2S MTU5S TGI5W 
456
void INT_MTU2S_MTU5S_TGI5W(void){for( ;; ); /* sleep(); */}
457
// 223 Reserved
458
 
459
// 224 POE2 OEI3
460
void INT_POE2_OEI3(void){for( ;; ); /* sleep(); */}
461
// 225 Reserved
462
 
463
// 226 USB USI0
464
void INT_USB_USI0(void){for( ;; ); /* sleep(); */}
465
// 227 USB USI1
466
void INT_USB_USI1(void){for( ;; ); /* sleep(); */}
467
// 228 IIC3 STPI
468
void INT_IIC3_STPI(void){for( ;; ); /* sleep(); */}
469
// 229 IIC3 NAKI 
470
void INT_IIC3_NAKI(void){for( ;; ); /* sleep(); */}
471
// 230 IIC3 RXI 
472
void INT_IIC3_RXI(void){for( ;; ); /* sleep(); */}
473
// 231 IIC3 TXI
474
void INT_IIC3_TXI(void){for( ;; ); /* sleep(); */}
475
// 232 IIC3 TEI 
476
void INT_IIC3_TEI(void){for( ;; ); /* sleep(); */}
477
// 233 RSPI SPERI
478
void INT_RSPI_SPERI(void){for( ;; ); /* sleep(); */}
479
// 234 RSPI SPRXI
480
void INT_RSPI_SPRXI(void){for( ;; ); /* sleep(); */}
481
// 235 RSPI SPTXI
482
void INT_RSPI_SPTXI(void){for( ;; ); /* sleep(); */}
483
// 236 SCI SCI4 ERI4
484
void INT_SCI_SCI4_ERI4(void){for( ;; ); /* sleep(); */}
485
// 237 SCI SCI4 RXI4
486
void INT_SCI_SCI4_RXI4(void){for( ;; ); /* sleep(); */}
487
// 238 SCI SCI4 TXI4
488
void INT_SCI_SCI4_TXI4(void){for( ;; ); /* sleep(); */}
489
// 239 SCI SCI4 TEI4
490
void INT_SCI_SCI4_TEI4(void){for( ;; ); /* sleep(); */}
491
// 240 SCI SCI0 ERI0
492
void INT_SCI_SCI0_ERI0(void){for( ;; ); /* sleep(); */}
493
// 241 SCI SCI0 RXI0
494
void INT_SCI_SCI0_RXI0(void){for( ;; ); /* sleep(); */}
495
// 242 SCI SCI0 TXI0
496
void INT_SCI_SCI0_TXI0(void){for( ;; ); /* sleep(); */}
497
// 243 SCI SCI0 TEI0
498
void INT_SCI_SCI0_TEI0(void){for( ;; ); /* sleep(); */}
499
// 244 SCI SCI1 ERI1
500
void INT_SCI_SCI1_ERI1(void){for( ;; ); /* sleep(); */}
501
// 245 SCI SCI1 RXI1
502
void INT_SCI_SCI1_RXI1(void){for( ;; ); /* sleep(); */}
503
// 246 SCI SCI1 TXI1
504
void INT_SCI_SCI1_TXI1(void){for( ;; ); /* sleep(); */}
505
// 247 SCI SCI1 TEI1
506
void INT_SCI_SCI1_TEI1(void){for( ;; ); /* sleep(); */}
507
// 248 SCI SCI2 ERI2
508
void INT_SCI_SCI2_ERI2(void){for( ;; ); /* sleep(); */}
509
// 249 SCI SCI2 RXI2
510
void INT_SCI_SCI2_RXI2(void){for( ;; ); /* sleep(); */}
511
// 250 SCI SCI2 TXI2
512
void INT_SCI_SCI2_TXI2(void){for( ;; ); /* sleep(); */}
513
// 251 SCI SCI2 TEI2
514
void INT_SCI_SCI2_TEI2(void){for( ;; ); /* sleep(); */}
515
// 252 SCIF SCIF3 BRI3
516
void INT_SCIF_SCIF3_BRI3(void){for( ;; ); /* sleep(); */}
517
// 253 SCIF SCIF3 ERI3
518
void INT_SCIF_SCIF3_ERI3(void){for( ;; ); /* sleep(); */}
519
// 254 SCIF SCIF3 RXI3
520
void INT_SCIF_SCIF3_RXI3(void){for( ;; ); /* sleep(); */}
521
// 255 SCIF SCIF3 TXI3
522
void INT_SCIF_SCIF3_TXI3(void){for( ;; ); /* sleep(); */}
523
// Dummy
524
void Dummy(void){ for( ;; ); sleep(); }
525
 
526
/* End of File */

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