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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [SuperH_SH7216_Renesas/] [RTOSDemo/] [regtest.src] - Blame information for rev 585

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;/*
;    FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
;
;    ***************************************************************************
;    *                                                                         *
;    * If you are:                                                             *
;    *                                                                         *
;    *    + New to FreeRTOS,                                                   *
;    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *
;    *    + Looking for basic training,                                        *
;    *    + Wanting to improve your FreeRTOS skills and productivity           *
;    *                                                                         *
;    * then take a look at the FreeRTOS books - available as PDF or paperback  *
;    *                                                                         *
;    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *
;    *                  http://www.FreeRTOS.org/Documentation                  *
;    *                                                                         *
;    * A pdf reference manual is also available.  Both are usually delivered   *
;    * to your inbox within 20 minutes to two hours when purchased between 8am *
;    * and 8pm GMT (although please allow up to 24 hours in case of            *
;    * exceptional circumstances).  Thank you for your support!                *
;    *                                                                         *
;    ***************************************************************************
;
;    This file is part of the FreeRTOS distribution.
;
;    FreeRTOS is free software; you can redistribute it and/or modify it under
;    the terms of the GNU General Public License (version 2) as published by the
;    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
;    ***NOTE*** The exception to the GPL is included to allow you to distribute
;    a combined work that includes FreeRTOS without being obliged to provide the
;    source code for proprietary components outside of the FreeRTOS kernel.
;    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
;    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
;    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
;    more details. You should have received a copy of the GNU General Public
;    License and the FreeRTOS license exception along with FreeRTOS; if not it
;    can be viewed here: http://www.freertos.org/a00114.html and also obtained
;    by writing to Richard Barry, contact details for whom are available on the
;    FreeRTOS WEB site.
;
;    1 tab == 4 spaces!
;
;    http://www.FreeRTOS.org - Documentation, latest information, license and
;    contact details.
;
;    http://www.SafeRTOS.com - A version that is certified for use in safety
;    critical systems.
;
;    http://www.OpenRTOS.com - Commercial support, development, porting,
;    licensing and training services.
;*/
 
        .import _ulRegTest1CycleCount
        .import _ulRegTest2CycleCount
        .import _vPortYield
 
        .export _vRegTest1Task
        .export _vRegTest2Task
 
    .section    P, code, align=4
 
 
 
_vRegTest1Task:
 
        ; Fill the registers with known values.
        mov             #2, r1
        mov             #3, r2
        mov             #4, r3
        mov             #5, r4
        mov             #6, r5
        mov             #7, r6
        mov             #8, r7
        mov             #9, r8
        mov             #10, r9
        mov             #11, r10
        mov             #12, r11
        mov             #13, r12
        mov             #14, r13
        mov             #15, r14
 
        mov             #16, r0
        lds             r0, macl
        mov             #17, r0
        lds             r0, mach
        mov             #18, r0
        ldc             r0, gbr
 
        ; Also fill the flop registers with known values.
        lds             r1, fpul
        fsts    fpul, fr1
        lds             r2, fpul
        fsts    fpul, fr2
        lds             r3, fpul
        fsts    fpul, fr3
        lds             r4, fpul
        fsts    fpul, fr4
        lds             r5, fpul
        fsts    fpul, fr5
        lds             r6, fpul
        fsts    fpul, fr6
        lds             r7, fpul
        fsts    fpul, fr7
        lds             r8, fpul
        fsts    fpul, fr8
        lds             r9, fpul
        fsts    fpul, fr9
        lds             r10, fpul
        fsts    fpul, fr10
        lds             r11, fpul
        fsts    fpul, fr11
        lds             r12, fpul
        fsts    fpul, fr12
        lds             r13, fpul
        fsts    fpul, fr13
        lds             r14, fpul
        fsts    fpul, fr14
 
_vRegTest1Loop:
 
        ; Reset r1 which was used in the tests.
        mov             #2, r1
 
        ; Test that the registers still contain the expected values.  If not, jump to
        ; vRegTestError, which will stop this function looping and so cause it to stop
        ; incrementing its loop counter.  Both the standard and flop registers are
        ; checked.
        mov             #2, r0
        cmp/eq  r0, r1
        bf              _vRegTest1Error
        flds    fr1, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest1Error
 
        mov             #3, r0
        cmp/eq  r0, r2
        bf              _vRegTest1Error
        flds    fr2, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest1Error
 
        mov             #4, r0
        cmp/eq  r0, r3
        bf              _vRegTest1Error
        flds    fr3, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest1Error
 
        mov             #5, r0
        cmp/eq  r0, r4
        bf              _vRegTest1Error
        flds    fr4, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest1Error
 
        mov             #6, r0
        cmp/eq  r0, r5
        bf              _vRegTest1Error
        flds    fr5, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest1Error
 
        mov             #7, r0
        cmp/eq  r0, r6
        bf              _vRegTest1Error
        flds    fr6, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest1Error
 
        mov             #8, r0
        cmp/eq  r0, r7
        bf              _vRegTest1Error
        flds    fr7, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest1Error
 
        mov             #9, r0
        cmp/eq  r0, r8
        bf              _vRegTest1Error
        flds    fr8, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest1Error
 
        mov             #10, r0
        cmp/eq  r0, r9
        bf              _vRegTest1Error
        flds    fr9, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest1Error
 
        mov             #11, r0
        cmp/eq  r0, r10
        bf              _vRegTest1Error
        flds    fr10, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest1Error
 
        mov             #12, r0
        cmp/eq  r0, r11
        bf              _vRegTest1Error
        flds    fr11, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest1Error
 
        mov             #13, r0
        cmp/eq  r0, r12
        bf              _vRegTest1Error
        flds    fr12, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest1Error
 
        mov             #14, r0
        cmp/eq  r0, r13
        bf              _vRegTest1Error
        flds    fr13, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest1Error
 
        mov             #15, r0
        cmp/eq  r0, r14
        bf              _vRegTest1Error
        flds    fr14, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest1Error
 
        sts             macl, r0
        mov             #16, r1
        cmp/eq  r0, r1
        bf              _vRegTest1Error
 
        sts             mach, r0
        mov             #17, r1
        cmp/eq  r0, r1
        bf              _vRegTest1Error
 
        stc             gbr, r0
        mov             #18, r1
        cmp/eq  r0, r1
        bf              _vRegTest1Error
 
        ; Increment the loop counter to indicate that this task is still running and
        ; still healthy.
        mov.l   #_ulRegTest1CycleCount, r0
        mov.l   @r0, r1
        add             #1, r1
        mov.l   r1, @r0
 
        ; Jump back to test all the registers again.
        bra             _vRegTest1Loop
        nop
 
;-----------------------------------------------------------
 
_vRegTest1Error:
        bra             _vRegTest1Error
        nop
 
;-----------------------------------------------------------
 
_vRegTest2Task:
 
        ; Fill the standard registers with known values.
        mov             #12, r1
        mov             #13, r2
        mov             #14, r3
        mov             #15, r4
        mov             #16, r5
        mov             #17, r6
        mov             #18, r7
        mov             #19, r8
        mov             #110, r9
        mov             #111, r10
        mov             #112, r11
        mov             #113, r12
        mov             #114, r13
 
        mov             #115, r0
        lds             r0, macl
        mov             #116, r0
        lds             r0, mach
        mov             #117, r0
        ldc             r0, gbr
 
        ; Also fill the flop registers with known values.
        lds             r1, fpul
        fsts    fpul, fr1
        lds             r2, fpul
        fsts    fpul, fr2
        lds             r3, fpul
        fsts    fpul, fr3
        lds             r4, fpul
        fsts    fpul, fr4
        lds             r5, fpul
        fsts    fpul, fr5
        lds             r6, fpul
        fsts    fpul, fr6
        lds             r7, fpul
        fsts    fpul, fr7
        lds             r8, fpul
        fsts    fpul, fr8
        lds             r9, fpul
        fsts    fpul, fr9
        lds             r10, fpul
        fsts    fpul, fr10
        lds             r11, fpul
        fsts    fpul, fr11
        lds             r12, fpul
        fsts    fpul, fr12
        lds             r13, fpul
        fsts    fpul, fr13
        lds             r14, fpul
        fsts    fpul, fr14
 
_vRegTest2Loop:
 
        ; Reset r1 which was used in the tests.
        mov             #12, r1
 
        ; Test that the registers still contain the expected values.  If not, jump to
        ; vRegTestError, which will stop this function looping and so cause it to stop
        ; incrementing its loop counter.  Both the standard and flop registers are
        ; checked.
        mov             #12, r0
        cmp/eq  r0, r1
        bf              _vRegTest2Error
        flds    fr1, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest2Error
 
        mov             #13, r0
        cmp/eq  r0, r2
        bf              _vRegTest2Error
        flds    fr2, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest2Error
 
        mov             #14, r0
        cmp/eq  r0, r3
        bf              _vRegTest2Error
        flds    fr3, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest2Error
 
        mov             #15, r0
        cmp/eq  r0, r4
        bf              _vRegTest2Error
        flds    fr4, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest2Error
 
        mov             #16, r0
        cmp/eq  r0, r5
        bf              _vRegTest2Error
        flds    fr5, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest2Error
 
        mov             #17, r0
        cmp/eq  r0, r6
        bf              _vRegTest2Error
        flds    fr6, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest2Error
 
        mov             #18, r0
        cmp/eq  r0, r7
        bf              _vRegTest2Error
        flds    fr7, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest2Error
 
        mov             #19, r0
        cmp/eq  r0, r8
        bf              _vRegTest2Error
        flds    fr8, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest2Error
 
        mov             #110, r0
        cmp/eq  r0, r9
        bf              _vRegTest2Error
        flds    fr9, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest2Error
 
        mov             #111, r0
        cmp/eq  r0, r10
        bf              _vRegTest2Error
        flds    fr10, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest2Error
 
        mov             #112, r0
        cmp/eq  r0, r11
        bf              _vRegTest2Error
        flds    fr11, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest2Error
 
        mov             #113, r0
        cmp/eq  r0, r12
        bf              _vRegTest2Error
        flds    fr12, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest2Error
 
        mov             #114, r0
        cmp/eq  r0, r13
        bf              _vRegTest2Error
        flds    fr13, fpul
        sts             fpul, r1
        cmp/eq  r0, r1
        bf              _vRegTest2Error
 
        sts             macl, r0
        mov             #115, r1
        cmp/eq  r0, r1
        bf              _vRegTest2Error
 
        sts             mach, r0
        mov             #116, r1
        cmp/eq  r0, r1
        bf              _vRegTest2Error
 
        stc             gbr, r0
        mov             #117, r1
        cmp/eq  r0, r1
        bf              _vRegTest2Error
 
        ; Increment the loop counter to indicate that this task is still running and
        ; still healthy.
        mov.l   #_ulRegTest2CycleCount, r0
        mov.l   @r0, r1
        add             #1, r1
        mov.l   r1, @r0
 
        ; Jump back to test all the registers again.
        bra             _vRegTest2Loop
        nop
 
;-----------------------------------------------------------
 
_vRegTest2Error:
 
        bra             _vRegTest2Error
        nop
 
 
        .end
 

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Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [SuperH_SH7216_Renesas/] [RTOSDemo/] [regtest.src] - Blame information for rev 585

Line No.	Rev	Author	Line
1	585	jeremybenn	`;/*`
2			`; FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.`
3			`;`
4			`; ***************************************************************************`
5			`; * *`
6			`; * If you are: *`
7			`; * *`
8			`; * + New to FreeRTOS, *`
9			`; * + Wanting to learn FreeRTOS or multitasking in general quickly *`
10			`; * + Looking for basic training, *`
11			`; * + Wanting to improve your FreeRTOS skills and productivity *`
12			`; * *`
13			`; * then take a look at the FreeRTOS books - available as PDF or paperback *`
14			`; * *`
15			`; * "Using the FreeRTOS Real Time Kernel - a Practical Guide" *`
16			`; * http://www.FreeRTOS.org/Documentation *`
17			`; * *`
18			`; * A pdf reference manual is also available. Both are usually delivered *`
19			`; * to your inbox within 20 minutes to two hours when purchased between 8am *`
20			`; * and 8pm GMT (although please allow up to 24 hours in case of *`
21			`; * exceptional circumstances). Thank you for your support! *`
22			`; * *`
23			`; ***************************************************************************`
24			`;`
25			`; This file is part of the FreeRTOS distribution.`
26			`;`
27			`; FreeRTOS is free software; you can redistribute it and/or modify it under`
28			`; the terms of the GNU General Public License (version 2) as published by the`
29			`; Free Software Foundation AND MODIFIED BY the FreeRTOS exception.`
30			`; *NOTE* The exception to the GPL is included to allow you to distribute`
31			`; a combined work that includes FreeRTOS without being obliged to provide the`
32			`; source code for proprietary components outside of the FreeRTOS kernel.`
33			`; FreeRTOS is distributed in the hope that it will be useful, but WITHOUT`
34			`; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or`
35			`; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for`
36			`; more details. You should have received a copy of the GNU General Public`
37			`; License and the FreeRTOS license exception along with FreeRTOS; if not it`
38			`; can be viewed here: http://www.freertos.org/a00114.html and also obtained`
39			`; by writing to Richard Barry, contact details for whom are available on the`
40			`; FreeRTOS WEB site.`
41			`;`
42			`; 1 tab == 4 spaces!`
43			`;`
44			`; http://www.FreeRTOS.org - Documentation, latest information, license and`
45			`; contact details.`
46			`;`
47			`; http://www.SafeRTOS.com - A version that is certified for use in safety`
48			`; critical systems.`
49			`;`
50			`; http://www.OpenRTOS.com - Commercial support, development, porting,`
51			`; licensing and training services.`
52			`;*/`
53
54			`.import _ulRegTest1CycleCount`
55			`.import _ulRegTest2CycleCount`
56			`.import _vPortYield`
57
58			`.export _vRegTest1Task`
59			`.export _vRegTest2Task`
60
61			`.section P, code, align=4`
62
63
64
65			`_vRegTest1Task:`
66
67			`; Fill the registers with known values.`
68			`mov #2, r1`
69			`mov #3, r2`
70			`mov #4, r3`
71			`mov #5, r4`
72			`mov #6, r5`
73			`mov #7, r6`
74			`mov #8, r7`
75			`mov #9, r8`
76			`mov #10, r9`
77			`mov #11, r10`
78			`mov #12, r11`
79			`mov #13, r12`
80			`mov #14, r13`
81			`mov #15, r14`
82
83			`mov #16, r0`
84			`lds r0, macl`
85			`mov #17, r0`
86			`lds r0, mach`
87			`mov #18, r0`
88			`ldc r0, gbr`
89
90			`; Also fill the flop registers with known values.`
91			`lds r1, fpul`
92			`fsts fpul, fr1`
93			`lds r2, fpul`
94			`fsts fpul, fr2`
95			`lds r3, fpul`
96			`fsts fpul, fr3`
97			`lds r4, fpul`
98			`fsts fpul, fr4`
99			`lds r5, fpul`
100			`fsts fpul, fr5`
101			`lds r6, fpul`
102			`fsts fpul, fr6`
103			`lds r7, fpul`
104			`fsts fpul, fr7`
105			`lds r8, fpul`
106			`fsts fpul, fr8`
107			`lds r9, fpul`
108			`fsts fpul, fr9`
109			`lds r10, fpul`
110			`fsts fpul, fr10`
111			`lds r11, fpul`
112			`fsts fpul, fr11`
113			`lds r12, fpul`
114			`fsts fpul, fr12`
115			`lds r13, fpul`
116			`fsts fpul, fr13`
117			`lds r14, fpul`
118			`fsts fpul, fr14`
119
120			`_vRegTest1Loop:`
121
122			`; Reset r1 which was used in the tests.`
123			`mov #2, r1`
124
125			`; Test that the registers still contain the expected values. If not, jump to`
126			`; vRegTestError, which will stop this function looping and so cause it to stop`
127			`; incrementing its loop counter. Both the standard and flop registers are`
128			`; checked.`
129			`mov #2, r0`
130			`cmp/eq r0, r1`
131			`bf _vRegTest1Error`
132			`flds fr1, fpul`
133			`sts fpul, r1`
134			`cmp/eq r0, r1`
135			`bf _vRegTest1Error`
136
137			`mov #3, r0`
138			`cmp/eq r0, r2`
139			`bf _vRegTest1Error`
140			`flds fr2, fpul`
141			`sts fpul, r1`
142			`cmp/eq r0, r1`
143			`bf _vRegTest1Error`
144
145			`mov #4, r0`
146			`cmp/eq r0, r3`
147			`bf _vRegTest1Error`
148			`flds fr3, fpul`
149			`sts fpul, r1`
150			`cmp/eq r0, r1`
151			`bf _vRegTest1Error`
152
153			`mov #5, r0`
154			`cmp/eq r0, r4`
155			`bf _vRegTest1Error`
156			`flds fr4, fpul`
157			`sts fpul, r1`
158			`cmp/eq r0, r1`
159			`bf _vRegTest1Error`
160
161			`mov #6, r0`
162			`cmp/eq r0, r5`
163			`bf _vRegTest1Error`
164			`flds fr5, fpul`
165			`sts fpul, r1`
166			`cmp/eq r0, r1`
167			`bf _vRegTest1Error`
168
169			`mov #7, r0`
170			`cmp/eq r0, r6`
171			`bf _vRegTest1Error`
172			`flds fr6, fpul`
173			`sts fpul, r1`
174			`cmp/eq r0, r1`
175			`bf _vRegTest1Error`
176
177			`mov #8, r0`
178			`cmp/eq r0, r7`
179			`bf _vRegTest1Error`
180			`flds fr7, fpul`
181			`sts fpul, r1`
182			`cmp/eq r0, r1`
183			`bf _vRegTest1Error`
184
185			`mov #9, r0`
186			`cmp/eq r0, r8`
187			`bf _vRegTest1Error`
188			`flds fr8, fpul`
189			`sts fpul, r1`
190			`cmp/eq r0, r1`
191			`bf _vRegTest1Error`
192
193			`mov #10, r0`
194			`cmp/eq r0, r9`
195			`bf _vRegTest1Error`
196			`flds fr9, fpul`
197			`sts fpul, r1`
198			`cmp/eq r0, r1`
199			`bf _vRegTest1Error`
200
201			`mov #11, r0`
202			`cmp/eq r0, r10`
203			`bf _vRegTest1Error`
204			`flds fr10, fpul`
205			`sts fpul, r1`
206			`cmp/eq r0, r1`
207			`bf _vRegTest1Error`
208
209			`mov #12, r0`
210			`cmp/eq r0, r11`
211			`bf _vRegTest1Error`
212			`flds fr11, fpul`
213			`sts fpul, r1`
214			`cmp/eq r0, r1`
215			`bf _vRegTest1Error`
216
217			`mov #13, r0`
218			`cmp/eq r0, r12`
219			`bf _vRegTest1Error`
220			`flds fr12, fpul`
221			`sts fpul, r1`
222			`cmp/eq r0, r1`
223			`bf _vRegTest1Error`
224
225			`mov #14, r0`
226			`cmp/eq r0, r13`
227			`bf _vRegTest1Error`
228			`flds fr13, fpul`
229			`sts fpul, r1`
230			`cmp/eq r0, r1`
231			`bf _vRegTest1Error`
232
233			`mov #15, r0`
234			`cmp/eq r0, r14`
235			`bf _vRegTest1Error`
236			`flds fr14, fpul`
237			`sts fpul, r1`
238			`cmp/eq r0, r1`
239			`bf _vRegTest1Error`
240
241			`sts macl, r0`
242			`mov #16, r1`
243			`cmp/eq r0, r1`
244			`bf _vRegTest1Error`
245
246			`sts mach, r0`
247			`mov #17, r1`
248			`cmp/eq r0, r1`
249			`bf _vRegTest1Error`
250
251			`stc gbr, r0`
252			`mov #18, r1`
253			`cmp/eq r0, r1`
254			`bf _vRegTest1Error`
255
256			`; Increment the loop counter to indicate that this task is still running and`
257			`; still healthy.`
258			`mov.l #_ulRegTest1CycleCount, r0`
259			`mov.l @r0, r1`
260			`add #1, r1`
261			`mov.l r1, @r0`
262
263			`; Jump back to test all the registers again.`
264			`bra _vRegTest1Loop`
265			`nop`
266
267			`;-----------------------------------------------------------`
268
269			`_vRegTest1Error:`
270			`bra _vRegTest1Error`
271			`nop`
272
273			`;-----------------------------------------------------------`
274
275			`_vRegTest2Task:`
276
277			`; Fill the standard registers with known values.`
278			`mov #12, r1`
279			`mov #13, r2`
280			`mov #14, r3`
281			`mov #15, r4`
282			`mov #16, r5`
283			`mov #17, r6`
284			`mov #18, r7`
285			`mov #19, r8`
286			`mov #110, r9`
287			`mov #111, r10`
288			`mov #112, r11`
289			`mov #113, r12`
290			`mov #114, r13`
291
292			`mov #115, r0`
293			`lds r0, macl`
294			`mov #116, r0`
295			`lds r0, mach`
296			`mov #117, r0`
297			`ldc r0, gbr`
298
299			`; Also fill the flop registers with known values.`
300			`lds r1, fpul`
301			`fsts fpul, fr1`
302			`lds r2, fpul`
303			`fsts fpul, fr2`
304			`lds r3, fpul`
305			`fsts fpul, fr3`
306			`lds r4, fpul`
307			`fsts fpul, fr4`
308			`lds r5, fpul`
309			`fsts fpul, fr5`
310			`lds r6, fpul`
311			`fsts fpul, fr6`
312			`lds r7, fpul`
313			`fsts fpul, fr7`
314			`lds r8, fpul`
315			`fsts fpul, fr8`
316			`lds r9, fpul`
317			`fsts fpul, fr9`
318			`lds r10, fpul`
319			`fsts fpul, fr10`
320			`lds r11, fpul`
321			`fsts fpul, fr11`
322			`lds r12, fpul`
323			`fsts fpul, fr12`
324			`lds r13, fpul`
325			`fsts fpul, fr13`
326			`lds r14, fpul`
327			`fsts fpul, fr14`
328
329			`_vRegTest2Loop:`
330
331			`; Reset r1 which was used in the tests.`
332			`mov #12, r1`
333
334			`; Test that the registers still contain the expected values. If not, jump to`
335			`; vRegTestError, which will stop this function looping and so cause it to stop`
336			`; incrementing its loop counter. Both the standard and flop registers are`
337			`; checked.`
338			`mov #12, r0`
339			`cmp/eq r0, r1`
340			`bf _vRegTest2Error`
341			`flds fr1, fpul`
342			`sts fpul, r1`
343			`cmp/eq r0, r1`
344			`bf _vRegTest2Error`
345
346			`mov #13, r0`
347			`cmp/eq r0, r2`
348			`bf _vRegTest2Error`
349			`flds fr2, fpul`
350			`sts fpul, r1`
351			`cmp/eq r0, r1`
352			`bf _vRegTest2Error`
353
354			`mov #14, r0`
355			`cmp/eq r0, r3`
356			`bf _vRegTest2Error`
357			`flds fr3, fpul`
358			`sts fpul, r1`
359			`cmp/eq r0, r1`
360			`bf _vRegTest2Error`
361
362			`mov #15, r0`
363			`cmp/eq r0, r4`
364			`bf _vRegTest2Error`
365			`flds fr4, fpul`
366			`sts fpul, r1`
367			`cmp/eq r0, r1`
368			`bf _vRegTest2Error`
369
370			`mov #16, r0`
371			`cmp/eq r0, r5`
372			`bf _vRegTest2Error`
373			`flds fr5, fpul`
374			`sts fpul, r1`
375			`cmp/eq r0, r1`
376			`bf _vRegTest2Error`
377
378			`mov #17, r0`
379			`cmp/eq r0, r6`
380			`bf _vRegTest2Error`
381			`flds fr6, fpul`
382			`sts fpul, r1`
383			`cmp/eq r0, r1`
384			`bf _vRegTest2Error`
385
386			`mov #18, r0`
387			`cmp/eq r0, r7`
388			`bf _vRegTest2Error`
389			`flds fr7, fpul`
390			`sts fpul, r1`
391			`cmp/eq r0, r1`
392			`bf _vRegTest2Error`
393
394			`mov #19, r0`
395			`cmp/eq r0, r8`
396			`bf _vRegTest2Error`
397			`flds fr8, fpul`
398			`sts fpul, r1`
399			`cmp/eq r0, r1`
400			`bf _vRegTest2Error`
401
402			`mov #110, r0`
403			`cmp/eq r0, r9`
404			`bf _vRegTest2Error`
405			`flds fr9, fpul`
406			`sts fpul, r1`
407			`cmp/eq r0, r1`
408			`bf _vRegTest2Error`
409
410			`mov #111, r0`
411			`cmp/eq r0, r10`
412			`bf _vRegTest2Error`
413			`flds fr10, fpul`
414			`sts fpul, r1`
415			`cmp/eq r0, r1`
416			`bf _vRegTest2Error`
417
418			`mov #112, r0`
419			`cmp/eq r0, r11`
420			`bf _vRegTest2Error`
421			`flds fr11, fpul`
422			`sts fpul, r1`
423			`cmp/eq r0, r1`
424			`bf _vRegTest2Error`
425
426			`mov #113, r0`
427			`cmp/eq r0, r12`
428			`bf _vRegTest2Error`
429			`flds fr12, fpul`
430			`sts fpul, r1`
431			`cmp/eq r0, r1`
432			`bf _vRegTest2Error`
433
434			`mov #114, r0`
435			`cmp/eq r0, r13`
436			`bf _vRegTest2Error`
437			`flds fr13, fpul`
438			`sts fpul, r1`
439			`cmp/eq r0, r1`
440			`bf _vRegTest2Error`
441
442			`sts macl, r0`
443			`mov #115, r1`
444			`cmp/eq r0, r1`
445			`bf _vRegTest2Error`
446
447			`sts mach, r0`
448			`mov #116, r1`
449			`cmp/eq r0, r1`
450			`bf _vRegTest2Error`
451
452			`stc gbr, r0`
453			`mov #117, r1`
454			`cmp/eq r0, r1`
455			`bf _vRegTest2Error`
456
457			`; Increment the loop counter to indicate that this task is still running and`
458			`; still healthy.`
459			`mov.l #_ulRegTest2CycleCount, r0`
460			`mov.l @r0, r1`
461			`add #1, r1`
462			`mov.l r1, @r0`
463
464			`; Jump back to test all the registers again.`
465			`bra _vRegTest2Loop`
466			`nop`
467
468			`;-----------------------------------------------------------`
469
470			`_vRegTest2Error:`
471
472			`bra _vRegTest2Error`
473			`nop`
474
475
476			`.end`
477