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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [SuperH_SH7216_Renesas/] [RTOSDemo/] [vect.h] - Blame information for rev 607

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1 585 jeremybenn
/******************************************************************************
2
*   DISCLAIMER
3
*
4
*   This software is supplied by Renesas Technology Corp. and is only
5
*   intended for use with Renesas products. No other uses are authorized.
6
*
7
*   This software is owned by Renesas Technology Corp. and is protected under
8
*   all applicable laws, including copyright laws.
9
*
10
*   THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES
11
*   REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY,
12
*   INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
13
*   PARTICULAR PURPOSE AND NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY
14
*   DISCLAIMED.
15
*
16
*   TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
17
*   TECHNOLOGY CORP. NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
18
*   FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES
19
*   FOR ANY REASON RELATED TO THE THIS SOFTWARE, EVEN IF RENESAS OR ITS
20
*   AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
21
*
22
*   Renesas reserves the right, without notice, to make changes to this
23
*   software and to discontinue the availability of this software.
24
*   By using this software, you agree to the additional terms and
25
*   conditions found by accessing the following link:
26
*   http://www.renesas.com/disclaimer
27
********************************************************************************
28
*   Copyright (C) 2009. Renesas Technology Corp., All Rights Reserved.
29
*""FILE COMMENT""*********** Technical reference data **************************
30
*   System Name : SH7216 Sample Program
31
*   File Name   : vect.h
32
*   Abstract    : Definition of Vector
33
*   Version     : 0.02.00
34
*   Device      : SH7216
35
*   Tool-Chain  : High-performance Embedded Workshop (Ver.4.05.01).
36
*               : C/C++ compiler package for the SuperH RISC engine family
37
*               :                             (Ver.9.03 Release00).
38
*   OS          : None
39
*   H/W Platform: R0K572167 (CPU board)
40
*   Description :
41
********************************************************************************
42
*   History     : Mar.30,2009 Ver.0.02.00
43
*""FILE COMMENT END""**********************************************************/
44
#ifndef VECT_H
45
#define VECT_H
46
 
47
 
48
//;<<VECTOR DATA START (POWER ON RESET)>>
49
// 0 Power On Reset PC
50
extern void PowerON_Reset_PC(void);
51
 
52
//;<<VECTOR DATA END (POWER ON RESET)>>
53
// 1 Power On Reset SP
54
 
55
//;<<VECTOR DATA START (MANUAL RESET)>>
56
// 2 Manual Reset PC
57
extern void Manual_Reset_PC(void);
58
 
59
//;<<VECTOR DATA END (MANUAL RESET)>>
60
// 3 Manual Reset SP
61
 
62
// 4 Illegal code
63
#pragma interrupt INT_Illegal_code
64
extern void INT_Illegal_code(void);
65
 
66
// 5 Reserved
67
 
68
// 6 Illegal slot
69
#pragma interrupt INT_Illegal_slot
70
extern void INT_Illegal_slot(void);
71
 
72
// 7 Reserved
73
 
74
// 8 Reserved
75
 
76
// 9 CPU Address error
77
#pragma interrupt INT_CPU_Address
78
extern void INT_CPU_Address(void);
79
 
80
// 10 DMAC Address error
81
#pragma interrupt INT_DMAC_Address
82
extern void INT_DMAC_Address(void);
83
 
84
// 11 NMI
85
#pragma interrupt INT_NMI
86
extern void INT_NMI(void);
87
 
88
// 12 User breakpoint trap
89
#pragma interrupt INT_User_Break
90
extern void INT_User_Break(void);
91
 
92
// 13 Reserved
93
 
94
// 14 H-UDI
95
#pragma interrupt INT_HUDI
96
extern void INT_HUDI(void);
97
 
98
// 15 Register bank over
99
#pragma interrupt INT_Bank_Overflow
100
extern void INT_Bank_Overflow(void);
101
 
102
// 16 Register bank under
103
#pragma interrupt INT_Bank_Underflow
104
extern void INT_Bank_Underflow(void);
105
 
106
// 17 ZERO_DIV
107
#pragma interrupt INT_Divide_by_Zero
108
extern void INT_Divide_by_Zero(void);
109
 
110
// 18 OVER_DIV
111
#pragma interrupt INT_Divide_Overflow
112
extern void INT_Divide_Overflow(void);
113
 
114
// 19 Reserved
115
 
116
// 20 Reserved
117
 
118
// 21 Reserved
119
 
120
// 22 Reserved
121
 
122
// 23 Reserved
123
 
124
// 24 Reserved
125
 
126
// 25 Reserved
127
 
128
// 26 Reserved
129
 
130
// 27 Reserved
131
 
132
// 28 Reserved
133
 
134
// 29 Reserved
135
 
136
// 30 Reserved
137
 
138
// 31 Reserved
139
 
140
// 32 TRAPA (User Vecter)
141
#pragma interrupt INT_TRAPA32
142
extern void INT_TRAPA32(void);
143
 
144
// 33 TRAPA (User Vecter)
145
#pragma interrupt INT_TRAPA33
146
extern void INT_TRAPA33(void);
147
 
148
// 34 TRAPA (User Vecter)
149
#pragma interrupt INT_TRAPA34
150
extern void INT_TRAPA34(void);
151
 
152
// 35 TRAPA (User Vecter)
153
#pragma interrupt INT_TRAPA35
154
extern void INT_TRAPA35(void);
155
 
156
// 36 TRAPA (User Vecter)
157
#pragma interrupt INT_TRAPA36
158
extern void INT_TRAPA36(void);
159
 
160
// 37 TRAPA (User Vecter)
161
#pragma interrupt INT_TRAPA37
162
extern void INT_TRAPA37(void);
163
 
164
// 38 TRAPA (User Vecter)
165
#pragma interrupt INT_TRAPA38
166
extern void INT_TRAPA38(void);
167
 
168
// 39 TRAPA (User Vecter)
169
#pragma interrupt INT_TRAPA39
170
extern void INT_TRAPA39(void);
171
 
172
// 40 TRAPA (User Vecter)
173
#pragma interrupt INT_TRAPA40
174
extern void INT_TRAPA40(void);
175
 
176
// 41 TRAPA (User Vecter)
177
#pragma interrupt INT_TRAPA41
178
extern void INT_TRAPA41(void);
179
 
180
// 42 TRAPA (User Vecter)
181
#pragma interrupt INT_TRAPA42
182
extern void INT_TRAPA42(void);
183
 
184
// 43 TRAPA (User Vecter)
185
#pragma interrupt INT_TRAPA43
186
extern void INT_TRAPA43(void);
187
 
188
// 44 TRAPA (User Vecter)
189
#pragma interrupt INT_TRAPA44
190
extern void INT_TRAPA44(void);
191
 
192
// 45 TRAPA (User Vecter)
193
#pragma interrupt INT_TRAPA45
194
extern void INT_TRAPA45(void);
195
 
196
// 46 TRAPA (User Vecter)
197
#pragma interrupt INT_TRAPA46
198
extern void INT_TRAPA46(void);
199
 
200
// 47 TRAPA (User Vecter)
201
#pragma interrupt INT_TRAPA47
202
extern void INT_TRAPA47(void);
203
 
204
// 48 TRAPA (User Vecter)
205
#pragma interrupt INT_TRAPA48
206
extern void INT_TRAPA48(void);
207
 
208
// 49 TRAPA (User Vecter)
209
#pragma interrupt INT_TRAPA49
210
extern void INT_TRAPA49(void);
211
 
212
// 50 TRAPA (User Vecter)
213
#pragma interrupt INT_TRAPA50
214
extern void INT_TRAPA50(void);
215
 
216
// 51 TRAPA (User Vecter)
217
#pragma interrupt INT_TRAPA51
218
extern void INT_TRAPA51(void);
219
 
220
// 52 TRAPA (User Vecter)
221
#pragma interrupt INT_TRAPA52
222
extern void INT_TRAPA52(void);
223
 
224
// 53 TRAPA (User Vecter)
225
#pragma interrupt INT_TRAPA53
226
extern void INT_TRAPA53(void);
227
 
228
// 54 TRAPA (User Vecter)
229
#pragma interrupt INT_TRAPA54
230
extern void INT_TRAPA54(void);
231
 
232
// 55 TRAPA (User Vecter)
233
#pragma interrupt INT_TRAPA55
234
extern void INT_TRAPA55(void);
235
 
236
// 56 TRAPA (User Vecter)
237
#pragma interrupt INT_TRAPA56
238
extern void INT_TRAPA56(void);
239
 
240
// 57 TRAPA (User Vecter)
241
#pragma interrupt INT_TRAPA57
242
extern void INT_TRAPA57(void);
243
 
244
// 58 TRAPA (User Vecter)
245
#pragma interrupt INT_TRAPA58
246
extern void INT_TRAPA58(void);
247
 
248
// 59 TRAPA (User Vecter)
249
#pragma interrupt INT_TRAPA59
250
extern void INT_TRAPA59(void);
251
 
252
// 60 TRAPA (User Vecter)
253
#pragma interrupt INT_TRAPA60
254
extern void INT_TRAPA60(void);
255
 
256
// 61 TRAPA (User Vecter)
257
#pragma interrupt INT_TRAPA61
258
extern void INT_TRAPA61(void);
259
 
260
// 62 TRAPA (User Vecter)
261
#pragma interrupt INT_TRAPA62
262
extern void INT_TRAPA62(void);
263
 
264
// 63 TRAPA (User Vecter)
265
#pragma interrupt INT_TRAPA63
266
extern void INT_TRAPA63(void);
267
 
268
// 64 Interrupt IRQ0
269
#pragma interrupt INT_IRQ0(resbank)
270
extern void INT_IRQ0(void);
271
 
272
// 65 Interrupt IRQ1
273
#pragma interrupt INT_IRQ1(resbank)
274
extern void INT_IRQ1(void);
275
 
276
// 66 Interrupt IRQ2
277
#pragma interrupt INT_IRQ2(resbank)
278
extern void INT_IRQ2(void);
279
 
280
// 67 Interrupt IRQ3
281
#pragma interrupt INT_IRQ3(resbank)
282
extern void INT_IRQ3(void);
283
 
284
// 68 Interrupt IRQ4
285
#pragma interrupt INT_IRQ4(resbank)
286
extern void INT_IRQ4(void);
287
 
288
// 69 Interrupt IRQ5
289
#pragma interrupt INT_IRQ5(resbank)
290
extern void INT_IRQ5(void);
291
 
292
// 70 Interrupt IRQ6
293
#pragma interrupt INT_IRQ6(resbank)
294
extern void INT_IRQ6(void);
295
 
296
// 71 Interrupt IRQ7
297
#pragma interrupt INT_IRQ7(resbank)
298
extern void INT_IRQ7(void);
299
 
300
// 72 Reserved
301
 
302
// 73 Reserved
303
 
304
// 74 Reserved
305
 
306
// 75 Reserved
307
 
308
// 76 Reserved
309
 
310
// 77 Reserved
311
 
312
// 78 Reserved
313
 
314
// 79 Reserved
315
 
316
// 80 Interrupt PINT0
317
#pragma interrupt INT_PINT0(resbank)
318
extern void INT_PINT0(void);
319
 
320
// 81 Interrupt PINT1
321
#pragma interrupt INT_PINT1(resbank)
322
extern void INT_PINT1(void);
323
 
324
// 82 Interrupt PINT2
325
#pragma interrupt INT_PINT2(resbank)
326
extern void INT_PINT2(void);
327
 
328
// 83 Interrupt PINT3
329
#pragma interrupt INT_PINT3(resbank)
330
extern void INT_PINT3(void);
331
 
332
// 84 Interrupt PINT4
333
#pragma interrupt INT_PINT4(resbank)
334
extern void INT_PINT4(void);
335
 
336
// 85 Interrupt PINT5
337
#pragma interrupt INT_PINT5(resbank)
338
extern void INT_PINT5(void);
339
 
340
// 86 Interrupt PINT6
341
#pragma interrupt INT_PINT6(resbank)
342
extern void INT_PINT6(void);
343
 
344
// 87 Interrupt PINT7
345
#pragma interrupt INT_PINT7(resbank)
346
extern void INT_PINT7(void);
347
 
348
// 88 Reserved
349
 
350
// 89 Reserved
351
 
352
// 90 Reserved
353
 
354
// 91 ROM FIFE
355
#pragma interrupt INT_ROM_FIFE(resbank)
356
extern void INT_ROM_FIFE(void);
357
 
358
// 92 A/D ADI0
359
#pragma interrupt INT_AD_ADI0(resbank)
360
extern void INT_AD_ADI0(void);
361
 
362
// 93 Reserved
363
 
364
// 94 Reserved
365
 
366
// 95 Reserved
367
 
368
// 96 A/D ADI1
369
#pragma interrupt INT_AD_ADI1(resbank)
370
extern void INT_AD_ADI1(void);
371
 
372
// 97 Reserved
373
 
374
// 98 Reserved
375
 
376
// 99 Reserved
377
 
378
// 100 Reserved
379
 
380
// 101 Reserved
381
 
382
// 102 Reserved
383
 
384
// 103 Reserved
385
 
386
// 104 RCANET0 ERS_0
387
#pragma interrupt INT_RCANET0_ERS_0
388
extern void INT_RCANET0_ERS_0(void);
389
 
390
// 105 RCANET0 OVR_0
391
#pragma interrupt INT_RCANET0_OVR_0
392
extern void INT_RCANET0_OVR_0(void);
393
 
394
// 106 RCANET0 RM01_0
395
#pragma interrupt INT_RCANET0_RM01_0
396
extern void INT_RCANET0_RM01_0(void);
397
 
398
// 107 RCANET0 SLE_0
399
#pragma interrupt INT_RCANET0_SLE_0
400
extern void INT_RCANET0_SLE_0(void);
401
 
402
// 108 DMAC0 DEI0
403
#pragma interrupt INT_DMAC0_DEI0(resbank)
404
extern void INT_DMAC0_DEI0(void);
405
 
406
// 109 DMAC0 HEI0
407
#pragma interrupt INT_DMAC0_HEI0(resbank)
408
extern void INT_DMAC0_HEI0(void);
409
 
410
// 110 Reserved
411
 
412
// 111 Reserved
413
 
414
// 112 DMAC1 DEI1
415
#pragma interrupt INT_DMAC1_DEI1(resbank)
416
extern void INT_DMAC1_DEI1(void);
417
 
418
// 113 DMAC1 HEI1
419
#pragma interrupt INT_DMAC1_HEI1(resbank)
420
extern void INT_DMAC1_HEI1(void);
421
 
422
// 114 Reserved
423
 
424
// 115 Reserved
425
 
426
// 116 DMAC2 DEI2
427
#pragma interrupt INT_DMAC2_DEI2(resbank)
428
extern void INT_DMAC2_DEI2(void);
429
 
430
// 117 DMAC2 HEI2
431
#pragma interrupt INT_DMAC2_HEI2(resbank)
432
extern void INT_DMAC2_HEI2(void);
433
 
434
// 118 Reserved
435
 
436
// 119 Reserved
437
 
438
// 120 DMAC3 DEI3
439
#pragma interrupt INT_DMAC3_DEI3(resbank)
440
extern void INT_DMAC3_DEI3(void);
441
 
442
// 121 DMAC3 HEI3
443
#pragma interrupt INT_DMAC3_HEI3(resbank)
444
extern void INT_DMAC3_HEI3(void);
445
 
446
// 122 Reserved
447
 
448
// 123 Reserved
449
 
450
// 124 DMAC4 DEI4
451
#pragma interrupt INT_DMAC4_DEI4(resbank)
452
extern void INT_DMAC4_DEI4(void);
453
 
454
// 125 DMAC4 HEI4
455
#pragma interrupt INT_DMAC4_HEI4(resbank)
456
extern void INT_DMAC4_HEI4(void);
457
 
458
// 126 Reserved
459
 
460
// 127 Reserved
461
 
462
// 128 DMAC5 DEI5
463
#pragma interrupt INT_DMAC5_DEI5(resbank)
464
extern void INT_DMAC5_DEI5(void);
465
 
466
// 129 DMAC5 HEI5
467
#pragma interrupt INT_DMAC5_HEI5(resbank)
468
extern void INT_DMAC5_HEI5(void);
469
 
470
// 130 Reserved
471
 
472
// 131 Reserved
473
 
474
// 132 DMAC6 DEI6
475
#pragma interrupt INT_DMAC6_DEI6(resbank)
476
extern void INT_DMAC6_DEI6(void);
477
 
478
// 133 DMAC6 HEI6
479
#pragma interrupt INT_DMAC6_HEI6(resbank)
480
extern void INT_DMAC6_HEI6(void);
481
 
482
// 134 Reserved
483
 
484
// 135 Reserved
485
 
486
// 136 DMAC7 DEI7
487
#pragma interrupt INT_DMAC7_DEI7(resbank)
488
extern void INT_DMAC7_DEI7(void);
489
 
490
// 137 DMAC7 HEI7
491
#pragma interrupt INT_DMAC7_HEI7(resbank)
492
extern void INT_DMAC7_HEI7(void);
493
 
494
// 138 Reserved
495
 
496
// 139 Reserved
497
 
498
// 140 CMT CMI0
499
#pragma interrupt INT_CMT_CMI0(resbank)
500
extern void INT_CMT_CMI0(void);
501
 
502
// 141 Reserved
503
 
504
// 142 Reserved
505
 
506
// 143 Reserved
507
 
508
// 144 CMT CMI1
509
#pragma interrupt INT_CMT_CMI1(resbank)
510
extern void INT_CMT_CMI1(void);
511
 
512
// 145 Reserved
513
 
514
// 146 Reserved
515
 
516
// 147 Reserved
517
 
518
// 148 BSC CMTI
519
#pragma interrupt INT_BSC_CMTI(resbank)
520
extern void INT_BSC_CMTI(void);
521
 
522
// 149 Reserved
523
 
524
// 150 USB EP4FULL
525
#pragma interrupt INT_USB_EP4FULL(resbank)
526
extern void INT_USB_EP4FULL(void);
527
 
528
// 151 USB EP5EMPTY
529
#pragma interrupt INT_USB_EP5EMPTY(resbank)
530
extern void INT_USB_EP5EMPTY(void);
531
 
532
// 152 WDT ITI
533
#pragma interrupt INT_WDT_ITI(resbank)
534
extern void INT_WDT_ITI(void);
535
 
536
// 153 E-DMAC EINT0
537
#pragma interrupt INT_EDMAC_EINT0(resbank)
538
extern void INT_EDMAC_EINT0(void);
539
 
540
// 154 USB EP1FULL
541
#pragma interrupt INT_USB_EP1FULL(resbank)
542
extern void INT_USB_EP1FULL(void);
543
 
544
// 155 USB EP2EMPTY
545
#pragma interrupt INT_USB_EP2EMPTY(resbank)
546
extern void INT_USB_EP2EMPTY(void);
547
 
548
// 156 MTU2 MTU0 TGI0A
549
#pragma interrupt INT_MTU2_MTU0_TGI0A(resbank)
550
extern void INT_MTU2_MTU0_TGI0A(void);
551
 
552
// 157 MTU2 MTU0 TGI0B
553
#pragma interrupt INT_MTU2_MTU0_TGI0B(resbank)
554
extern void INT_MTU2_MTU0_TGI0B(void);
555
 
556
// 158 MTU2 MTU0 TGI0C
557
#pragma interrupt INT_MTU2_MTU0_TGI0C(resbank)
558
extern void INT_MTU2_MTU0_TGI0C(void);
559
 
560
// 159 MTU2 MTU0 TGI0D
561
#pragma interrupt INT_MTU2_MTU0_TGI0D(resbank)
562
extern void INT_MTU2_MTU0_TGI0D(void);
563
 
564
// 160 MTU2 MTU0 TGI0V
565
#pragma interrupt INT_MTU2_MTU0_TGI0V(resbank)
566
extern void INT_MTU2_MTU0_TGI0V(void);
567
 
568
// 161 MTU2 MTU0 TGI0E
569
#pragma interrupt INT_MTU2_MTU0_TGI0E(resbank)
570
extern void INT_MTU2_MTU0_TGI0E(void);
571
 
572
// 162 MTU2 MTU0 TGI0F
573
#pragma interrupt INT_MTU2_MTU0_TGI0F(resbank)
574
extern void INT_MTU2_MTU0_TGI0F(void);
575
 
576
// 163 Reserved
577
 
578
// 164 MTU2 MTU1 TGI1A
579
#pragma interrupt INT_MTU2_MTU1_TGI1A(resbank)
580
extern void INT_MTU2_MTU1_TGI1A(void);
581
 
582
// 165 MTU2 MTU1 TGI1B
583
#pragma interrupt INT_MTU2_MTU1_TGI1B(resbank)
584
extern void INT_MTU2_MTU1_TGI1B(void);
585
 
586
// 166 Reserved 
587
 
588
// 167 Reserved
589
 
590
// 168 MTU2 MTU1 TGI1V
591
#pragma interrupt INT_MTU2_MTU1_TGI1V(resbank)
592
extern void INT_MTU2_MTU1_TGI1V(void);
593
 
594
// 169 MTU2 MTU1 TGI1U
595
#pragma interrupt INT_MTU2_MTU1_TGI1U(resbank)
596
extern void INT_MTU2_MTU1_TGI1U(void);
597
 
598
// 170 Reserved 
599
 
600
// 171 Reserved
601
 
602
// 172 MTU2 MTU2 TGI2A
603
#pragma interrupt INT_MTU2_MTU2_TGI2A(resbank)
604
extern void INT_MTU2_MTU2_TGI2A(void);
605
 
606
// 173 MTU2 MTU2 TGI2B
607
#pragma interrupt INT_MTU2_MTU2_TGI2B(resbank)
608
extern void INT_MTU2_MTU2_TGI2B(void);
609
 
610
// 174 Reserved 
611
 
612
// 175 Reserved
613
 
614
// 176 MTU2 MTU2 TGI2V
615
#pragma interrupt INT_MTU2_MTU2_TGI2V(resbank)
616
extern void INT_MTU2_MTU2_TGI2V(void);
617
 
618
// 177 MTU2 MTU2 TGI2U
619
#pragma interrupt INT_MTU2_MTU2_TGI2U(resbank)
620
extern void INT_MTU2_MTU2_TGI2U(void);
621
 
622
// 178 Reserved 
623
 
624
// 179 Reserved
625
 
626
// 180 MTU2 MTU3 TGI3A
627
#pragma interrupt INT_MTU2_MTU3_TGI3A(resbank)
628
extern void INT_MTU2_MTU3_TGI3A(void);
629
 
630
// 181 MTU2 MTU3 TGI3B
631
#pragma interrupt INT_MTU2_MTU3_TGI3B(resbank)
632
extern void INT_MTU2_MTU3_TGI3B(void);
633
 
634
// 182 MTU2 MTU3 TGI3C
635
#pragma interrupt INT_MTU2_MTU3_TGI3C(resbank)
636
extern void INT_MTU2_MTU3_TGI3C(void);
637
 
638
// 183 MTU2 MTU3 TGI3D
639
#pragma interrupt INT_MTU2_MTU3_TGI3D(resbank)
640
extern void INT_MTU2_MTU3_TGI3D(void);
641
 
642
// 184 MTU2 MTU3 TGI3V
643
#pragma interrupt INT_MTU2_MTU3_TGI3V(resbank)
644
extern void INT_MTU2_MTU3_TGI3V(void);
645
 
646
// 185 Reserved 
647
 
648
// 186 Reserved
649
 
650
// 187 Reserved 
651
 
652
// 188 MTU2 MTU4 TGI4A
653
#pragma interrupt INT_MTU2_MTU4_TGI4A(resbank)
654
extern void INT_MTU2_MTU4_TGI4A(void);
655
 
656
// 189 MTU2 MTU4 TGI4B
657
#pragma interrupt INT_MTU2_MTU4_TGI4B(resbank)
658
extern void INT_MTU2_MTU4_TGI4B(void);
659
 
660
// 190 MTU2 MTU4 TGI4C
661
#pragma interrupt INT_MTU2_MTU4_TGI4C(resbank)
662
extern void INT_MTU2_MTU4_TGI4C(void);
663
 
664
// 191 MTU2 MTU4 TGI4D
665
#pragma interrupt INT_MTU2_MTU4_TGI4D(resbank)
666
extern void INT_MTU2_MTU4_TGI4D(void);
667
 
668
// 192 MTU2 MTU4 TGI4V
669
#pragma interrupt INT_MTU2_MTU4_TGI4V(resbank)
670
extern void INT_MTU2_MTU4_TGI4V(void);
671
 
672
// 193 Reserved 
673
 
674
// 194 Reserved
675
 
676
// 195 Reserved 
677
 
678
// 196 MTU2 MTU5 TGI5U
679
#pragma interrupt INT_MTU2_MTU5_TGI5U(resbank)
680
extern void INT_MTU2_MTU5_TGI5U(void);
681
 
682
// 197 MTU2 MTU5 TGI5V
683
#pragma interrupt INT_MTU2_MTU5_TGI5V(resbank)
684
extern void INT_MTU2_MTU5_TGI5V(void);
685
 
686
// 198 MTU2 MTU5 TGI5W
687
#pragma interrupt INT_MTU2_MTU5_TGI5W(resbank)
688
extern void INT_MTU2_MTU5_TGI5W(void);
689
 
690
// 199 Reserved 
691
 
692
// 200 POE2 OEI1
693
#pragma interrupt INT_POE2_OEI1(resbank)
694
extern void INT_POE2_OEI1(void);
695
 
696
// 201 POE2 OEI2 
697
#pragma interrupt INT_POE2_OEI2(resbank)
698
extern void INT_POE2_OEI2(void);
699
 
700
// 202 Reserved 
701
 
702
// 203 Reserved
703
 
704
// 204 MTU2S MTU3S TGI3A 
705
#pragma interrupt INT_MTU2S_MTU3S_TGI3A(resbank)
706
extern void INT_MTU2S_MTU3S_TGI3A(void);
707
 
708
// 205 MTU2S MTU3S TGI3B
709
#pragma interrupt INT_MTU2S_MTU3S_TGI3B(resbank)
710
extern void INT_MTU2S_MTU3S_TGI3B(void);
711
 
712
// 206 MTU2S MTU3S TGI3C
713
#pragma interrupt INT_MTU2S_MTU3S_TGI3C(resbank)
714
extern void INT_MTU2S_MTU3S_TGI3C(void);
715
 
716
// 207 MTU2S MTU3S TGI3D 
717
#pragma interrupt INT_MTU2S_MTU3S_TGI3D(resbank)
718
extern void INT_MTU2S_MTU3S_TGI3D(void);
719
 
720
// 208 MTU2S MTU3S TGI3V
721
#pragma interrupt INT_MTU2S_MTU3S_TGI3V(resbank)
722
extern void INT_MTU2S_MTU3S_TGI3V(void);
723
 
724
// 209 Reserved 
725
 
726
// 210 Reserved 
727
 
728
// 211 Reserved
729
 
730
// 212 MTU2S MTU4S TGI4A 
731
#pragma interrupt INT_MTU2S_MTU4S_TGI4A(resbank)
732
extern void INT_MTU2S_MTU4S_TGI4A(void);
733
 
734
// 213 MTU2S MTU4S TGI4B 
735
#pragma interrupt INT_MTU2S_MTU4S_TGI4B(resbank)
736
extern void INT_MTU2S_MTU4S_TGI4B(void);
737
 
738
// 214 MTU2S MTU4S TGI4C
739
#pragma interrupt INT_MTU2S_MTU4S_TGI4C(resbank)
740
extern void INT_MTU2S_MTU4S_TGI4C(void);
741
 
742
// 215 MTU2S MTU4S TGI4D 
743
#pragma interrupt INT_MTU2S_MTU4S_TGI4D(resbank)
744
extern void INT_MTU2S_MTU4S_TGI4D(void);
745
 
746
// 216 MTU2S MTU4S TGI4V
747
#pragma interrupt INT_MTU2S_MTU4S_TGI4V(resbank)
748
extern void INT_MTU2S_MTU4S_TGI4V(void);
749
 
750
// 217 Reserved 
751
 
752
// 218 Reserved
753
 
754
// 219 Reserved 
755
 
756
// 220 MTU2S MTU5S TGI5U
757
#pragma interrupt INT_MTU2S_MTU5S_TGI5U(resbank)
758
extern void INT_MTU2S_MTU5S_TGI5U(void);
759
 
760
// 221 MTU2S MTU5S TGI5V
761
#pragma interrupt INT_MTU2S_MTU5S_TGI5V(resbank)
762
extern void INT_MTU2S_MTU5S_TGI5V(void);
763
 
764
// 222 MTU2S MTU5S TGI5W 
765
#pragma interrupt INT_MTU2S_MTU5S_TGI5W(resbank)
766
extern void INT_MTU2S_MTU5S_TGI5W(void);
767
 
768
// 223 Reserved
769
 
770
// 224 POE2 OEI3
771
#pragma interrupt INT_POE2_OEI3(resbank)
772
extern void INT_POE2_OEI3(void);
773
 
774
// 225 Reserved
775
 
776
// 226 USB USI0
777
#pragma interrupt INT_USB_USI0(resbank)
778
extern void INT_USB_USI0(void);
779
 
780
// 227 USB USI1
781
#pragma interrupt INT_USB_USI1(resbank)
782
extern void INT_USB_USI1(void);
783
 
784
// 228 IIC3 STPI
785
#pragma interrupt INT_IIC3_STPI(resbank)
786
extern void INT_IIC3_STPI(void);
787
 
788
// 229 IIC3 NAKI
789
#pragma interrupt INT_IIC3_NAKI(resbank)
790
extern void INT_IIC3_NAKI(void);
791
 
792
// 230 IIC3 RXI
793
#pragma interrupt INT_IIC3_RXI(resbank)
794
extern void INT_IIC3_RXI(void);
795
 
796
// 231 IIC3 TXI
797
#pragma interrupt INT_IIC3_TXI(resbank)
798
extern void INT_IIC3_TXI(void);
799
 
800
// 232 IIC3 TEI
801
#pragma interrupt INT_IIC3_TEI(resbank)
802
extern void INT_IIC3_TEI(void);
803
 
804
// 233 RSPI SPERI
805
#pragma interrupt INT_RSPI_SPERI(resbank)
806
extern void INT_RSPI_SPERI(void);
807
 
808
// 234 RSPI SPRXI
809
#pragma interrupt INT_RSPI_SPRXI(resbank)
810
extern void INT_RSPI_SPRXI(void);
811
 
812
// 235 RSPI SPTXI
813
#pragma interrupt INT_RSPI_SPTXI(resbank)
814
extern void INT_RSPI_SPTXI(void);
815
 
816
// 236 SCI SCI4 ERI4
817
#pragma interrupt INT_SCI_SCI4_ERI4(resbank)
818
extern void INT_SCI_SCI4_ERI4(void);
819
 
820
// 237 SCI SCI4 RXI4
821
#pragma interrupt INT_SCI_SCI4_RXI4(resbank)
822
extern void INT_SCI_SCI4_RXI4(void);
823
 
824
// 238 SCI SCI4 TXI4
825
#pragma interrupt INT_SCI_SCI4_TXI4(resbank)
826
extern void INT_SCI_SCI4_TXI4(void);
827
 
828
// 239 SCI SCI4 TEI4
829
#pragma interrupt INT_SCI_SCI4_TEI4(resbank)
830
extern void INT_SCI_SCI4_TEI4(void);
831
 
832
// 240 SCI SCI0 ERI0
833
#pragma interrupt INT_SCI_SCI0_ERI0(resbank)
834
extern void INT_SCI_SCI0_ERI0(void);
835
 
836
// 241 SCI SCI0 RXI0
837
#pragma interrupt INT_SCI_SCI0_RXI0(resbank)
838
extern void INT_SCI_SCI0_RXI0(void);
839
 
840
// 242 SCI SCI0 TXI0
841
#pragma interrupt INT_SCI_SCI0_TXI0(resbank)
842
extern void INT_SCI_SCI0_TXI0(void);
843
 
844
// 243 SCI SCI0 TEI0
845
#pragma interrupt INT_SCI_SCI0_TEI0(resbank)
846
extern void INT_SCI_SCI0_TEI0(void);
847
 
848
// 244 SCI SCI1 ERI1
849
#pragma interrupt INT_SCI_SCI1_ERI1(resbank)
850
extern void INT_SCI_SCI1_ERI1(void);
851
 
852
// 245 SCI SCI1 RXI1
853
#pragma interrupt INT_SCI_SCI1_RXI1(resbank)
854
extern void INT_SCI_SCI1_RXI1(void);
855
 
856
// 246 SCI SCI1 TXI1
857
#pragma interrupt INT_SCI_SCI1_TXI1(resbank)
858
extern void INT_SCI_SCI1_TXI1(void);
859
 
860
// 247 SCI SCI1 TEI1
861
#pragma interrupt INT_SCI_SCI1_TEI1(resbank)
862
extern void INT_SCI_SCI1_TEI1(void);
863
 
864
// 248 SCI SCI2 ERI2
865
#pragma interrupt INT_SCI_SCI2_ERI2(resbank)
866
extern void INT_SCI_SCI2_ERI2(void);
867
 
868
// 249 SCI SCI2 RXI2
869
#pragma interrupt INT_SCI_SCI2_RXI2(resbank)
870
extern void INT_SCI_SCI2_RXI2(void);
871
 
872
// 250 SCI SCI2 TXI2
873
#pragma interrupt INT_SCI_SCI2_TXI2(resbank)
874
extern void INT_SCI_SCI2_TXI2(void);
875
 
876
// 251 SCI SCI2 TEI2
877
#pragma interrupt INT_SCI_SCI2_TEI2(resbank)
878
extern void INT_SCI_SCI2_TEI2(void);
879
 
880
// 252 SCIF SCIF3 BRI3
881
#pragma interrupt INT_SCIF_SCIF3_BRI3(resbank)
882
extern void INT_SCIF_SCIF3_BRI3(void);
883
 
884
// 253 SCIF SCIF3 ERI3
885
#pragma interrupt INT_SCIF_SCIF3_ERI3(resbank)
886
extern void INT_SCIF_SCIF3_ERI3(void);
887
 
888
// 254 SCIF SCIF3 RXI3
889
#pragma interrupt INT_SCIF_SCIF3_RXI3(resbank)
890
extern void INT_SCIF_SCIF3_RXI3(void);
891
 
892
// 255 SCIF SCIF3 TXI3
893
#pragma interrupt INT_SCIF_SCIF3_TXI3(resbank)
894
extern void INT_SCIF_SCIF3_TXI3(void);
895
 
896
// Dummy
897
#pragma interrupt Dummy(resbank)
898
extern void Dummy(void);
899
 
900
#endif /* VECT_H */
901
 
902
/* End of File */

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