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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [SuperH_SH7216_Renesas/] [RTOSDemo/] [vecttbl.c] - Blame information for rev 607

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Line No. Rev Author Line
1 585 jeremybenn
/***********************************************************************/
2
/*                                                                     */
3
/*  FILE        :vecttbl.c                                             */
4
/*  DATE        :Sun, Dec 27, 2009                                     */
5
/*  DESCRIPTION :Initialize of Vector Table                            */
6
/*  CPU TYPE    :Other                                                 */
7
/*                                                                     */
8
/*  This file is generated by Renesas Project Generator (Ver.4.16).    */
9
/*                                                                     */
10
/***********************************************************************/
11
 
12
 
13
 
14
#include "vect.h"
15
 
16
extern void vPortStartFirstTask( void );
17
extern void vPortYieldHandler( void );
18
extern void vPortPreemptiveTick( void );
19
extern void vEMAC_ISR_Wrapper( void );
20
extern void MTU_Match( void );
21
 
22
#pragma section VECTTBL
23
 
24
void *RESET_Vectors[] = {
25
//;<<VECTOR DATA START (POWER ON RESET)>>
26
//;0 Power On Reset PC
27
    (void*)     PowerON_Reset_PC,
28
//;<<VECTOR DATA END (POWER ON RESET)>>
29
// 1 Power On Reset SP
30
    __secend("S"),
31
//;<<VECTOR DATA START (MANUAL RESET)>>
32
//;2 Manual Reset PC
33
    (void*)     Manual_Reset_PC,
34
//;<<VECTOR DATA END (MANUAL RESET)>>
35
// 3 Manual Reset SP
36
    __secend("S")
37
 
38
};
39
#pragma section INTTBL
40
void *INT_Vectors[] = {
41
// 4 Illegal code
42
    (void*) INT_Illegal_code,
43
// 5 Reserved
44
    (void*) Dummy,
45
// 6 Illegal slot
46
        (void*) INT_Illegal_slot,
47
// 7 Reserved
48
    (void*) Dummy,
49
// 8 Reserved
50
    (void*) Dummy,
51
// 9 CPU Address error
52
        (void*) INT_CPU_Address,
53
// 10 DMAC Address error
54
        (void*) INT_DMAC_Address,
55
// 11 NMI
56
        (void*) INT_NMI,
57
// 12 User breakpoint trap
58
        (void*) INT_User_Break,
59
// 13 Reserved
60
    (void*) Dummy,
61
// 14 H-UDI
62
        (void*) INT_HUDI,
63
// 15 Register bank over
64
    (void*) INT_Bank_Overflow,
65
// 16 Register bank under
66
    (void*) INT_Bank_Underflow,
67
// 17 ZERO_DIV
68
    (void*) INT_Divide_by_Zero,
69
// 18 OVER_DIV
70
    (void*) INT_Divide_Overflow,
71
// 19 Reserved
72
    (void*) Dummy,
73
// 20 Reserved
74
    (void*) Dummy,
75
// 21 Reserved
76
    (void*) Dummy,
77
// 22 Reserved
78
    (void*) Dummy,
79
// 23 Reserved
80
    (void*) Dummy,
81
// 24 Reserved
82
    (void*) Dummy,
83
// 25 Reserved
84
    (void*) Dummy,
85
// 26 Reserved
86
    (void*) Dummy,
87
// 27 Reserved
88
    (void*) Dummy,
89
// 28 Reserved
90
    (void*) Dummy,
91
// 29 Reserved
92
    (void*) Dummy,
93
// 30 Reserved
94
    (void*) Dummy,
95
// 31 Reserved
96
    (void*) Dummy,
97
// 32 TRAPA (User Vecter)
98
//   (void*) INT_TRAPA32,
99
        (void*) vPortStartFirstTask,
100
// 33 TRAPA (User Vecter)
101
//    (void*) INT_TRAPA33,
102
        (void*) vPortYieldHandler,
103
// 34 TRAPA (User Vecter)
104
    (void*) INT_TRAPA34,
105
// 35 TRAPA (User Vecter)
106
    (void*) INT_TRAPA35,
107
// 36 TRAPA (User Vecter)
108
    (void*) INT_TRAPA36,
109
// 37 TRAPA (User Vecter)
110
    (void*) INT_TRAPA37,
111
// 38 TRAPA (User Vecter)
112
    (void*) INT_TRAPA38,
113
// 39 TRAPA (User Vecter)
114
    (void*) INT_TRAPA39,
115
// 40 TRAPA (User Vecter)
116
    (void*) INT_TRAPA40,
117
// 41 TRAPA (User Vecter)
118
    (void*) INT_TRAPA41,
119
// 42 TRAPA (User Vecter)
120
    (void*) INT_TRAPA42,
121
// 43 TRAPA (User Vecter)
122
    (void*) INT_TRAPA43,
123
// 44 TRAPA (User Vecter)
124
    (void*) INT_TRAPA44,
125
// 45 TRAPA (User Vecter)
126
    (void*) INT_TRAPA45,
127
// 46 TRAPA (User Vecter)
128
    (void*) INT_TRAPA46,
129
// 47 TRAPA (User Vecter)
130
    (void*) INT_TRAPA47,
131
// 48 TRAPA (User Vecter)
132
    (void*) INT_TRAPA48,
133
// 49 TRAPA (User Vecter)
134
    (void*) INT_TRAPA49,
135
// 50 TRAPA (User Vecter)
136
    (void*) INT_TRAPA50,
137
// 51 TRAPA (User Vecter)
138
    (void*) INT_TRAPA51,
139
// 52 TRAPA (User Vecter)
140
    (void*) INT_TRAPA52,
141
// 53 TRAPA (User Vecter)
142
    (void*) INT_TRAPA53,
143
// 54 TRAPA (User Vecter)
144
    (void*) INT_TRAPA54,
145
// 55 TRAPA (User Vecter)
146
    (void*) INT_TRAPA55,
147
// 56 TRAPA (User Vecter)
148
    (void*) INT_TRAPA56,
149
// 57 TRAPA (User Vecter)
150
    (void*) INT_TRAPA57,
151
// 58 TRAPA (User Vecter)
152
    (void*) INT_TRAPA58,
153
// 59 TRAPA (User Vecter)
154
    (void*) INT_TRAPA59,
155
// 60 TRAPA (User Vecter)
156
    (void*) INT_TRAPA60,
157
// 61 TRAPA (User Vecter)
158
    (void*) INT_TRAPA61,
159
// 62 TRAPA (User Vecter)
160
    (void*) INT_TRAPA62,
161
// 63 TRAPA (User Vecter)
162
    (void*) INT_TRAPA63,
163
// 64 Interrupt IRQ0
164
        (void*) INT_IRQ0,
165
// 65 Interrupt IRQ1
166
        (void*) INT_IRQ1,
167
// 66 Interrupt IRQ2
168
        (void*) INT_IRQ2,
169
// 67 Interrupt IRQ3
170
        (void*) INT_IRQ3,
171
// 68 Interrupt IRQ4
172
        (void*) INT_IRQ4,
173
// 69 Interrupt IRQ5
174
        (void*) INT_IRQ5,
175
// 70 Interrupt IRQ6
176
        (void*) INT_IRQ6,
177
// 71 Interrupt IRQ7
178
        (void*) INT_IRQ7,
179
// 72 Reserved
180
    (void*) Dummy,
181
// 73 Reserved
182
    (void*) Dummy,
183
// 74 Reserved
184
    (void*) Dummy,
185
// 75 Reserved
186
    (void*) Dummy,
187
// 76 Reserved
188
    (void*) Dummy,
189
// 77 Reserved
190
    (void*) Dummy,
191
// 78 Reserved
192
    (void*) Dummy,
193
// 79 Reserved
194
    (void*) Dummy,
195
// 80 Interrupt PINT0
196
        (void*) INT_PINT0,
197
// 81 Interrupt PINT1
198
        (void*) INT_PINT1,
199
// 82 Interrupt PINT2
200
        (void*) INT_PINT2,
201
// 83 Interrupt PINT3
202
        (void*) INT_PINT3,
203
// 84 Interrupt PINT4
204
        (void*) INT_PINT4,
205
// 85 Interrupt PINT5
206
        (void*) INT_PINT5,
207
// 86 Interrupt PINT6
208
        (void*) INT_PINT6,
209
// 87 Interrupt PINT7
210
        (void*) INT_PINT7,
211
// 88 Reserved
212
    (void*) Dummy,
213
// 89 Reserved
214
    (void*) Dummy,
215
// 90 Reserved
216
    (void*) Dummy,
217
// 91 ROM FIFE
218
    (void*) INT_ROM_FIFE,
219
// 92 A/D ADI0
220
        (void*) INT_AD_ADI0,
221
// 93 Reserved
222
    (void*) Dummy,
223
// 94 Reserved
224
    (void*) Dummy,
225
// 95 Reserved
226
    (void*) Dummy,
227
// 96 A/D ADI1
228
        (void*) INT_AD_ADI1,
229
// 97 Reserved
230
    (void*) Dummy,
231
// 98 Reserved
232
    (void*) Dummy,
233
// 99 Reserved
234
    (void*) Dummy,
235
// 100 Reserved
236
    (void*) Dummy,
237
// 101 Reserved
238
    (void*) Dummy,
239
// 102 Reserved
240
    (void*) Dummy,
241
// 103 Reserved
242
    (void*) Dummy,
243
// 104 RCANET0 ERS_0
244
    (void*) INT_RCANET0_ERS_0,
245
// 105 RCANET0 OVR_0
246
    (void*) INT_RCANET0_OVR_0,
247
// 106 RCANET0 RM01_0
248
    (void*) INT_RCANET0_RM01_0,
249
// 107 RCANET0 SLE_0
250
    (void*) INT_RCANET0_SLE_0,
251
// 108 DMAC0 DEI0
252
        (void*) INT_DMAC0_DEI0,
253
// 109 DMAC0 HEI0
254
        (void*) INT_DMAC0_HEI0,
255
// 110 Reserved
256
    (void*) Dummy,
257
// 111 Reserved
258
    (void*) Dummy,
259
// 112 DMAC1 DEI1
260
        (void*) INT_DMAC1_DEI1,
261
// 113 DMAC1 HEI1
262
        (void*) INT_DMAC1_HEI1,
263
// 114 Reserved
264
    (void*) Dummy,
265
// 115 Reserved
266
    (void*) Dummy,
267
// 116 DMAC2 DEI2
268
        (void*) INT_DMAC2_DEI2,
269
// 117 DMAC2 HEI2
270
        (void*) INT_DMAC2_HEI2,
271
// 118 Reserved
272
    (void*) Dummy,
273
// 119 Reserved
274
    (void*) Dummy,
275
// 120 DMAC3 DEI3
276
        (void*) INT_DMAC3_DEI3,
277
// 121 DMAC3 HEI3
278
        (void*) INT_DMAC3_HEI3,
279
// 122 Reserved
280
    (void*) Dummy,
281
// 123 Reserved
282
    (void*) Dummy,
283
// 124 DMAC4 DEI4
284
        (void*) INT_DMAC4_DEI4,
285
// 125 DMAC4 HEI4
286
        (void*) INT_DMAC4_HEI4,
287
// 126 Reserved
288
    (void*) Dummy,
289
// 127 Reserved
290
    (void*) Dummy,
291
// 128 DMAC5 DEI5
292
        (void*) INT_DMAC5_DEI5,
293
// 129 DMAC5 HEI5
294
        (void*) INT_DMAC5_HEI5,
295
// 130 Reserved
296
    (void*) Dummy,
297
// 131 Reserved
298
    (void*) Dummy,
299
// 132 DMAC6 DEI6
300
        (void*) INT_DMAC6_DEI6,
301
// 133 DMAC6 HEI6
302
        (void*) INT_DMAC6_HEI6,
303
// 134 Reserved
304
    (void*) Dummy,
305
// 135 Reserved
306
    (void*) Dummy,
307
// 136 DMAC7 DEI7
308
        (void*) INT_DMAC7_DEI7,
309
// 137 DMAC7 HEI7
310
        (void*) INT_DMAC7_HEI7,
311
// 138 Reserved
312
    (void*) Dummy,
313
// 139 Reserved
314
    (void*) Dummy,
315
// 140 CMT CMI0
316
//      (void*) INT_CMT_CMI0,
317
        (void*) vPortPreemptiveTick,
318
// 141 Reserved
319
    (void*) Dummy,
320
// 142 Reserved
321
    (void*) Dummy,
322
// 143 Reserved
323
    (void*) Dummy,
324
// 144 CMT CMI1
325
        (void*) INT_CMT_CMI1,
326
// 145 Reserved
327
    (void*) Dummy,
328
// 146 Reserved
329
    (void*) Dummy,
330
// 147 Reserved
331
    (void*) Dummy,
332
// 148 BSC CMTI
333
        (void*) INT_BSC_CMTI,
334
// 149 Reserved
335
    (void*) Dummy,
336
// 150 USB EP4FULL
337
    (void*) INT_USB_EP4FULL,
338
// 151 USB EP5EMPTY
339
    (void*) INT_USB_EP5EMPTY,
340
// 152 WDT ITI
341
        (void*) INT_WDT_ITI,
342
// 153 E-DMAC EINT0
343
    (void*) vEMAC_ISR_Wrapper,
344
// 154 USB EP1FULL
345
    (void*) INT_USB_EP1FULL,
346
// 155 USB EP2EMPTY
347
    (void*) INT_USB_EP2EMPTY,
348
// 156 MTU2 MTU0 TGI0A
349
//      (void*) INT_MTU2_MTU0_TGI0A,
350
        (void*) MTU_Match,
351
// 157 MTU2 MTU0 TGI0B
352
        (void*) INT_MTU2_MTU0_TGI0B,
353
// 158 MTU2 MTU0 TGI0C
354
        (void*) INT_MTU2_MTU0_TGI0C,
355
// 159 MTU2 MTU0 TGI0D
356
        (void*) INT_MTU2_MTU0_TGI0D,
357
// 160 MTU2 MTU0 TGI0V
358
        (void*) INT_MTU2_MTU0_TGI0V,
359
// 161 MTU2 MTU0 TGI0E
360
        (void*) INT_MTU2_MTU0_TGI0E,
361
// 162 MTU2 MTU0 TGI0F
362
        (void*) INT_MTU2_MTU0_TGI0F,
363
// 163 Reserved
364
    (void*) Dummy,
365
// 164 MTU2 MTU1 TGI1A
366
        (void*) INT_MTU2_MTU1_TGI1A,
367
// 165 MTU2 MTU1 TGI1B
368
        (void*) INT_MTU2_MTU1_TGI1B,
369
// 166 Reserved 
370
    (void*) Dummy,
371
// 167 Reserved
372
    (void*) Dummy,
373
// 168 MTU2 MTU1 TGI1V
374
        (void*) INT_MTU2_MTU1_TGI1V,
375
// 169 MTU2 MTU1 TGI1U
376
        (void*) INT_MTU2_MTU1_TGI1U,
377
// 170 Reserved 
378
    (void*) Dummy,
379
// 171 Reserved
380
    (void*) Dummy,
381
// 172 MTU2 MTU2 TGI2A
382
        (void*) INT_MTU2_MTU2_TGI2A,
383
// 173 MTU2 MTU2 TGI2B
384
        (void*) INT_MTU2_MTU2_TGI2B,
385
// 174 Reserved 
386
    (void*) Dummy,
387
// 175 Reserved
388
    (void*) Dummy,
389
// 176 MTU2 MTU2 TGI2V
390
        (void*) INT_MTU2_MTU2_TGI2V,
391
// 177 MTU2 MTU2 TGI2U
392
        (void*) INT_MTU2_MTU2_TGI2U,
393
// 178 Reserved 
394
    (void*) Dummy,
395
// 179 Reserved
396
    (void*) Dummy,
397
// 180 MTU2 MTU3 TGI3A
398
        (void*) INT_MTU2_MTU3_TGI3A,
399
// 181 MTU2 MTU3 TGI3B
400
        (void*) INT_MTU2_MTU3_TGI3B,
401
// 182 MTU2 MTU3 TGI3C
402
        (void*) INT_MTU2_MTU3_TGI3C,
403
// 183 MTU2 MTU3 TGI3D
404
        (void*) INT_MTU2_MTU3_TGI3D,
405
// 184 MTU2 MTU3 TGI3V
406
        (void*) INT_MTU2_MTU3_TGI3V,
407
// 185 Reserved 
408
    (void*) Dummy,
409
// 186 Reserved
410
    (void*) Dummy,
411
// 187 Reserved 
412
    (void*) Dummy,
413
// 188 MTU2 MTU4 TGI4A
414
        (void*) INT_MTU2_MTU4_TGI4A,
415
// 189 MTU2 MTU4 TGI4B
416
        (void*) INT_MTU2_MTU4_TGI4B,
417
// 190 MTU2 MTU4 TGI4C
418
        (void*) INT_MTU2_MTU4_TGI4C,
419
// 191 MTU2 MTU4 TGI4D
420
        (void*) INT_MTU2_MTU4_TGI4D,
421
// 192 MTU2 MTU4 TGI4V
422
        (void*) INT_MTU2_MTU4_TGI4V,
423
// 193 Reserved 
424
    (void*) Dummy,
425
// 194 Reserved
426
    (void*) Dummy,
427
// 195 Reserved 
428
    (void*) Dummy,
429
// 196 MTU2 MTU5 TGI5U
430
        (void*) INT_MTU2_MTU5_TGI5U,
431
// 197 MTU2 MTU5 TGI5V
432
        (void*) INT_MTU2_MTU5_TGI5V,
433
// 198 MTU2 MTU5 TGI5W
434
        (void*) INT_MTU2_MTU5_TGI5W,
435
// 199 Reserved 
436
    (void*) Dummy,
437
// 200 POE2 OEI1
438
        (void*) INT_POE2_OEI1,
439
// 201 POE2 OEI2 
440
        (void*) INT_POE2_OEI2,
441
// 202 Reserved 
442
    (void*) Dummy,
443
// 203 Reserved
444
    (void*) Dummy,
445
// 204 MTU2S MTU3S TGI3A 
446
        (void*) INT_MTU2S_MTU3S_TGI3A,
447
// 205 MTU2S MTU3S TGI3B
448
        (void*) INT_MTU2S_MTU3S_TGI3B,
449
// 206 MTU2S MTU3S TGI3C
450
        (void*) INT_MTU2S_MTU3S_TGI3C,
451
// 207 MTU2S MTU3S TGI3D 
452
        (void*) INT_MTU2S_MTU3S_TGI3D,
453
// 208 MTU2S MTU3S TGI3V
454
        (void*) INT_MTU2S_MTU3S_TGI3V,
455
// 209 Reserved 
456
    (void*) Dummy,
457
// 210 Reserved 
458
    (void*) Dummy,
459
// 211 Reserved
460
    (void*) Dummy,
461
// 212 MTU2S MTU4S TGI4A 
462
        (void*) INT_MTU2S_MTU4S_TGI4A,
463
// 213 MTU2S MTU4S TGI4B 
464
        (void*) INT_MTU2S_MTU4S_TGI4B,
465
// 214 MTU2S MTU4S TGI4C 
466
        (void*) INT_MTU2S_MTU4S_TGI4C,
467
// 215 MTU2S MTU4S TGI4D 
468
        (void*) INT_MTU2S_MTU4S_TGI4D,
469
// 216 MTU2S MTU4S TGI4V 
470
        (void*) INT_MTU2S_MTU4S_TGI4V,
471
// 217 Reserved 
472
    (void*) Dummy,
473
// 218 Reserved
474
    (void*) Dummy,
475
// 219 Reserved 
476
    (void*) Dummy,
477
// 220 MTU2S MTU5S TGI5U 
478
        (void*) INT_MTU2S_MTU5S_TGI5U,
479
// 221 MTU2S MTU5S TGI5V
480
        (void*) INT_MTU2S_MTU5S_TGI5V,
481
// 222 MTU2S MTU5S TGI5W 
482
        (void*) INT_MTU2S_MTU5S_TGI5W,
483
// 223 Reserved
484
    (void*) Dummy,
485
// 224 POE2 OEI3
486
        (void*) INT_POE2_OEI3,
487
// 225 Reserved
488
    (void*) Dummy,
489
// 226 USB USI0 
490
    (void*) INT_USB_USI0,
491
// 227 USB USI1 
492
    (void*) INT_USB_USI1,
493
// 228 IIC3 STPI
494
        (void*) INT_IIC3_STPI,
495
// 229 IIC3 NAKI 
496
        (void*) INT_IIC3_NAKI,
497
// 230 IIC3 RXI 
498
        (void*) INT_IIC3_RXI,
499
// 231 IIC3 TXI
500
        (void*) INT_IIC3_TXI,
501
// 232 IIC3 TEI 
502
        (void*) INT_IIC3_TEI,
503
// 233 RSPI SPERI 
504
    (void*) INT_RSPI_SPERI,
505
// 234 RSPI SPRXI 
506
    (void*) INT_RSPI_SPRXI,
507
// 235 RSPI SPTXI
508
    (void*) INT_RSPI_SPTXI,
509
// 236 SCI SCI4 ERI4 
510
    (void*) INT_SCI_SCI4_ERI4,
511
// 237 SCI SCI4 RXI4 
512
    (void*) INT_SCI_SCI4_RXI4,
513
// 238 SCI SCI4 TXI4
514
    (void*) INT_SCI_SCI4_TXI4,
515
// 239 SCI SCI4 TEI4 
516
    (void*) INT_SCI_SCI4_TEI4,
517
// 240 SCI SCI0 ERI0
518
        (void*) INT_SCI_SCI0_ERI0,
519
// 241 SCI SCI0 RXI0
520
        (void*) INT_SCI_SCI0_RXI0,
521
// 242 SCI SCI0 TXI0
522
        (void*) INT_SCI_SCI0_TXI0,
523
// 243 SCI SCI0 TEI0
524
        (void*) INT_SCI_SCI0_TEI0,
525
// 244 SCI SCI1 ERI1
526
        (void*) INT_SCI_SCI1_ERI1,
527
// 245 SCI SCI1 RXI1
528
        (void*) INT_SCI_SCI1_RXI1,
529
// 246 SCI SCI1 TXI1
530
        (void*) INT_SCI_SCI1_TXI1,
531
// 247 SCI SCI1 TEI1
532
        (void*) INT_SCI_SCI1_TEI1,
533
// 248 SCI SCI2 ERI2
534
        (void*) INT_SCI_SCI2_ERI2,
535
// 249 SCI SCI2 RXI2
536
        (void*) INT_SCI_SCI2_RXI2,
537
// 250 SCI SCI2 TXI2
538
        (void*) INT_SCI_SCI2_TXI2,
539
// 251 SCI SCI2 TEI2
540
        (void*) INT_SCI_SCI2_TEI2,
541
// 252 SCIF SCIF3 BRI3
542
        (void*) INT_SCIF_SCIF3_BRI3,
543
// 253 SCIF SCIF3 ERI3
544
        (void*) INT_SCIF_SCIF3_ERI3,
545
// 254 SCIF SCIF3 RXI3
546
        (void*) INT_SCIF_SCIF3_RXI3,
547
// 255 SCIF SCIF3 TXI3
548
        (void*) INT_SCIF_SCIF3_TXI3,
549
// xx Reserved
550
    (void*) Dummy
551
};
552
 
553
/* End of File */

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