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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [WizNET_DEMO_GCC_ARM7/] [TCP.c] - Blame information for rev 596

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1 585 jeremybenn
/*
2
    FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
3
 
4
    ***************************************************************************
5
    *                                                                         *
6
    * If you are:                                                             *
7
    *                                                                         *
8
    *    + New to FreeRTOS,                                                   *
9
    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *
10
    *    + Looking for basic training,                                        *
11
    *    + Wanting to improve your FreeRTOS skills and productivity           *
12
    *                                                                         *
13
    * then take a look at the FreeRTOS books - available as PDF or paperback  *
14
    *                                                                         *
15
    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *
16
    *                  http://www.FreeRTOS.org/Documentation                  *
17
    *                                                                         *
18
    * A pdf reference manual is also available.  Both are usually delivered   *
19
    * to your inbox within 20 minutes to two hours when purchased between 8am *
20
    * and 8pm GMT (although please allow up to 24 hours in case of            *
21
    * exceptional circumstances).  Thank you for your support!                *
22
    *                                                                         *
23
    ***************************************************************************
24
 
25
    This file is part of the FreeRTOS distribution.
26
 
27
    FreeRTOS is free software; you can redistribute it and/or modify it under
28
    the terms of the GNU General Public License (version 2) as published by the
29
    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
30
    ***NOTE*** The exception to the GPL is included to allow you to distribute
31
    a combined work that includes FreeRTOS without being obliged to provide the
32
    source code for proprietary components outside of the FreeRTOS kernel.
33
    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
34
    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
35
    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
36
    more details. You should have received a copy of the GNU General Public
37
    License and the FreeRTOS license exception along with FreeRTOS; if not it
38
    can be viewed here: http://www.freertos.org/a00114.html and also obtained
39
    by writing to Richard Barry, contact details for whom are available on the
40
    FreeRTOS WEB site.
41
 
42
    1 tab == 4 spaces!
43
 
44
    http://www.FreeRTOS.org - Documentation, latest information, license and
45
    contact details.
46
 
47
    http://www.SafeRTOS.com - A version that is certified for use in safety
48
    critical systems.
49
 
50
    http://www.OpenRTOS.com - Commercial support, development, porting,
51
    licensing and training services.
52
*/
53
 
54
/*
55
        Changes from V3.2.3
56
 
57
        + Modified char* types to compile without warning when using GCC V4.0.1.
58
        + Corrected the address to which the MAC address is written.  Thanks to
59
          Bill Knight for this correction.
60
 
61
        Changes from V3.2.4
62
 
63
        + Changed the default MAC address to something more realistic.
64
 
65
*/
66
 
67
/* Standard includes. */
68
#include <stdlib.h>
69
#include <string.h>
70
 
71
/* Scheduler include files. */
72
#include "FreeRTOS.h"
73
#include "task.h"
74
#include "semphr.h"
75
#include "tcp.h"
76
#include "serial.h"
77
 
78
/* Application includes. */
79
#include "i2c.h"
80
#include "html_pages.h"
81
 
82
/*-----------------------------------------------------------*/
83
 
84
/* Hardwired i2c address of the WIZNet device. */
85
#define tcpDEVICE_ADDRESS                               ( ( unsigned char ) 0x00 )
86
 
87
/* Constants used to configure the Tx and Rx buffer sizes within the WIZnet
88
device. */
89
#define tcp8K_RX                                                ( ( unsigned char ) 0x03 )
90
#define tcp8K_TX                                                ( ( unsigned char ) 0x03 )
91
 
92
/* Constants used to generate the WIZnet internal buffer addresses. */
93
#define tcpSINGLE_SOCKET_ADDR_MASK              ( ( unsigned long ) 0x1fff )
94
#define tcpSINGLE_SOCKET_ADDR_OFFSET    ( ( unsigned long ) 0x4000 )
95
 
96
/* Bit definitions of the commands that can be sent to the command register. */
97
#define tcpRESET_CMD                                    ( ( unsigned char ) 0x80 )
98
#define tcpSYS_INIT_CMD                                 ( ( unsigned char ) 0x01 )
99
#define tcpSOCK_STREAM                                  ( ( unsigned char ) 0x01 )
100
#define tcpSOCK_INIT                                    ( ( unsigned char ) 0x02 )
101
#define tcpLISTEN_CMD                                   ( ( unsigned char ) 0x08 )
102
#define tcpRECEIVE_CMD                                  ( ( unsigned char ) 0x40 )
103
#define tcpDISCONNECT_CMD                               ( ( unsigned char ) 0x10 )
104
#define tcpSEND_CMD                                             ( ( unsigned char ) 0x20 )
105
 
106
/* Constants required to handle the interrupts. */
107
#define tcpCLEAR_EINT0                                  ( 1 )
108
#define i2cCLEAR_ALL_INTERRUPTS                 ( ( unsigned char ) 0xff )
109
#define i2cCHANNEL_0_ISR_ENABLE                 ( ( unsigned char ) 0x01 )
110
#define i2cCHANNEL_0_ISR_DISABLE                ( ( unsigned char ) 0x00 )
111
#define tcpWAKE_ON_EINT0                                ( 1 )
112
#define tcpENABLE_EINT0_FUNCTION                ( ( unsigned long ) 0x01 )
113
#define tcpEINT0_VIC_CHANNEL_BIT                ( ( unsigned long ) 0x4000 )
114
#define tcpEINT0_VIC_CHANNEL                    ( ( unsigned long ) 14 )
115
#define tcpEINT0_VIC_ENABLE                             ( ( unsigned long ) 0x0020 )
116
 
117
/* Various delays used in the driver. */
118
#define tcpRESET_DELAY                                  ( ( portTickType ) 16 / portTICK_RATE_MS )
119
#define tcpINIT_DELAY                                   ( ( portTickType ) 500 / portTICK_RATE_MS  )
120
#define tcpLONG_DELAY                                   ( ( portTickType ) 500 / portTICK_RATE_MS  )
121
#define tcpSHORT_DELAY                                  ( ( portTickType ) 5 / portTICK_RATE_MS )
122
#define tcpCONNECTION_WAIT_DELAY                ( ( portTickType ) 100 / portTICK_RATE_MS )
123
#define tcpNO_DELAY                                             ( ( portTickType ) 0 )
124
 
125
/* Length of the data to read for various register reads. */
126
#define tcpSTATUS_READ_LEN                              ( ( unsigned long ) 1 )
127
#define tcpSHADOW_READ_LEN                              ( ( unsigned long ) 1 )
128
 
129
/* Register addresses within the WIZnet device. */
130
#define tcpCOMMAND_REG                                  ( ( unsigned short ) 0x0000 )
131
#define tcpGATEWAY_ADDR_REG                             ( ( unsigned short ) 0x0080 )
132
#define tcpSUBNET_MASK_REG                              ( ( unsigned short ) 0x0084 )
133
#define tcpSOURCE_HA_REG                                ( ( unsigned short ) 0x0088 )
134
#define tpcSOURCE_IP_REG                                ( ( unsigned short ) 0x008E )
135
#define tpcSOCKET_OPT_REG                               ( ( unsigned short ) 0x00A1 )
136
#define tcpSOURCE_PORT_REG                              ( ( unsigned short ) 0x00AE )
137
#define tcpTX_WRITE_POINTER_REG                 ( ( unsigned short ) 0x0040 )
138
#define tcpTX_READ_POINTER_REG                  ( ( unsigned short ) 0x0044 )
139
#define tcpTX_ACK_POINTER_REG                   ( ( unsigned short ) 0x0018 )
140
#define tcpTX_MEM_SIZE_REG                              ( ( unsigned short ) 0x0096 )
141
#define tcpRX_MEM_SIZE_REG                              ( ( unsigned short ) 0x0095 )
142
#define tcpINTERRUPT_STATUS_REG                 ( ( unsigned short ) 0x0004 )
143
#define tcpTX_WRITE_SHADOW_REG                  ( ( unsigned short ) 0x01F0 )
144
#define tcpTX_ACK_SHADOW_REG                    ( ( unsigned short ) 0x01E2 )
145
#define tcpISR_MASK_REG                                 ( ( unsigned short ) 0x0009 )
146
#define tcpINTERRUPT_REG                                ( ( unsigned short ) 0x0008 )
147
#define tcpSOCKET_STATE_REG                             ( ( unsigned short ) 0x00a0 )
148
 
149
/* Constants required for hardware setup. */
150
#define tcpRESET_ACTIVE_LOW                     ( ( unsigned long ) 0x20 )
151
#define tcpRESET_ACTIVE_HIGH                    ( ( unsigned long ) 0x10 )
152
 
153
/* Constants defining the source of the WIZnet ISR. */
154
#define tcpISR_SYS_INIT                                 ( ( unsigned char ) 0x01 )
155
#define tcpISR_SOCKET_INIT                              ( ( unsigned char ) 0x02 )
156
#define tcpISR_ESTABLISHED                              ( ( unsigned char ) 0x04 )
157
#define tcpISR_CLOSED                                   ( ( unsigned char ) 0x08 )
158
#define tcpISR_TIMEOUT                                  ( ( unsigned char ) 0x10 )
159
#define tcpISR_TX_COMPLETE                              ( ( unsigned char ) 0x20 )
160
#define tcpISR_RX_COMPLETE                              ( ( unsigned char ) 0x40 )
161
 
162
/* Constants defining the socket status bits. */
163
#define tcpSTATUS_ESTABLISHED                   ( ( unsigned char ) 0x06 )
164
#define tcpSTATUS_LISTEN                                ( ( unsigned char ) 0x02 )
165
 
166
/* Misc constants. */
167
#define tcpNO_STATUS_BITS                               ( ( unsigned char ) 0x00 )
168
#define i2cNO_ADDR_REQUIRED                             ( ( unsigned short ) 0x0000 )
169
#define i2cNO_DATA_REQUIRED                             ( 0x0000 )
170
#define tcpISR_QUEUE_LENGTH                             ( ( unsigned portBASE_TYPE ) 10 )
171
#define tcpISR_QUEUE_ITEM_SIZE                  ( ( unsigned portBASE_TYPE ) 0 )
172
#define tcpBUFFER_LEN                                   ( 4 * 1024 )
173
#define tcpMAX_REGISTER_LEN                             ( 4 )
174
#define tcpMAX_ATTEMPTS_TO_CHECK_BUFFER ( 6 )
175
#define tcpMAX_NON_LISTEN_STAUS_READS   ( 5 )
176
 
177
/* Message definitions.  The IP address, MAC address, gateway address, etc.
178
is set here! */
179
const unsigned char const ucDataGAR[]                           = { 172, 25, 218, 3 };  /* Gateway address. */
180
const unsigned char const ucDataMSR[]                           = { 255, 255, 255, 0 };  /* Subnet mask.         */
181
const unsigned char const ucDataSIPR[]                          = { 172, 25, 218, 201 };/* IP address.          */
182
const unsigned char const ucDataSHAR[]                          = { 00, 23, 30, 41, 15, 26 }; /* MAC address - DO NOT USE THIS ON A PUBLIC NETWORK! */
183
 
184
/* Other fixed messages. */
185
const unsigned char const ucDataReset[]                         = { tcpRESET_CMD };
186
const unsigned char const ucDataInit[]                          = { tcpSYS_INIT_CMD };
187
const unsigned char const ucDataProtocol[]                      = { tcpSOCK_STREAM };
188
const unsigned char const ucDataPort[]                          = { 0xBA, 0xCC };
189
const unsigned char const ucDataSockInit[]                      = { tcpSOCK_INIT };
190
const unsigned char const ucDataTxWritePointer[]        = { 0x11, 0x22, 0x00, 0x00 };
191
const unsigned char const ucDataTxAckPointer[]          = { 0x11, 0x22, 0x00, 0x00 };
192
const unsigned char const ucDataTxReadPointer[]         = { 0x11, 0x22, 0x00, 0x00 };
193
const unsigned char const ucDataListen[]                        = { tcpLISTEN_CMD };
194
const unsigned char const ucDataReceiveCmd[]            = { tcpRECEIVE_CMD };
195
const unsigned char const ucDataSetTxBufSize[]          = { tcp8K_TX };
196
const unsigned char const ucDataSetRxBufSize[]          = { tcp8K_RX };
197
const unsigned char const ucDataSend[]                          = { tcpSEND_CMD };
198
const unsigned char const ucDataDisconnect[]            = { tcpDISCONNECT_CMD };
199
const unsigned char const ucDataEnableISR[]                     = { i2cCHANNEL_0_ISR_ENABLE };
200
const unsigned char const ucDataDisableISR[]            = { i2cCHANNEL_0_ISR_DISABLE };
201
const unsigned char const ucDataClearInterrupt[]        = { i2cCLEAR_ALL_INTERRUPTS };
202
 
203
static xSemaphoreHandle xMessageComplete = NULL;
204
xQueueHandle xTCPISRQueue = NULL;
205
 
206
/* Dynamically generate and send an html page. */
207
static void prvSendSamplePage( void );
208
 
209
/* Read a register from the WIZnet device via the i2c interface. */
210
static void prvReadRegister( unsigned char *pucDestination, unsigned short usAddress, unsigned long ulLength );
211
 
212
/* Send the entire Tx buffer (the Tx buffer within the WIZnet device). */
213
static void prvFlushBuffer( unsigned long ulTxAddress );
214
 
215
/* Write a string to the WIZnet Tx buffer. */
216
static void prvWriteString( const char * const pucTxBuffer, long lTxLen, unsigned long *pulTxAddress );
217
 
218
/* Convert a number to a string. */
219
void ultoa( unsigned long ulVal, char *pcBuffer, long lIgnore );
220
 
221
/*-----------------------------------------------------------*/
222
 
223
void ultoa( unsigned long ulVal, char *pcBuffer, long lIgnore )
224
{
225
unsigned long lNibble;
226
long lIndex;
227
 
228
        /* Simple routine to convert an unsigned long value into a string in hex
229
        format. */
230
 
231
        /* For each nibble in the number we are converting. */
232
        for( lIndex = 0; lIndex < ( sizeof( ulVal ) * 2 ); lIndex++ )
233
        {
234
                /* Take the top four bits of the number. */
235
                lNibble = ( ulVal >> 28 );
236
 
237
                /* We are converting it to a hex string, so is the number in the range
238
                0-10 or A-F? */
239
                if( lNibble < 10 )
240
                {
241
                        pcBuffer[ lIndex ] = '0' + lNibble;
242
                }
243
                else
244
                {
245
                        lNibble -= 10;
246
                        pcBuffer[ lIndex ] = 'A' + lNibble;
247
                }
248
 
249
                /* Shift off the top nibble so we use the next nibble next time around. */
250
                ulVal <<= 4;
251
        }
252
 
253
        /* Mark the end of the string with a null terminator. */
254
        pcBuffer[ lIndex ] = 0x00;
255
}
256
/*-----------------------------------------------------------*/
257
 
258
static void prvReadRegister( unsigned char *pucDestination, unsigned short usAddress, unsigned long ulLength )
259
{
260
unsigned char ucRxBuffer[ tcpMAX_REGISTER_LEN ];
261
 
262
        /* Read a register value from the WIZnet device. */
263
 
264
        /* First write out the address of the register we want to read. */
265
        i2cMessage( ucRxBuffer, i2cNO_DATA_REQUIRED, tcpDEVICE_ADDRESS, usAddress, i2cWRITE, NULL, portMAX_DELAY );
266
 
267
        /* Then read back from that address. */
268
        i2cMessage( ( unsigned char * ) pucDestination, ulLength, tcpDEVICE_ADDRESS, i2cNO_ADDR_REQUIRED, i2cREAD, xMessageComplete, portMAX_DELAY );
269
 
270
        /* I2C messages are queued so use the semaphore to wait for the read to
271
        complete - otherwise we will leave this function before the I2C
272
        transactions have completed. */
273
        xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
274
}
275
/*-----------------------------------------------------------*/
276
 
277
void vTCPHardReset( void )
278
{
279
        /* Physical reset of the WIZnet device by using the GPIO lines to hold the
280
        WIZnet reset lines active for a few milliseconds. */
281
 
282
        /* Make sure the interrupt from the WIZnet is disabled. */
283
        VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
284
 
285
        /* If xMessageComplete is NULL then this is the first time that this
286
        function has been called and the queue and semaphore used in this file
287
        have not yet been created. */
288
        if( xMessageComplete == NULL )
289
        {
290
                /* Create and obtain the semaphore used when we want to wait for an i2c
291
                message to be completed. */
292
                vSemaphoreCreateBinary( xMessageComplete );
293
                xSemaphoreTake( xMessageComplete, tcpNO_DELAY );
294
 
295
                /* Create the queue used to communicate between the WIZnet and TCP tasks. */
296
                xTCPISRQueue = xQueueCreate( tcpISR_QUEUE_LENGTH, tcpISR_QUEUE_ITEM_SIZE );
297
        }
298
 
299
        /* Use the GPIO to reset the network hardware. */
300
        GPIO_IOCLR = tcpRESET_ACTIVE_LOW;
301
        GPIO_IOSET = tcpRESET_ACTIVE_HIGH;
302
 
303
        /* Delay with the network hardware in reset for a short while. */
304
        vTaskDelay( tcpRESET_DELAY );
305
 
306
        GPIO_IOCLR = tcpRESET_ACTIVE_HIGH;
307
        GPIO_IOSET = tcpRESET_ACTIVE_LOW;
308
 
309
        vTaskDelay( tcpINIT_DELAY );
310
 
311
        /* Setup the EINT0 to interrupt on required events from the WIZnet device.
312
        First enable the EINT0 function of the pin. */
313
        PCB_PINSEL1 |= tcpENABLE_EINT0_FUNCTION;
314
 
315
        /* We want the TCP comms to wake us from power save. */
316
        SCB_EXTWAKE = tcpWAKE_ON_EINT0;
317
 
318
        /* Install the ISR into the VIC - but don't enable it yet! */
319
        portENTER_CRITICAL();
320
        {
321
                extern void ( vEINT0_ISR_Wrapper )( void );
322
 
323
                VICIntSelect &= ~( tcpEINT0_VIC_CHANNEL_BIT );
324
                VICVectAddr3 = ( long ) vEINT0_ISR_Wrapper;
325
 
326
                VICVectCntl3 = tcpEINT0_VIC_CHANNEL | tcpEINT0_VIC_ENABLE;
327
        }
328
        portEXIT_CRITICAL();
329
 
330
        /* Enable interrupts in the WIZnet itself. */
331
        i2cMessage( ucDataEnableISR, sizeof( ucDataEnableISR ), tcpDEVICE_ADDRESS, tcpISR_MASK_REG, i2cWRITE, NULL, portMAX_DELAY );
332
 
333
        vTaskDelay( tcpLONG_DELAY );
334
}
335
/*-----------------------------------------------------------*/
336
 
337
long lTCPSoftReset( void )
338
{
339
unsigned char ucStatus;
340
extern volatile long lTransactionCompleted;
341
 
342
        /* Send a message to the WIZnet device to tell it set all it's registers
343
        back to their default states.  Then setup the WIZnet device as required. */
344
 
345
        /* Reset the internal WIZnet registers. */
346
        i2cMessage( ucDataReset,        sizeof( ucDataReset ),  tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
347
 
348
        /* Now we can configure the protocol.   Here the MAC address, gateway
349
        address, subnet mask and IP address are configured. */
350
        i2cMessage( ucDataSHAR,         sizeof( ucDataSHAR ),   tcpDEVICE_ADDRESS, tcpSOURCE_HA_REG, i2cWRITE, NULL, portMAX_DELAY );
351
        i2cMessage( ucDataGAR,          sizeof( ucDataGAR ),    tcpDEVICE_ADDRESS, tcpGATEWAY_ADDR_REG, i2cWRITE, NULL, portMAX_DELAY );
352
        i2cMessage( ucDataMSR,          sizeof( ucDataMSR ),    tcpDEVICE_ADDRESS, tcpSUBNET_MASK_REG,  i2cWRITE, NULL, portMAX_DELAY );
353
        i2cMessage( ucDataSIPR,         sizeof( ucDataSIPR ),   tcpDEVICE_ADDRESS, tpcSOURCE_IP_REG,    i2cWRITE, NULL, portMAX_DELAY );
354
 
355
        /* Next the memory buffers are configured to give all the WIZnet internal
356
        memory over to a single socket.  This gives the socket the maximum internal
357
        Tx and Rx buffer space. */
358
        i2cMessage( ucDataSetTxBufSize, sizeof( ucDataSetTxBufSize ), tcpDEVICE_ADDRESS, tcpTX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
359
        i2cMessage( ucDataSetRxBufSize, sizeof( ucDataSetRxBufSize ), tcpDEVICE_ADDRESS, tcpRX_MEM_SIZE_REG, i2cWRITE, NULL, portMAX_DELAY );
360
 
361
        /* Send the sys init command so the above parameters take effect. */
362
        i2cMessage( ucDataInit,         sizeof( ucDataInit ),   tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
363
 
364
        /* Seems to like a little wait here. */
365
        vTaskDelay( tcpINIT_DELAY );
366
 
367
        /* Read back the status to ensure the system initialised ok. */
368
        prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
369
 
370
        /* We should find that the sys init was successful. */
371
        if( ucStatus != tcpISR_SYS_INIT )
372
        {
373
                return ( long ) pdFAIL;
374
        }
375
 
376
        /* No i2c errors yet. */
377
        portENTER_CRITICAL();
378
                lTransactionCompleted = pdTRUE;
379
        portEXIT_CRITICAL();
380
 
381
        return ( long ) pdPASS;
382
}
383
/*-----------------------------------------------------------*/
384
 
385
long lTCPCreateSocket( void )
386
{
387
unsigned char ucStatus;
388
 
389
        /* Create and configure a socket. */
390
 
391
        /* Setup and init the socket.  Here the port number is set and the socket
392
        is initialised. */
393
        i2cMessage( ucDataProtocol, sizeof( ucDataProtocol),tcpDEVICE_ADDRESS, tpcSOCKET_OPT_REG, i2cWRITE, NULL, portMAX_DELAY );
394
        i2cMessage( ucDataPort,         sizeof( ucDataPort),    tcpDEVICE_ADDRESS, tcpSOURCE_PORT_REG, i2cWRITE, NULL, portMAX_DELAY );
395
        i2cMessage( ucDataSockInit, sizeof( ucDataSockInit),tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
396
 
397
        /* Wait for the Init command to be sent. */
398
        if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
399
        {
400
                /* For some reason the message was not transmitted within our block
401
                period. */
402
                return ( long ) pdFAIL;
403
        }
404
 
405
        /* Allow the socket to initialise. */
406
        vTaskDelay( tcpINIT_DELAY );
407
 
408
        /* Read back the status to ensure the socket initialised ok. */
409
        prvReadRegister( &ucStatus, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
410
 
411
        /* We should find that the socket init was successful. */
412
        if( ucStatus != tcpISR_SOCKET_INIT )
413
        {
414
                return ( long ) pdFAIL;
415
        }
416
 
417
 
418
        /* Setup the Tx pointer registers to indicate that the Tx buffer is empty. */
419
        i2cMessage( ucDataTxReadPointer, sizeof( ucDataTxReadPointer ), tcpDEVICE_ADDRESS, tcpTX_READ_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
420
        vTaskDelay( tcpSHORT_DELAY );
421
        i2cMessage( ucDataTxWritePointer, sizeof( ucDataTxWritePointer ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
422
        vTaskDelay( tcpSHORT_DELAY );
423
        i2cMessage( ucDataTxAckPointer,   sizeof( ucDataTxAckPointer ),   tcpDEVICE_ADDRESS, tcpTX_ACK_POINTER_REG, i2cWRITE, NULL, portMAX_DELAY );
424
        vTaskDelay( tcpSHORT_DELAY );
425
 
426
        return ( long ) pdPASS;
427
}
428
/*-----------------------------------------------------------*/
429
 
430
void vTCPListen( void )
431
{
432
unsigned char ucISR;
433
 
434
        /* Start a passive listen on the socket. */
435
 
436
        /* Enable interrupts in the WizNet device after ensuring none are
437
        currently pending. */
438
        while( SCB_EXTINT & tcpCLEAR_EINT0 )
439
        {
440
                /* The WIZnet device is still asserting and interrupt so tell it to
441
                clear. */
442
                i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
443
                xSemaphoreTake( xMessageComplete, tcpLONG_DELAY );
444
 
445
                vTaskDelay( 1 );
446
                SCB_EXTINT = tcpCLEAR_EINT0;
447
        }
448
 
449
        while( xQueueReceive( xTCPISRQueue, &ucISR, tcpNO_DELAY ) )
450
        {
451
                /* Just clearing the queue used by the ISR routine to tell this task
452
                that the WIZnet device needs attention. */
453
        }
454
 
455
        /* Now all the pending interrupts have been cleared we can enable the
456
        processor interrupts. */
457
        VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
458
 
459
        /* Then start listening for incoming connections. */
460
        i2cMessage( ucDataListen, sizeof( ucDataListen ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
461
}
462
/*-----------------------------------------------------------*/
463
 
464
long lProcessConnection( void )
465
{
466
unsigned char ucISR, ucState, ucLastState = 2, ucShadow;
467
extern volatile long lTransactionCompleted;
468
long lSameStateCount = 0, lDataSent = pdFALSE;
469
unsigned long ulWritePointer, ulAckPointer;
470
 
471
        /* No I2C errors can yet have occurred. */
472
        portENTER_CRITICAL();
473
                lTransactionCompleted = pdTRUE;
474
        portEXIT_CRITICAL();
475
 
476
        /* Keep looping - processing interrupts, until we have completed a
477
        transaction.   This uses the WIZnet in it's simplest form.  The socket
478
        accepts a connection - we process the connection - then close the socket.
479
        We then go back to reinitialise everything and start again. */
480
        while( lTransactionCompleted == pdTRUE )
481
        {
482
                /* Wait for a message on the queue from the WIZnet ISR.  When the
483
                WIZnet device asserts an interrupt the ISR simply posts a message
484
                onto this queue to wake this task. */
485
                if( xQueueReceive( xTCPISRQueue, &ucISR, tcpCONNECTION_WAIT_DELAY ) )
486
                {
487
                        /* The ISR posted a message on this queue to tell us that the
488
                        WIZnet device asserted an interrupt.  The ISR cannot process
489
                        an I2C message so cannot tell us what caused the interrupt so
490
                        we have to query the device here.  This task is the highest
491
                        priority in the system so will run immediately following the ISR. */
492
                        prvReadRegister( &ucISR, tcpINTERRUPT_STATUS_REG, tcpSTATUS_READ_LEN );
493
 
494
                        /* Once we have read what caused the ISR we can clear the interrupt
495
                        in the WIZnet. */
496
                        i2cMessage( ucDataClearInterrupt, sizeof( ucDataClearInterrupt ), tcpDEVICE_ADDRESS, tcpINTERRUPT_REG, i2cWRITE, NULL, portMAX_DELAY );
497
 
498
                        /* Now we can clear the processor interrupt and re-enable ready for
499
                        the next. */
500
                        SCB_EXTINT = tcpCLEAR_EINT0;
501
                        VICIntEnable |= tcpEINT0_VIC_CHANNEL_BIT;
502
 
503
                        /* Process the interrupt ... */
504
 
505
                        if( ucISR & tcpISR_ESTABLISHED )
506
                        {
507
                                /* A connection has been established - respond by sending
508
                                a receive command. */
509
                                i2cMessage( ucDataReceiveCmd, sizeof( ucDataReceiveCmd ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
510
                        }
511
 
512
                        if( ucISR & tcpISR_RX_COMPLETE )
513
                        {
514
                                /* We message has been received.  This will be an HTTP get
515
                                command.  We only have one page to send so just send it without
516
                                regard to what the actual requested page was. */
517
                                prvSendSamplePage();
518
                        }
519
 
520
                        if( ucISR & tcpISR_TX_COMPLETE )
521
                        {
522
                                /* We have a TX complete interrupt - which oddly does not
523
                                indicate that the message being sent is complete so we cannot
524
                                yet close the socket.  Instead we read the position of the Tx
525
                                pointer within the WIZnet device so we know how much data it
526
                                has to send.  Later we will read the ack pointer and compare
527
                                this to the Tx pointer to ascertain whether the transmission
528
                                has completed. */
529
 
530
                                /* First read the shadow register. */
531
                                prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
532
 
533
                                /* Now a short delay is required. */
534
                                vTaskDelay( tcpSHORT_DELAY );
535
 
536
                                /* Then we can read the real register. */
537
                                prvReadRegister( ( unsigned char * ) &ulWritePointer, tcpTX_WRITE_POINTER_REG, sizeof( ulWritePointer ) );
538
 
539
                                /* We cannot do anything more here but need to remember that
540
                                this interrupt has occurred. */
541
                                lDataSent = pdTRUE;
542
                        }
543
 
544
                        if( ucISR & tcpISR_CLOSED )
545
                        {
546
                                /* The socket has been closed so we can leave this function. */
547
                                lTransactionCompleted = pdFALSE;
548
                        }
549
                }
550
                else
551
                {
552
                        /* We have not received an interrupt from the WIZnet device for a
553
                        while.  Read the socket status and check that everything is as
554
                        expected. */
555
                        prvReadRegister( &ucState, tcpSOCKET_STATE_REG, tcpSTATUS_READ_LEN );
556
 
557
                        if( ( ucState == tcpSTATUS_ESTABLISHED ) && ( lDataSent > 0 ) )
558
                        {
559
                                /* The socket is established and we have already received a Tx
560
                                end interrupt.  We must therefore be waiting for the Tx buffer
561
                                inside the WIZnet device to be empty before we can close the
562
                                socket.
563
 
564
                                Read the Ack pointer register to see if it has caught up with
565
                                the Tx pointer register.  First we have to read the shadow
566
                                register. */
567
                                prvReadRegister( &ucShadow, tcpTX_ACK_SHADOW_REG, tcpSHADOW_READ_LEN );
568
                                vTaskDelay( tcpSHORT_DELAY );
569
                                prvReadRegister( ( unsigned char * ) &ulAckPointer, tcpTX_ACK_POINTER_REG, sizeof( ulWritePointer ) );
570
 
571
                                if( ulAckPointer == ulWritePointer )
572
                                {
573
                                        /* The Ack and write pointer are now equal and we can
574
                                        safely close the socket. */
575
                                        i2cMessage( ucDataDisconnect, sizeof( ucDataDisconnect ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, NULL, portMAX_DELAY );
576
                                }
577
                                else
578
                                {
579
                                        /* Keep a count of how many times we encounter the Tx
580
                                        buffer still containing data. */
581
                                        lDataSent++;
582
                                        if( lDataSent > tcpMAX_ATTEMPTS_TO_CHECK_BUFFER )
583
                                        {
584
                                                /* Assume we cannot complete sending the data and
585
                                                therefore cannot safely close the socket.  Start over. */
586
                                                vTCPHardReset();
587
                                                lTransactionCompleted = pdFALSE;
588
                                        }
589
                                }
590
                        }
591
                        else if( ucState != tcpSTATUS_LISTEN )
592
                        {
593
                                /* If we have not yet received a Tx end interrupt we would only
594
                                ever expect to find the socket still listening for any
595
                                sustained period. */
596
                                if( ucState == ucLastState )
597
                                {
598
                                        lSameStateCount++;
599
                                        if( lSameStateCount > tcpMAX_NON_LISTEN_STAUS_READS )
600
                                        {
601
                                                /* We are persistently in an unexpected state.  Assume
602
                                                we cannot safely close the socket and start over. */
603
                                                vTCPHardReset();
604
                                                lTransactionCompleted = pdFALSE;
605
                                        }
606
                                }
607
                        }
608
                        else
609
                        {
610
                                /* We are in the listen state so are happy that everything
611
                                is as expected. */
612
                                lSameStateCount = 0;
613
                        }
614
 
615
                        /* Remember what state we are in this time around so we can check
616
                        for a persistence on an unexpected state. */
617
                        ucLastState = ucState;
618
                }
619
        }
620
 
621
        /* We are going to reinitialise the WIZnet device so do not want our
622
        interrupts from the WIZnet to be processed. */
623
        VICIntEnClear |= tcpEINT0_VIC_CHANNEL_BIT;
624
        return lTransactionCompleted;
625
}
626
/*-----------------------------------------------------------*/
627
 
628
static void prvWriteString( const char * const pucTxBuffer, long lTxLen, unsigned long *pulTxAddress )
629
{
630
unsigned long ulSendAddress;
631
 
632
        /* Send a string to the Tx buffer internal to the WIZnet device. */
633
 
634
        /* Calculate the address to which we are going to write in the buffer. */
635
        ulSendAddress = ( *pulTxAddress & tcpSINGLE_SOCKET_ADDR_MASK ) + tcpSINGLE_SOCKET_ADDR_OFFSET;
636
 
637
        /* Send the buffer to the calculated address.  Use the semaphore so we
638
        can wait until the entire message has been transferred. */
639
        i2cMessage( ( unsigned char * ) pucTxBuffer, lTxLen, tcpDEVICE_ADDRESS, ( unsigned short ) ulSendAddress, i2cWRITE, xMessageComplete, portMAX_DELAY );
640
 
641
        /* Wait until the semaphore indicates that the message has been transferred. */
642
        if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
643
        {
644
                return;
645
        }
646
 
647
        /* Return the new address of the end of the buffer (within the WIZnet
648
        device). */
649
        *pulTxAddress += ( unsigned long ) lTxLen;
650
}
651
/*-----------------------------------------------------------*/
652
 
653
static void prvFlushBuffer( unsigned long ulTxAddress )
654
{
655
unsigned char ucTxBuffer[ tcpMAX_REGISTER_LEN ];
656
 
657
        /* We have written some data to the Tx buffer internal to the WIZnet
658
        device.  Now we update the Tx pointer inside the WIZnet then send a
659
        Send command - which causes     the data up to the new Tx pointer to be
660
        transmitted. */
661
 
662
        /* Make sure endieness is correct for transmission. */
663
        ulTxAddress = htonl( ulTxAddress );
664
 
665
        /* Place the new Tx pointer in the string to be transmitted. */
666
        ucTxBuffer[ 0 ] = ( unsigned char ) ( ulTxAddress & 0xff );
667
        ulTxAddress >>= 8;
668
        ucTxBuffer[ 1 ] = ( unsigned char ) ( ulTxAddress & 0xff );
669
        ulTxAddress >>= 8;
670
        ucTxBuffer[ 2 ] = ( unsigned char ) ( ulTxAddress & 0xff );
671
        ulTxAddress >>= 8;
672
        ucTxBuffer[ 3 ] = ( unsigned char ) ( ulTxAddress & 0xff );
673
        ulTxAddress >>= 8;
674
 
675
        /* And send it to the WIZnet device. */
676
        i2cMessage( ucTxBuffer, sizeof( ulTxAddress ), tcpDEVICE_ADDRESS, tcpTX_WRITE_POINTER_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
677
 
678
        if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
679
        {
680
                return;
681
        }
682
 
683
        vTaskDelay( tcpSHORT_DELAY );
684
 
685
        /* Transmit! */
686
        i2cMessage( ucDataSend, sizeof( ucDataSend ), tcpDEVICE_ADDRESS, tcpCOMMAND_REG, i2cWRITE, xMessageComplete, portMAX_DELAY );
687
 
688
        if( !xSemaphoreTake( xMessageComplete, tcpLONG_DELAY ) )
689
        {
690
                return;
691
        }
692
}
693
/*-----------------------------------------------------------*/
694
 
695
static void prvSendSamplePage( void )
696
{
697
extern long lErrorInTask;
698
unsigned long ulTxAddress;
699
unsigned char ucShadow;
700
long lIndex;
701
static unsigned long ulRefreshCount = 0x00;
702
static char cPageBuffer[ tcpBUFFER_LEN ];
703
 
704
 
705
        /* This function just generates a sample page of HTML which gets
706
        sent each time a client attaches to the socket.  The page is created
707
        from two fixed strings (cSamplePageFirstPart and cSamplePageSecondPart)
708
        with a bit of dynamically generated data in the middle. */
709
 
710
        /* We need to know the address to which the html string should be sent
711
        in the WIZnet Tx buffer.  First read the shadow register. */
712
        prvReadRegister( &ucShadow, tcpTX_WRITE_SHADOW_REG, tcpSHADOW_READ_LEN );
713
 
714
        /* Now a short delay is required. */
715
        vTaskDelay( tcpSHORT_DELAY );
716
 
717
        /* Now we can read the real pointer value. */
718
        prvReadRegister( ( unsigned char * ) &ulTxAddress, tcpTX_WRITE_POINTER_REG, sizeof( ulTxAddress ) );
719
 
720
        /* Make sure endieness is correct. */
721
        ulTxAddress = htonl( ulTxAddress );
722
 
723
        /* Send the start of the page. */
724
        prvWriteString( cSamplePageFirstPart, strlen( cSamplePageFirstPart ), &ulTxAddress );
725
 
726
        /* Generate a bit of dynamic data and place it in the buffer ready to be
727
        transmitted. */
728
        strcpy( cPageBuffer, "<BR>Number of ticks since boot = 0x" );
729
        lIndex = strlen( cPageBuffer );
730
        ultoa( xTaskGetTickCount(), &( cPageBuffer[ lIndex ] ), 0 );
731
        strcat( cPageBuffer, "<br>Number of tasks executing = ");
732
        lIndex = strlen( cPageBuffer );
733
        ultoa( ( unsigned long ) uxTaskGetNumberOfTasks(), &( cPageBuffer[ lIndex ] ), 0 );
734
        strcat( cPageBuffer, "<br>IO port 0 state (used by flash tasks) = 0x" );
735
        lIndex = strlen( cPageBuffer );
736
        ultoa( ( unsigned long ) GPIO0_IOPIN, &( cPageBuffer[ lIndex ] ), 0 );
737
        strcat( cPageBuffer, "<br>Refresh = 0x" );
738
        lIndex = strlen( cPageBuffer );
739
        ultoa( ( unsigned long ) ulRefreshCount, &( cPageBuffer[ lIndex ] ), 0 );
740
 
741
        if( lErrorInTask )
742
        {
743
                strcat( cPageBuffer, "<p>An error has occurred in at least one task." );
744
        }
745
        else
746
        {
747
                strcat( cPageBuffer, "<p>All tasks executing without error." );
748
        }
749
 
750
        ulRefreshCount++;
751
 
752
        /* Send the dynamically generated string. */
753
        prvWriteString( cPageBuffer, strlen( cPageBuffer ), &ulTxAddress );
754
 
755
        /* Finish the page. */
756
        prvWriteString( cSamplePageSecondPart, strlen( cSamplePageSecondPart ), &ulTxAddress );
757
 
758
        /* Tell the WIZnet to send the data we have just written to its Tx buffer. */
759
        prvFlushBuffer( ulTxAddress );
760
}
761
 

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