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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [WizNET_DEMO_GCC_ARM7/] [boot.s] - Blame information for rev 591

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Line No. Rev Author Line
1 585 jeremybenn
        /* Sample initialization file */
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        .extern main
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        .extern exit
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        .text
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        .code 32
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        .align  0
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        .extern __bss_beg__
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        .extern __bss_end__
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        .extern __stack_end__
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        .extern __data_beg__
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        .extern __data_end__
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        .extern __data+beg_src__
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        .global start
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        .global endless_loop
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        /* Stack Sizes */
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    .set  UND_STACK_SIZE, 0x00000004
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    .set  ABT_STACK_SIZE, 0x00000004
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    .set  FIQ_STACK_SIZE, 0x00000004
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    .set  IRQ_STACK_SIZE, 0X00000400
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    .set  SVC_STACK_SIZE, 0x00000400
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        /* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
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    .set  MODE_USR, 0x10            /* User Mode */
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    .set  MODE_FIQ, 0x11            /* FIQ Mode */
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    .set  MODE_IRQ, 0x12            /* IRQ Mode */
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    .set  MODE_SVC, 0x13            /* Supervisor Mode */
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    .set  MODE_ABT, 0x17            /* Abort Mode */
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    .set  MODE_UND, 0x1B            /* Undefined Mode */
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    .set  MODE_SYS, 0x1F            /* System Mode */
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    .equ  I_BIT, 0x80               /* when I bit is set, IRQ is disabled */
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    .equ  F_BIT, 0x40               /* when F bit is set, FIQ is disabled */
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start:
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_start:
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_mainCRTStartup:
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        /* Setup a stack for each mode - note that this only sets up a usable stack
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        for system/user, SWI and IRQ modes.   Also each mode is setup with
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        interrupts initially disabled. */
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    ldr   r0, .LC6
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    msr   CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
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    mov   sp, r0
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    sub   r0, r0, #UND_STACK_SIZE
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    msr   CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
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    mov   sp, r0
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    sub   r0, r0, #ABT_STACK_SIZE
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    msr   CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
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    mov   sp, r0
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    sub   r0, r0, #FIQ_STACK_SIZE
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    msr   CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
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    mov   sp, r0
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    sub   r0, r0, #IRQ_STACK_SIZE
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    msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
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    mov   sp, r0
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    sub   r0, r0, #SVC_STACK_SIZE
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    msr   CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */
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    mov   sp, r0
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        /* We want to start in supervisor mode.  Operation will switch to system
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        mode when the first task starts. */
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        msr   CPSR_c, #MODE_SVC|I_BIT|F_BIT
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        /* Clear BSS. */
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        mov     a2, #0                   /* Fill value */
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        mov             fp, a2                  /* Null frame pointer */
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        mov             r7, a2                  /* Null frame pointer for Thumb */
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        ldr             r1, .LC1                /* Start of memory block */
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        ldr             r3, .LC2                /* End of memory block */
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        subs    r3, r3, r1      /* Length of block */
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        beq             .end_clear_loop
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        mov             r2, #0
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.clear_loop:
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        strb    r2, [r1], #1
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        subs    r3, r3, #1
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        bgt             .clear_loop
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.end_clear_loop:
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        /* Initialise data. */
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        ldr             r1, .LC3                /* Start of memory block */
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        ldr             r2, .LC4                /* End of memory block */
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        ldr             r3, .LC5
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        subs    r3, r3, r1              /* Length of block */
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        beq             .end_set_loop
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.set_loop:
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        ldrb    r4, [r2], #1
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        strb    r4, [r1], #1
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        subs    r3, r3, #1
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        bgt             .set_loop
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.end_set_loop:
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        mov             r0, #0          /* no arguments  */
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        mov             r1, #0          /* no argv either */
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        bl              main
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endless_loop:
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        b               endless_loop
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        .align 0
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        .LC1:
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        .word   __bss_beg__
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        .LC2:
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        .word   __bss_end__
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        .LC3:
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        .word   __data_beg__
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        .LC4:
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        .word   __data_beg_src__
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        .LC5:
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        .word   __data_end__
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        .LC6:
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        .word   __stack_end__
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        /* Setup vector table.  Note that undf, pabt, dabt, fiq just execute
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        a null loop. */
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.section .startup,"ax"
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         .code 32
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         .align 0
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        b     _start                                            /* reset - _start                       */
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        ldr   pc, _undf                                         /* undefined - _undf            */
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        ldr   pc, _swi                                          /* SWI - _swi                           */
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        ldr   pc, _pabt                                         /* program abort - _pabt        */
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        ldr   pc, _dabt                                         /* data abort - _dabt           */
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        nop                                                                     /* reserved                                     */
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        ldr   pc, [pc,#-0xFF0]                          /* IRQ - read the VIC           */
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        ldr   pc, _fiq                                          /* FIQ - _fiq                           */
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_undf:  .word __undf                    /* undefined                            */
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_swi:   .word vPortYieldProcessor       /* SWI                                          */
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_pabt:  .word __pabt                    /* program abort                        */
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_dabt:  .word __dabt                    /* data abort                           */
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_fiq:   .word __fiq                     /* FIQ                                          */
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__undf: b     .                         /* undefined                            */
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__pabt: b     .                         /* program abort                        */
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__dabt: b     .                         /* data abort                           */
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__fiq:  b     .                         /* FIQ                                          */

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