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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [WizNET_DEMO_GCC_ARM7/] [i2c.c] - Blame information for rev 800

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1 585 jeremybenn
/*
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    FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
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    ***************************************************************************
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    *                                                                         *
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    * If you are:                                                             *
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    *                                                                         *
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    *    + New to FreeRTOS,                                                   *
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    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *
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    *    + Looking for basic training,                                        *
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    *    + Wanting to improve your FreeRTOS skills and productivity           *
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    *                                                                         *
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    * then take a look at the FreeRTOS books - available as PDF or paperback  *
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    *                                                                         *
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    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *
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    *                  http://www.FreeRTOS.org/Documentation                  *
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    *                                                                         *
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    * A pdf reference manual is also available.  Both are usually delivered   *
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    * to your inbox within 20 minutes to two hours when purchased between 8am *
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    * and 8pm GMT (although please allow up to 24 hours in case of            *
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    * exceptional circumstances).  Thank you for your support!                *
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    *                                                                         *
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    ***************************************************************************
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    This file is part of the FreeRTOS distribution.
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    FreeRTOS is free software; you can redistribute it and/or modify it under
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    the terms of the GNU General Public License (version 2) as published by the
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    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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    ***NOTE*** The exception to the GPL is included to allow you to distribute
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    a combined work that includes FreeRTOS without being obliged to provide the
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    source code for proprietary components outside of the FreeRTOS kernel.
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    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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    more details. You should have received a copy of the GNU General Public
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    License and the FreeRTOS license exception along with FreeRTOS; if not it
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    can be viewed here: http://www.freertos.org/a00114.html and also obtained
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    by writing to Richard Barry, contact details for whom are available on the
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    FreeRTOS WEB site.
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    1 tab == 4 spaces!
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    http://www.FreeRTOS.org - Documentation, latest information, license and
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    contact details.
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    http://www.SafeRTOS.com - A version that is certified for use in safety
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    critical systems.
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    http://www.OpenRTOS.com - Commercial support, development, porting,
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    licensing and training services.
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*/
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/* Standard includes. */
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#include <stdlib.h>
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/* Scheduler include files. */
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#include "FreeRTOS.h"
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#include "queue.h"
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#include "semphr.h"
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/* Application includes. */
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#include "i2c.h"
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/*-----------------------------------------------------------*/
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/* Constants to setup the microcontroller IO. */
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#define mainSDA_ENABLE                  ( ( unsigned long ) 0x0040 )
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#define mainSCL_ENABLE                  ( ( unsigned long ) 0x0010 )
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/* Bit definitions within the I2CONCLR register. */
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#define i2cSTA_BIT                              ( ( unsigned char ) 0x20 )
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#define i2cSI_BIT                               ( ( unsigned char ) 0x08 )
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#define i2cSTO_BIT                              ( ( unsigned char ) 0x10 )
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/* Constants required to setup the VIC. */
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#define i2cI2C_VIC_CHANNEL              ( ( unsigned long ) 0x0009 )
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#define i2cI2C_VIC_CHANNEL_BIT  ( ( unsigned long ) 0x0200 )
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#define i2cI2C_VIC_ENABLE               ( ( unsigned long ) 0x0020 )
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/* Misc constants. */
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#define i2cNO_BLOCK                             ( ( portTickType ) 0 )
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#define i2cQUEUE_LENGTH                 ( ( unsigned char ) 5 )
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#define i2cEXTRA_MESSAGES               ( ( unsigned char ) 2 )
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#define i2cREAD_TX_LEN                  ( ( unsigned long ) 2 )
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#define i2cACTIVE_MASTER_MODE   ( ( unsigned char ) 0x40 )
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#define i2cTIMERL                               ( 200 )
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#define i2cTIMERH                               ( 200 )
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/* Array of message definitions.  See the header file for more information
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on the structure members.  There are two more places in the queue than as
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defined by i2cQUEUE_LENGTH.  This is to ensure that there is always a free
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message available - one can be in the process of being transmitted and one
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can be left free. */
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static xI2CMessage xTxMessages[ i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ];
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/* Function in the ARM part of the code used to create the queues. */
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extern void vI2CISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxTxMessages, unsigned long **ppulBusFree );
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/* Index to the next free message in the xTxMessages array. */
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unsigned long ulNextFreeMessage = ( unsigned long ) 0;
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/* Queue of messages that are waiting transmission. */
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static xQueueHandle xMessagesForTx;
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/* Flag to indicate the state of the I2C ISR state machine. */
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static unsigned long *pulBusFree;
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/*-----------------------------------------------------------*/
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void i2cMessage( const unsigned char * const pucMessage, long lMessageLength, unsigned char ucSlaveAddress, unsigned short usBufferAddress, unsigned long ulDirection, xSemaphoreHandle xMessageCompleteSemaphore, portTickType xBlockTime )
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{
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extern volatile xI2CMessage *pxCurrentMessage;
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xI2CMessage *pxNextFreeMessage;
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signed portBASE_TYPE xReturn;
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        portENTER_CRITICAL();
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        {
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                /* This message is guaranteed to be free as there are two more messages
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                than spaces in the queue allowing for one message to be in process of
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                being transmitted and one to be left free. */
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                pxNextFreeMessage = &( xTxMessages[ ulNextFreeMessage ] );
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                /* Fill the message with the data to be sent. */
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                /* Pointer to the actual data.  Only a pointer is stored (i.e. the
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                actual data is not copied, so the data being pointed to must still
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                be valid when the message eventually gets sent (it may be queued for
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                a while. */
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                pxNextFreeMessage->pucBuffer = ( unsigned char * ) pucMessage;
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                /* This is the address of the I2C device we are going to transmit this
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                message to. */
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                pxNextFreeMessage->ucSlaveAddress = ucSlaveAddress | ( unsigned char ) ulDirection;
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                /* A semaphore can be used to allow the I2C ISR to indicate that the
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                message has been sent.  This can be NULL if you don't want to wait for
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                the message transmission to complete. */
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                pxNextFreeMessage->xMessageCompleteSemaphore = xMessageCompleteSemaphore;
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                /* How many bytes are to be sent? */
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                pxNextFreeMessage->lMessageLength = lMessageLength;
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                /* The address within the WIZnet device to which the data will be
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                written.  This could be the address of a register, or alternatively
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                a location within the WIZnet Tx buffer. */
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                pxNextFreeMessage->ucBufferAddressLowByte = ( unsigned char ) ( usBufferAddress & 0xff );
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                /* Second byte of the address. */
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                usBufferAddress >>= 8;
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                pxNextFreeMessage->ucBufferAddressHighByte = ( unsigned char ) ( usBufferAddress & 0xff );
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                /* Increment to the next message in the array - with a wrap around check. */
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                ulNextFreeMessage++;
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                if( ulNextFreeMessage >= ( i2cQUEUE_LENGTH + i2cEXTRA_MESSAGES ) )
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                {
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                        ulNextFreeMessage = ( unsigned long ) 0;
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                }
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                /* Is the I2C interrupt in the middle of transmitting a message? */
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                if( *pulBusFree == ( unsigned long ) pdTRUE )
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                {
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                        /* No message is currently being sent or queued to be sent.  We
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                        can start the ISR sending this message immediately. */
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                        pxCurrentMessage = pxNextFreeMessage;
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                        I2C_I2CONCLR = i2cSI_BIT;
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                        I2C_I2CONSET = i2cSTA_BIT;
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                        *pulBusFree = ( unsigned long ) pdFALSE;
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                }
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                else
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                {
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                        /* The I2C interrupt routine is mid sending a message.  Queue
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                        this message ready to be sent. */
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                        xReturn = xQueueSend( xMessagesForTx, &pxNextFreeMessage, xBlockTime );
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                        /* We may have blocked while trying to queue the message.  If this
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                        was the case then the interrupt would have been enabled and we may
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                        now find that the I2C interrupt routine is no longer sending a
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                        message. */
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                        if( ( *pulBusFree == ( unsigned long ) pdTRUE ) && ( xReturn == pdPASS ) )
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                        {
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                                /* Get the next message in the queue (this should be the
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                                message we just posted) and start off the transmission
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                                again. */
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                                xQueueReceive( xMessagesForTx, &pxNextFreeMessage, i2cNO_BLOCK );
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                                pxCurrentMessage = pxNextFreeMessage;
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                                I2C_I2CONCLR = i2cSI_BIT;
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                                I2C_I2CONSET = i2cSTA_BIT;
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                                *pulBusFree = ( unsigned long ) pdFALSE;
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                        }
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                }
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        }
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        portEXIT_CRITICAL();
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}
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/*-----------------------------------------------------------*/
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void i2cInit( void )
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{
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extern void ( vI2C_ISR_Wrapper )( void );
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        /* Create the queue used to send messages to the ISR. */
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        vI2CISRCreateQueues( i2cQUEUE_LENGTH, &xMessagesForTx, &pulBusFree );
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        /* Configure the I2C hardware. */
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        I2C_I2CONCLR = 0xff;
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        PCB_PINSEL0 |= mainSDA_ENABLE;
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        PCB_PINSEL0 |= mainSCL_ENABLE;
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        I2C_I2SCLL = i2cTIMERL;
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        I2C_I2SCLH = i2cTIMERH;
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        I2C_I2CONSET = i2cACTIVE_MASTER_MODE;
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        portENTER_CRITICAL();
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        {
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                /* Setup the VIC for the i2c interrupt. */
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                VICIntSelect &= ~( i2cI2C_VIC_CHANNEL_BIT );
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                VICIntEnable |= i2cI2C_VIC_CHANNEL_BIT;
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                VICVectAddr2 = ( long ) vI2C_ISR_Wrapper;
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                VICVectCntl2 = i2cI2C_VIC_CHANNEL | i2cI2C_VIC_ENABLE;
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        }
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        portEXIT_CRITICAL();
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}
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