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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [lwIP_AVR32_UC3/] [DRIVERS/] [PM/] [pm.c] - Blame information for rev 867

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1 583 jeremybenn
/*This file has been prepared for Doxygen automatic documentation generation.*/
2
/*! \file *********************************************************************
3
 *
4
 * \brief Power Manager driver.
5
 *
6
 *
7
 * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
8
 * - Supported devices:  All AVR32 devices.
9
 * - AppNote:
10
 *
11
 * \author               Atmel Corporation: http://www.atmel.com \n
12
 *                       Support and FAQ: http://support.atmel.no/
13
 *
14
 *****************************************************************************/
15
 
16
/* Copyright (c) 2007, Atmel Corporation All rights reserved.
17
 *
18
 * Redistribution and use in source and binary forms, with or without
19
 * modification, are permitted provided that the following conditions are met:
20
 *
21
 * 1. Redistributions of source code must retain the above copyright notice,
22
 * this list of conditions and the following disclaimer.
23
 *
24
 * 2. Redistributions in binary form must reproduce the above copyright notice,
25
 * this list of conditions and the following disclaimer in the documentation
26
 * and/or other materials provided with the distribution.
27
 *
28
 * 3. The name of ATMEL may not be used to endorse or promote products derived
29
 * from this software without specific prior written permission.
30
 *
31
 * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
32
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
33
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
34
 * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
35
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
36
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
37
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
38
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
39
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
40
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41
 */
42
 
43
 
44
#include "pm.h"
45
 
46
 
47
/*! \name PM Writable Bit-Field Registers
48
 */
49
//! @{
50
 
51
typedef union
52
{
53
  unsigned long                 mcctrl;
54
  avr32_pm_mcctrl_t             MCCTRL;
55
} u_avr32_pm_mcctrl_t;
56
 
57
typedef union
58
{
59
  unsigned long                 cksel;
60
  avr32_pm_cksel_t              CKSEL;
61
} u_avr32_pm_cksel_t;
62
 
63
typedef union
64
{
65
  unsigned long                 pll;
66
  avr32_pm_pll_t                PLL;
67
} u_avr32_pm_pll_t;
68
 
69
typedef union
70
{
71
  unsigned long                 oscctrl0;
72
  avr32_pm_oscctrl0_t           OSCCTRL0;
73
} u_avr32_pm_oscctrl0_t;
74
 
75
typedef union
76
{
77
  unsigned long                 oscctrl1;
78
  avr32_pm_oscctrl1_t           OSCCTRL1;
79
} u_avr32_pm_oscctrl1_t;
80
 
81
typedef union
82
{
83
  unsigned long                 oscctrl32;
84
  avr32_pm_oscctrl32_t          OSCCTRL32;
85
} u_avr32_pm_oscctrl32_t;
86
 
87
typedef union
88
{
89
  unsigned long                 ier;
90
  avr32_pm_ier_t                IER;
91
} u_avr32_pm_ier_t;
92
 
93
typedef union
94
{
95
  unsigned long                 idr;
96
  avr32_pm_idr_t                IDR;
97
} u_avr32_pm_idr_t;
98
 
99
typedef union
100
{
101
  unsigned long                 icr;
102
  avr32_pm_icr_t                ICR;
103
} u_avr32_pm_icr_t;
104
 
105
typedef union
106
{
107
  unsigned long                 gcctrl;
108
  avr32_pm_gcctrl_t             GCCTRL;
109
} u_avr32_pm_gcctrl_t;
110
 
111
typedef union
112
{
113
  unsigned long                 rccr;
114
  avr32_pm_rccr_t               RCCR;
115
} u_avr32_pm_rccr_t;
116
 
117
typedef union
118
{
119
  unsigned long                 bgcr;
120
  avr32_pm_bgcr_t               BGCR;
121
} u_avr32_pm_bgcr_t;
122
 
123
typedef union
124
{
125
  unsigned long                 vregcr;
126
  avr32_pm_vregcr_t             VREGCR;
127
} u_avr32_pm_vregcr_t;
128
 
129
typedef union
130
{
131
  unsigned long                 bod;
132
  avr32_pm_bod_t                BOD;
133
} u_avr32_pm_bod_t;
134
 
135
//! @}
136
 
137
 
138
/*! \brief Sets the mode of the oscillator 0.
139
 *
140
 * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
141
 * \param mode Oscillator 0 mode (i.e. AVR32_PM_OSCCTRL0_MODE_x).
142
 */
143
static void pm_set_osc0_mode(volatile avr32_pm_t *pm, unsigned int mode)
144
{
145
  // Read
146
  u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0};
147
  // Modify
148
  u_avr32_pm_oscctrl0.OSCCTRL0.mode = mode;
149
  // Write
150
  pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0;
151
}
152
 
153
 
154
void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm)
155
{
156
  pm_set_osc0_mode(pm, AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK);
157
}
158
 
159
 
160
void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0)
161
{
162
  pm_set_osc0_mode(pm, (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 :
163
                                           AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3);
164
}
165
 
166
 
167
void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup)
168
{
169
  pm_enable_clk0_no_wait(pm, startup);
170
  pm_wait_for_clk0_ready(pm);
171
}
172
 
173
 
174
void pm_disable_clk0(volatile avr32_pm_t *pm)
175
{
176
  pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC0EN_MASK;
177
}
178
 
179
 
180
void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
181
{
182
  // Read register
183
  u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0};
184
  // Modify
185
  u_avr32_pm_oscctrl0.OSCCTRL0.startup = startup;
186
  // Write back
187
  pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0;
188
 
189
  pm->mcctrl |= AVR32_PM_MCCTRL_OSC0EN_MASK;
190
}
191
 
192
 
193
void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm)
194
{
195
  while (!(pm->poscsr & AVR32_PM_POSCSR_OSC0RDY_MASK));
196
}
197
 
198
 
199
/*! \brief Sets the mode of the oscillator 1.
200
 *
201
 * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
202
 * \param mode Oscillator 1 mode (i.e. AVR32_PM_OSCCTRL1_MODE_x).
203
 */
204
static void pm_set_osc1_mode(volatile avr32_pm_t *pm, unsigned int mode)
205
{
206
  // Read
207
  u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1};
208
  // Modify
209
  u_avr32_pm_oscctrl1.OSCCTRL1.mode = mode;
210
  // Write
211
  pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1;
212
}
213
 
214
 
215
void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm)
216
{
217
  pm_set_osc1_mode(pm, AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK);
218
}
219
 
220
 
221
void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1)
222
{
223
  pm_set_osc1_mode(pm, (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 :
224
                                           AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3);
225
}
226
 
227
 
228
void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup)
229
{
230
  pm_enable_clk1_no_wait(pm, startup);
231
  pm_wait_for_clk1_ready(pm);
232
}
233
 
234
 
235
void pm_disable_clk1(volatile avr32_pm_t *pm)
236
{
237
  pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC1EN_MASK;
238
}
239
 
240
 
241
void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
242
{
243
  // Read register
244
  u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1};
245
  // Modify
246
  u_avr32_pm_oscctrl1.OSCCTRL1.startup = startup;
247
  // Write back
248
  pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1;
249
 
250
  pm->mcctrl |= AVR32_PM_MCCTRL_OSC1EN_MASK;
251
}
252
 
253
 
254
void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm)
255
{
256
  while (!(pm->poscsr & AVR32_PM_POSCSR_OSC1RDY_MASK));
257
}
258
 
259
 
260
/*! \brief Sets the mode of the 32-kHz oscillator.
261
 *
262
 * \param pm Base address of the Power Manager (i.e. &AVR32_PM).
263
 * \param mode 32-kHz oscillator mode (i.e. AVR32_PM_OSCCTRL32_MODE_x).
264
 */
265
static void pm_set_osc32_mode(volatile avr32_pm_t *pm, unsigned int mode)
266
{
267
  // Read
268
  u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32};
269
  // Modify
270
  u_avr32_pm_oscctrl32.OSCCTRL32.mode = mode;
271
  // Write
272
  pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32;
273
}
274
 
275
 
276
void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm)
277
{
278
  pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK);
279
}
280
 
281
 
282
void pm_enable_osc32_crystal(volatile avr32_pm_t *pm)
283
{
284
  pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_CRYSTAL);
285
}
286
 
287
 
288
void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup)
289
{
290
  pm_enable_clk32_no_wait(pm, startup);
291
  pm_wait_for_clk32_ready(pm);
292
}
293
 
294
 
295
void pm_disable_clk32(volatile avr32_pm_t *pm)
296
{
297
  pm->oscctrl32 &= ~AVR32_PM_OSCCTRL32_OSC32EN_MASK;
298
}
299
 
300
 
301
void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
302
{
303
  // Read register
304
  u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32};
305
  // Modify
306
  u_avr32_pm_oscctrl32.OSCCTRL32.osc32en = 1;
307
  u_avr32_pm_oscctrl32.OSCCTRL32.startup = startup;
308
  // Write back
309
  pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32;
310
}
311
 
312
 
313
void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm)
314
{
315
  while (!(pm->poscsr & AVR32_PM_POSCSR_OSC32RDY_MASK));
316
}
317
 
318
 
319
void pm_cksel(volatile avr32_pm_t *pm,
320
              unsigned int pbadiv,
321
              unsigned int pbasel,
322
              unsigned int pbbdiv,
323
              unsigned int pbbsel,
324
              unsigned int hsbdiv,
325
              unsigned int hsbsel)
326
{
327
  u_avr32_pm_cksel_t u_avr32_pm_cksel = {0};
328
 
329
  u_avr32_pm_cksel.CKSEL.cpusel = hsbsel;
330
  u_avr32_pm_cksel.CKSEL.cpudiv = hsbdiv;
331
  u_avr32_pm_cksel.CKSEL.hsbsel = hsbsel;
332
  u_avr32_pm_cksel.CKSEL.hsbdiv = hsbdiv;
333
  u_avr32_pm_cksel.CKSEL.pbasel = pbasel;
334
  u_avr32_pm_cksel.CKSEL.pbadiv = pbadiv;
335
  u_avr32_pm_cksel.CKSEL.pbbsel = pbbsel;
336
  u_avr32_pm_cksel.CKSEL.pbbdiv = pbbdiv;
337
 
338
  pm->cksel = u_avr32_pm_cksel.cksel;
339
 
340
  // Wait for ckrdy bit and then clear it
341
  while (!(pm->poscsr & AVR32_PM_POSCSR_CKRDY_MASK));
342
}
343
 
344
 
345
void pm_gc_setup(volatile avr32_pm_t *pm,
346
                  unsigned int gc,
347
                  unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1)
348
                  unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1
349
                  unsigned int diven,
350
                  unsigned int div)
351
{
352
  u_avr32_pm_gcctrl_t u_avr32_pm_gcctrl = {0};
353
 
354
  u_avr32_pm_gcctrl.GCCTRL.oscsel = pll_osc;
355
  u_avr32_pm_gcctrl.GCCTRL.pllsel = osc_or_pll;
356
  u_avr32_pm_gcctrl.GCCTRL.diven  = diven;
357
  u_avr32_pm_gcctrl.GCCTRL.div    = div;
358
 
359
  pm->gcctrl[gc] = u_avr32_pm_gcctrl.gcctrl;
360
}
361
 
362
 
363
void pm_gc_enable(volatile avr32_pm_t *pm,
364
                  unsigned int gc)
365
{
366
  pm->gcctrl[gc] |= AVR32_PM_GCCTRL_CEN_MASK;
367
}
368
 
369
 
370
void pm_gc_disable(volatile avr32_pm_t *pm,
371
                   unsigned int gc)
372
{
373
  pm->gcctrl[gc] &= ~AVR32_PM_GCCTRL_CEN_MASK;
374
}
375
 
376
 
377
void pm_pll_setup(volatile avr32_pm_t *pm,
378
                  unsigned int pll,
379
                  unsigned int mul,
380
                  unsigned int div,
381
                  unsigned int osc,
382
                  unsigned int lockcount)
383
{
384
  u_avr32_pm_pll_t u_avr32_pm_pll = {0};
385
 
386
  u_avr32_pm_pll.PLL.pllosc   = osc;
387
  u_avr32_pm_pll.PLL.plldiv   = div;
388
  u_avr32_pm_pll.PLL.pllmul   = mul;
389
  u_avr32_pm_pll.PLL.pllcount = lockcount;
390
 
391
  pm->pll[pll] = u_avr32_pm_pll.pll;
392
}
393
 
394
 
395
void pm_pll_set_option(volatile avr32_pm_t *pm,
396
                       unsigned int pll,
397
                       unsigned int pll_freq,
398
                       unsigned int pll_div2,
399
                       unsigned int pll_wbwdisable)
400
{
401
  u_avr32_pm_pll_t u_avr32_pm_pll = {pm->pll[pll]};
402
  u_avr32_pm_pll.PLL.pllopt = pll_freq | (pll_div2 << 1) | (pll_wbwdisable << 2);
403
  pm->pll[pll] = u_avr32_pm_pll.pll;
404
}
405
 
406
 
407
unsigned int pm_pll_get_option(volatile avr32_pm_t *pm,
408
                               unsigned int pll)
409
{
410
  return (pm->pll[pll] & AVR32_PM_PLLOPT_MASK) >> AVR32_PM_PLLOPT_OFFSET;
411
}
412
 
413
 
414
void pm_pll_enable(volatile avr32_pm_t *pm,
415
                  unsigned int pll)
416
{
417
  pm->pll[pll] |= AVR32_PM_PLLEN_MASK;
418
}
419
 
420
 
421
void pm_pll_disable(volatile avr32_pm_t *pm,
422
                  unsigned int pll)
423
{
424
  pm->pll[pll] &= ~AVR32_PM_PLLEN_MASK;
425
}
426
 
427
 
428
void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm)
429
{
430
  while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK0_MASK));
431
 
432
  // Bypass the lock signal of the PLL
433
  pm->pll[0] |= AVR32_PM_PLL0_PLLBPL_MASK;
434
}
435
 
436
 
437
void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm)
438
{
439
  while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK1_MASK));
440
 
441
  // Bypass the lock signal of the PLL
442
  pm->pll[1] |= AVR32_PM_PLL1_PLLBPL_MASK;
443
}
444
 
445
 
446
void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock)
447
{
448
  // Read
449
  u_avr32_pm_mcctrl_t u_avr32_pm_mcctrl = {pm->mcctrl};
450
  // Modify
451
  u_avr32_pm_mcctrl.MCCTRL.mcsel = clock;
452
  // Write back
453
  pm->mcctrl = u_avr32_pm_mcctrl.mcctrl;
454
}
455
 
456
 
457
void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup)
458
{
459
  pm_enable_osc0_crystal(pm, fosc0);            // Enable the Osc0 in crystal mode
460
  pm_enable_clk0(pm, startup);                  // Crystal startup time - This parameter is critical and depends on the characteristics of the crystal
461
  pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0);  // Then switch main clock to Osc0
462
}
463
 
464
 
465
void pm_bod_enable_irq(volatile avr32_pm_t *pm)
466
{
467
  pm->ier = AVR32_PM_IER_BODDET_MASK;
468
}
469
 
470
 
471
void pm_bod_disable_irq(volatile avr32_pm_t *pm)
472
{
473
  pm->idr = AVR32_PM_IDR_BODDET_MASK;
474
}
475
 
476
 
477
void pm_bod_clear_irq(volatile avr32_pm_t *pm)
478
{
479
  pm->icr = AVR32_PM_ICR_BODDET_MASK;
480
}
481
 
482
 
483
unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm)
484
{
485
  return ((pm->isr & AVR32_PM_ISR_BODDET_MASK) != 0);
486
}
487
 
488
 
489
unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm)
490
{
491
  return ((pm->imr & AVR32_PM_IMR_BODDET_MASK) != 0);
492
}
493
 
494
 
495
unsigned long pm_bod_get_level(volatile avr32_pm_t *pm)
496
{
497
  return (pm->bod & AVR32_PM_BOD_LEVEL_MASK) >> AVR32_PM_BOD_LEVEL_OFFSET;
498
}
499
 
500
 
501
void pm_write_gplp(volatile avr32_pm_t *pm,unsigned long gplp, unsigned long value)
502
{
503
  pm->gplp[gplp] = value;
504
}
505
 
506
 
507
unsigned long pm_read_gplp(volatile avr32_pm_t *pm,unsigned long gplp)
508
{
509
  return pm->gplp[gplp];
510
}

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