OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [lwIP_AVR32_UC3/] [DRIVERS/] [TC/] [tc.h] - Blame information for rev 583

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 583 jeremybenn
/*This file is prepared for Doxygen automatic documentation generation.*/
2
/*! \file *********************************************************************
3
 *
4
 * \brief Timer/Counter driver for AVR32 UC3.
5
 *
6
 * AVR32 Timer/Counter driver module.
7
 *
8
 * - Compiler:           IAR EWAVR32 and GNU GCC for AVR32
9
 * - Supported devices:  All AVR32 devices with a TC module can be used.
10
 * - AppNote:
11
 *
12
 * \author               Atmel Corporation: http://www.atmel.com \n
13
 *                       Support and FAQ: http://support.atmel.no/
14
 *
15
 ******************************************************************************/
16
 
17
/* Copyright (c) 2007, Atmel Corporation All rights reserved.
18
 *
19
 * Redistribution and use in source and binary forms, with or without
20
 * modification, are permitted provided that the following conditions are met:
21
 *
22
 * 1. Redistributions of source code must retain the above copyright notice,
23
 * this list of conditions and the following disclaimer.
24
 *
25
 * 2. Redistributions in binary form must reproduce the above copyright notice,
26
 * this list of conditions and the following disclaimer in the documentation
27
 * and/or other materials provided with the distribution.
28
 *
29
 * 3. The name of ATMEL may not be used to endorse or promote products derived
30
 * from this software without specific prior written permission.
31
 *
32
 * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
33
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
34
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
35
 * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
36
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
37
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
38
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
39
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
41
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42
 */
43
 
44
 
45
#ifndef _TC_H_
46
#define _TC_H_
47
 
48
#include <avr32/io.h>
49
 
50
 
51
//! TC driver functions return value in case of invalid argument(s).
52
#define TC_INVALID_ARGUMENT                     (-1)
53
 
54
//! Number of timer/counter channels.
55
#define TC_NUMBER_OF_CHANNELS                   (sizeof(((avr32_tc_t *)0)->channel) / sizeof(avr32_tc_channel_t))
56
 
57
/*! \name External Clock Signal 0 Selection
58
 */
59
//! @{
60
#define TC_CH0_EXT_CLK0_SRC_TCLK0               AVR32_TC_TC0XC0S_TCLK0
61
#define TC_CH0_EXT_CLK0_SRC_NO_CLK              AVR32_TC_TC0XC0S_NO_CLK
62
#define TC_CH0_EXT_CLK0_SRC_TIOA1               AVR32_TC_TC0XC0S_TIOA1
63
#define TC_CH0_EXT_CLK0_SRC_TIOA2               AVR32_TC_TC0XC0S_TIOA2
64
//! @}
65
 
66
/*! \name External Clock Signal 1 Selection
67
 */
68
//! @{
69
#define TC_CH1_EXT_CLK1_SRC_TCLK1               AVR32_TC_TC1XC1S_TCLK1
70
#define TC_CH1_EXT_CLK1_SRC_NO_CLK              AVR32_TC_TC1XC1S_NO_CLK
71
#define TC_CH1_EXT_CLK1_SRC_TIOA0               AVR32_TC_TC1XC1S_TIOA0
72
#define TC_CH1_EXT_CLK1_SRC_TIOA2               AVR32_TC_TC1XC1S_TIOA2
73
//! @}
74
 
75
/*! \name External Clock Signal 2 Selection
76
 */
77
//! @{
78
#define TC_CH2_EXT_CLK2_SRC_TCLK2               AVR32_TC_TC2XC2S_TCLK2
79
#define TC_CH2_EXT_CLK2_SRC_NO_CLK              AVR32_TC_TC2XC2S_NO_CLK
80
#define TC_CH2_EXT_CLK2_SRC_TIOA0               AVR32_TC_TC2XC2S_TIOA0
81
#define TC_CH2_EXT_CLK2_SRC_TIOA1               AVR32_TC_TC2XC2S_TIOA1
82
//! @}
83
 
84
/*! \name Event/Trigger Actions on Output
85
 */
86
//! @{
87
#define TC_EVT_EFFECT_NOOP                      AVR32_TC_NONE
88
#define TC_EVT_EFFECT_SET                       AVR32_TC_SET
89
#define TC_EVT_EFFECT_CLEAR                     AVR32_TC_CLEAR
90
#define TC_EVT_EFFECT_TOGGLE                    AVR32_TC_TOGGLE
91
//! @}
92
 
93
/*! \name RC Compare Trigger Enable
94
 */
95
//! @{
96
#define TC_NO_TRIGGER_COMPARE_RC                0
97
#define TC_TRIGGER_COMPARE_RC                   1
98
//! @}
99
 
100
/*! \name Waveform Selection
101
 */
102
//! @{
103
#define TC_WAVEFORM_SEL_UP_MODE                 AVR32_TC_WAVSEL_UP_NO_AUTO
104
#define TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER      AVR32_TC_WAVSEL_UP_AUTO
105
#define TC_WAVEFORM_SEL_UPDOWN_MODE             AVR32_TC_WAVSEL_UPDOWN_NO_AUTO
106
#define TC_WAVEFORM_SEL_UPDOWN_MODE_RC_TRIGGER  AVR32_TC_WAVSEL_UPDOWN_AUTO
107
//! @}
108
 
109
/*! \name TIOA or TIOB External Trigger Selection
110
 */
111
//! @{
112
#define TC_EXT_TRIG_SEL_TIOA                    1
113
#define TC_EXT_TRIG_SEL_TIOB                    0
114
//! @}
115
 
116
/*! \name External Event Selection
117
 */
118
//! @{
119
#define TC_EXT_EVENT_SEL_TIOB_INPUT             AVR32_TC_EEVT_TIOB_INPUT
120
#define TC_EXT_EVENT_SEL_XC0_OUTPUT             AVR32_TC_EEVT_XC0_OUTPUT
121
#define TC_EXT_EVENT_SEL_XC1_OUTPUT             AVR32_TC_EEVT_XC1_OUTPUT
122
#define TC_EXT_EVENT_SEL_XC2_OUTPUT             AVR32_TC_EEVT_XC2_OUTPUT
123
//! @}
124
 
125
/*! \name Edge Selection
126
 */
127
//! @{
128
#define TC_SEL_NO_EDGE                          AVR32_TC_EEVTEDG_NO_EDGE
129
#define TC_SEL_RISING_EDGE                      AVR32_TC_EEVTEDG_POS_EDGE
130
#define TC_SEL_FALLING_EDGE                     AVR32_TC_EEVTEDG_NEG_EDGE
131
#define TC_SEL_EACH_EDGE                        AVR32_TC_EEVTEDG_BOTH_EDGES
132
//! @}
133
 
134
/*! \name Burst Signal Selection
135
 */
136
//! @{
137
#define TC_BURST_NOT_GATED                      AVR32_TC_BURST_NOT_GATED
138
#define TC_BURST_CLK_AND_XC0                    AVR32_TC_BURST_CLK_AND_XC0
139
#define TC_BURST_CLK_AND_XC1                    AVR32_TC_BURST_CLK_AND_XC1
140
#define TC_BURST_CLK_AND_XC2                    AVR32_TC_BURST_CLK_AND_XC2
141
//! @}
142
 
143
/*! \name Clock Invert
144
 */
145
//! @{
146
#define TC_CLOCK_RISING_EDGE                    0
147
#define TC_CLOCK_FALLING_EDGE                   1
148
//! @}
149
 
150
/*! \name Clock Selection
151
 */
152
//! @{
153
#define TC_CLOCK_SOURCE_TC1                     AVR32_TC_TCCLKS_TIMER_DIV1_CLOCK
154
#define TC_CLOCK_SOURCE_TC2                     AVR32_TC_TCCLKS_TIMER_DIV2_CLOCK
155
#define TC_CLOCK_SOURCE_TC3                     AVR32_TC_TCCLKS_TIMER_DIV3_CLOCK
156
#define TC_CLOCK_SOURCE_TC4                     AVR32_TC_TCCLKS_TIMER_DIV4_CLOCK
157
#define TC_CLOCK_SOURCE_TC5                     AVR32_TC_TCCLKS_TIMER_DIV5_CLOCK
158
#define TC_CLOCK_SOURCE_XC0                     AVR32_TC_TCCLKS_XC0
159
#define TC_CLOCK_SOURCE_XC1                     AVR32_TC_TCCLKS_XC1
160
#define TC_CLOCK_SOURCE_XC2                     AVR32_TC_TCCLKS_XC2
161
//! @}
162
 
163
 
164
//! Timer/counter interrupts.
165
typedef struct
166
{
167
  unsigned int                 :24;
168
 
169
  //! External trigger interrupt.
170
  unsigned int etrgs           : 1;
171
 
172
  //! RB load interrupt.
173
  unsigned int ldrbs           : 1;
174
 
175
  //! RA load interrupt.
176
  unsigned int ldras           : 1;
177
 
178
  //! RC compare interrupt.
179
  unsigned int cpcs            : 1;
180
 
181
  //! RB compare interrupt.
182
  unsigned int cpbs            : 1;
183
 
184
  //! RA compare interrupt.
185
  unsigned int cpas            : 1;
186
 
187
  //! Load overrun interrupt.
188
  unsigned int lovrs           : 1;
189
 
190
  //! Counter overflow interrupt.
191
  unsigned int covfs           : 1;
192
} tc_interrupt_t;
193
 
194
//! Parameters when initializing a timer/counter in capture mode.
195
typedef struct
196
{
197
  //! Channel to initialize.
198
  unsigned int channel            ;
199
 
200
  unsigned int                 :12;
201
 
202
  //! RB loading selection:\n
203
  //!   - \ref TC_SEL_NO_EDGE;\n
204
  //!   - \ref TC_SEL_RISING_EDGE;\n
205
  //!   - \ref TC_SEL_FALLING_EDGE;\n
206
  //!   - \ref TC_SEL_EACH_EDGE.
207
  unsigned int ldrb            : 2;
208
 
209
  //! RA loading selection:\n
210
  //!   - \ref TC_SEL_NO_EDGE;\n
211
  //!   - \ref TC_SEL_RISING_EDGE;\n
212
  //!   - \ref TC_SEL_FALLING_EDGE;\n
213
  //!   - \ref TC_SEL_EACH_EDGE.
214
  unsigned int ldra            : 2;
215
 
216
  unsigned int                 : 1;
217
 
218
  //! RC compare trigger enable:\n
219
  //!   - \ref TC_NO_TRIGGER_COMPARE_RC;\n
220
  //!   - \ref TC_TRIGGER_COMPARE_RC.
221
  unsigned int cpctrg          : 1;
222
 
223
  unsigned int                 : 3;
224
 
225
  //! TIOA or TIOB external trigger selection:\n
226
  //!   - \ref TC_EXT_TRIG_SEL_TIOA;\n
227
  //!   - \ref TC_EXT_TRIG_SEL_TIOB.
228
  unsigned int abetrg          : 1;
229
 
230
  //! External trigger edge selection:\n
231
  //!   - \ref TC_SEL_NO_EDGE;\n
232
  //!   - \ref TC_SEL_RISING_EDGE;\n
233
  //!   - \ref TC_SEL_FALLING_EDGE;\n
234
  //!   - \ref TC_SEL_EACH_EDGE.
235
  unsigned int etrgedg         : 2;
236
 
237
  //! Counter clock disable with RB loading:\n
238
  //!   - \c FALSE;\n
239
  //!   - \c TRUE.
240
  unsigned int ldbdis          : 1;
241
 
242
  //! Counter clock stopped with RB loading:\n
243
  //!   - \c FALSE;\n
244
  //!   - \c TRUE.
245
  unsigned int ldbstop         : 1;
246
 
247
  //! Burst signal selection:\n
248
  //!   - \ref TC_BURST_NOT_GATED;\n
249
  //!   - \ref TC_BURST_CLK_AND_XC0;\n
250
  //!   - \ref TC_BURST_CLK_AND_XC1;\n
251
  //!   - \ref TC_BURST_CLK_AND_XC2.
252
  unsigned int burst           : 2;
253
 
254
  //! Clock invert:\n
255
  //!   - \ref TC_CLOCK_RISING_EDGE;\n
256
  //!   - \ref TC_CLOCK_FALLING_EDGE.
257
  unsigned int clki            : 1;
258
 
259
  //! Clock selection:\n
260
  //!   - \ref TC_CLOCK_SOURCE_TC1;\n
261
  //!   - \ref TC_CLOCK_SOURCE_TC2;\n
262
  //!   - \ref TC_CLOCK_SOURCE_TC3;\n
263
  //!   - \ref TC_CLOCK_SOURCE_TC4;\n
264
  //!   - \ref TC_CLOCK_SOURCE_TC5;\n
265
  //!   - \ref TC_CLOCK_SOURCE_XC0;\n
266
  //!   - \ref TC_CLOCK_SOURCE_XC1;\n
267
  //!   - \ref TC_CLOCK_SOURCE_XC2.
268
  unsigned int tcclks          : 3;
269
} tc_capture_opt_t;
270
 
271
//! Parameters when initializing a timer/counter in waveform mode.
272
typedef struct
273
{
274
  //! Channel to initialize.
275
  unsigned int channel            ;
276
 
277
  //! Software trigger effect on TIOB:\n
278
  //!   - \ref TC_EVT_EFFECT_NOOP;\n
279
  //!   - \ref TC_EVT_EFFECT_SET;\n
280
  //!   - \ref TC_EVT_EFFECT_CLEAR;\n
281
  //!   - \ref TC_EVT_EFFECT_TOGGLE.
282
  unsigned int bswtrg          : 2;
283
 
284
  //! External event effect on TIOB:\n
285
  //!   - \ref TC_EVT_EFFECT_NOOP;\n
286
  //!   - \ref TC_EVT_EFFECT_SET;\n
287
  //!   - \ref TC_EVT_EFFECT_CLEAR;\n
288
  //!   - \ref TC_EVT_EFFECT_TOGGLE.
289
  unsigned int beevt           : 2;
290
 
291
  //! RC compare effect on TIOB:\n
292
  //!   - \ref TC_EVT_EFFECT_NOOP;\n
293
  //!   - \ref TC_EVT_EFFECT_SET;\n
294
  //!   - \ref TC_EVT_EFFECT_CLEAR;\n
295
  //!   - \ref TC_EVT_EFFECT_TOGGLE.
296
  unsigned int bcpc            : 2;
297
 
298
  //! RB compare effect on TIOB:\n
299
  //!   - \ref TC_EVT_EFFECT_NOOP;\n
300
  //!   - \ref TC_EVT_EFFECT_SET;\n
301
  //!   - \ref TC_EVT_EFFECT_CLEAR;\n
302
  //!   - \ref TC_EVT_EFFECT_TOGGLE.
303
  unsigned int bcpb            : 2;
304
 
305
  //! Software trigger effect on TIOA:\n
306
  //!   - \ref TC_EVT_EFFECT_NOOP;\n
307
  //!   - \ref TC_EVT_EFFECT_SET;\n
308
  //!   - \ref TC_EVT_EFFECT_CLEAR;\n
309
  //!   - \ref TC_EVT_EFFECT_TOGGLE.
310
  unsigned int aswtrg          : 2;
311
 
312
  //! External event effect on TIOA:\n
313
  //!   - \ref TC_EVT_EFFECT_NOOP;\n
314
  //!   - \ref TC_EVT_EFFECT_SET;\n
315
  //!   - \ref TC_EVT_EFFECT_CLEAR;\n
316
  //!   - \ref TC_EVT_EFFECT_TOGGLE.
317
  unsigned int aeevt           : 2;
318
 
319
  //! RC compare effect on TIOA:\n
320
  //!   - \ref TC_EVT_EFFECT_NOOP;\n
321
  //!   - \ref TC_EVT_EFFECT_SET;\n
322
  //!   - \ref TC_EVT_EFFECT_CLEAR;\n
323
  //!   - \ref TC_EVT_EFFECT_TOGGLE.
324
  unsigned int acpc            : 2;
325
 
326
  //! RA compare effect on TIOA:\n
327
  //!   - \ref TC_EVT_EFFECT_NOOP;\n
328
  //!   - \ref TC_EVT_EFFECT_SET;\n
329
  //!   - \ref TC_EVT_EFFECT_CLEAR;\n
330
  //!   - \ref TC_EVT_EFFECT_TOGGLE.
331
  unsigned int acpa            : 2;
332
 
333
  unsigned int                 : 1;
334
 
335
  //! Waveform selection:\n
336
  //!   - \ref TC_WAVEFORM_SEL_UP_MODE;\n
337
  //!   - \ref TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER;\n
338
  //!   - \ref TC_WAVEFORM_SEL_UPDOWN_MODE;\n
339
  //!   - \ref TC_WAVEFORM_SEL_UPDOWN_MODE_RC_TRIGGER.
340
  unsigned int wavsel          : 2;
341
 
342
  //! External event trigger enable:\n
343
  //!   - \c FALSE;\n
344
  //!   - \c TRUE.
345
  unsigned int enetrg          : 1;
346
 
347
  //! External event selection:\n
348
  //!   - \ref TC_EXT_EVENT_SEL_TIOB_INPUT;\n
349
  //!   - \ref TC_EXT_EVENT_SEL_XC0_OUTPUT;\n
350
  //!   - \ref TC_EXT_EVENT_SEL_XC1_OUTPUT;\n
351
  //!   - \ref TC_EXT_EVENT_SEL_XC2_OUTPUT.
352
  unsigned int eevt            : 2;
353
 
354
  //! External event edge selection:\n
355
  //!   - \ref TC_SEL_NO_EDGE;\n
356
  //!   - \ref TC_SEL_RISING_EDGE;\n
357
  //!   - \ref TC_SEL_FALLING_EDGE;\n
358
  //!   - \ref TC_SEL_EACH_EDGE.
359
  unsigned int eevtedg         : 2;
360
 
361
  //! Counter clock disable with RC compare:\n
362
  //!   - \c FALSE;\n
363
  //!   - \c TRUE.
364
  unsigned int cpcdis          : 1;
365
 
366
  //! Counter clock stopped with RC compare:\n
367
  //!   - \c FALSE;\n
368
  //!   - \c TRUE.
369
  unsigned int cpcstop         : 1;
370
 
371
  //! Burst signal selection:\n
372
  //!   - \ref TC_BURST_NOT_GATED;\n
373
  //!   - \ref TC_BURST_CLK_AND_XC0;\n
374
  //!   - \ref TC_BURST_CLK_AND_XC1;\n
375
  //!   - \ref TC_BURST_CLK_AND_XC2.
376
  unsigned int burst           : 2;
377
 
378
  //! Clock invert:\n
379
  //!   - \ref TC_CLOCK_RISING_EDGE;\n
380
  //!   - \ref TC_CLOCK_FALLING_EDGE.
381
  unsigned int clki            : 1;
382
 
383
  //! Clock selection:\n
384
  //!   - \ref TC_CLOCK_SOURCE_TC1;\n
385
  //!   - \ref TC_CLOCK_SOURCE_TC2;\n
386
  //!   - \ref TC_CLOCK_SOURCE_TC3;\n
387
  //!   - \ref TC_CLOCK_SOURCE_TC4;\n
388
  //!   - \ref TC_CLOCK_SOURCE_TC5;\n
389
  //!   - \ref TC_CLOCK_SOURCE_XC0;\n
390
  //!   - \ref TC_CLOCK_SOURCE_XC1;\n
391
  //!   - \ref TC_CLOCK_SOURCE_XC2.
392
  unsigned int tcclks          : 3;
393
} tc_waveform_opt_t;
394
 
395
 
396
/*! \brief Reads timer/counter interrupt settings.
397
 *
398
 * \param tc              Pointer to the TC instance to access.
399
 * \param channel         The TC instance channel to access.
400
 *
401
 * \retval >=0 The interrupt enable configuration organized according to \ref tc_interrupt_t.
402
 * \retval TC_INVALID_ARGUMENT Invalid argument(s).
403
 */
404
extern int tc_get_interrupt_settings(volatile avr32_tc_t *tc, unsigned int channel);
405
 
406
/*! \brief Enables various timer/counter interrupts.
407
 *
408
 * \param tc              Pointer to the TC instance to access.
409
 * \param channel         The TC instance channel to access.
410
 * \param bitfield        The interrupt enable configuration.
411
 *
412
 * \retval 0 Success.
413
 * \retval TC_INVALID_ARGUMENT Invalid argument(s).
414
 */
415
extern int tc_configure_interrupts(volatile avr32_tc_t *tc, unsigned int channel, const tc_interrupt_t *bitfield);
416
 
417
/*! \brief Selects which external clock to use and how to configure it.
418
 *
419
 * \param tc              Pointer to the TC instance to access.
420
 * \param channel         The TC instance channel to access.
421
 * \param ext_clk_sig_src External clock signal selection:
422
 *   \arg \c TC_CH0_EXT_CLK0_SRC_TCLK0;
423
 *   \arg \c TC_CH0_EXT_CLK0_SRC_NO_CLK;
424
 *   \arg \c TC_CH0_EXT_CLK0_SRC_TIOA1;
425
 *   \arg \c TC_CH0_EXT_CLK0_SRC_TIOA2;
426
 *   \arg \c TC_CH1_EXT_CLK1_SRC_TCLK1;
427
 *   \arg \c TC_CH1_EXT_CLK1_SRC_NO_CLK;
428
 *   \arg \c TC_CH1_EXT_CLK1_SRC_TIOA0;
429
 *   \arg \c TC_CH1_EXT_CLK1_SRC_TIOA2;
430
 *   \arg \c TC_CH2_EXT_CLK2_SRC_TCLK2;
431
 *   \arg \c TC_CH2_EXT_CLK2_SRC_NO_CLK;
432
 *   \arg \c TC_CH2_EXT_CLK2_SRC_TIOA0;
433
 *   \arg \c TC_CH2_EXT_CLK2_SRC_TIOA1.
434
 *
435
 * \retval 0 Success.
436
 * \retval TC_INVALID_ARGUMENT Invalid argument(s).
437
 */
438
extern int tc_select_external_clock(volatile avr32_tc_t *tc, unsigned int channel, unsigned int ext_clk_sig_src);
439
 
440
/*! \brief Sets options for timer/counter capture initialization.
441
 *
442
 * \param tc              Pointer to the TC instance to access.
443
 * \param opt             Options for capture mode.
444
 *
445
 * \retval 0 Success.
446
 * \retval TC_INVALID_ARGUMENT Invalid argument(s).
447
 */
448
extern int tc_init_capture(volatile avr32_tc_t *tc, const tc_capture_opt_t *opt);
449
 
450
/*! \brief Sets options for timer/counter waveform initialization.
451
 *
452
 * \param tc              Pointer to the TC instance to access.
453
 * \param opt             Options for waveform generation.
454
 *
455
 * \retval 0 Success.
456
 * \retval TC_INVALID_ARGUMENT Invalid argument(s).
457
 */
458
extern int tc_init_waveform(volatile avr32_tc_t *tc, const tc_waveform_opt_t *opt);
459
 
460
/*! \brief Starts a timer/counter.
461
 *
462
 * \param tc              Pointer to the TC instance to access.
463
 * \param channel         The TC instance channel to access.
464
 *
465
 * \retval 0 Success.
466
 * \retval TC_INVALID_ARGUMENT Invalid argument(s).
467
 */
468
extern int tc_start(volatile avr32_tc_t *tc, unsigned int channel);
469
 
470
/*! \brief Stops a timer/counter.
471
 *
472
 * \param tc              Pointer to the TC instance to access.
473
 * \param channel         The TC instance channel to access.
474
 *
475
 * \retval 0 Success.
476
 * \retval TC_INVALID_ARGUMENT Invalid argument(s).
477
 */
478
extern int tc_stop(volatile avr32_tc_t *tc, unsigned int channel);
479
 
480
/*! \brief Performs a software trigger: the counter is reset and the clock is started.
481
 *
482
 * \param tc              Pointer to the TC instance to access.
483
 * \param channel         The TC instance channel to access.
484
 *
485
 * \retval 0 Success.
486
 * \retval TC_INVALID_ARGUMENT Invalid argument(s).
487
 */
488
extern int tc_software_trigger(volatile avr32_tc_t *tc, unsigned int channel);
489
 
490
/*! \brief Asserts a SYNC signal to generate a software trigger and reset all channels.
491
 *
492
 * \param tc              Pointer to the TC instance to access.
493
 */
494
extern void tc_sync_trigger(volatile avr32_tc_t *tc);
495
 
496
/*! \brief Reads the status register.
497
 *
498
 * \param tc              Pointer to the TC instance to access.
499
 * \param channel         The TC instance channel to access.
500
 *
501
 * \retval >=0 Status register value.
502
 * \retval TC_INVALID_ARGUMENT Invalid argument(s).
503
 */
504
extern int tc_read_sr(volatile avr32_tc_t *tc, unsigned int channel);
505
 
506
/*! \brief Reads the channel's TC counter and returns the value.
507
 *
508
 * \param tc              Pointer to the TC instance to access.
509
 * \param channel         The TC instance channel to access.
510
 *
511
 * \retval >=0 TC counter value.
512
 * \retval TC_INVALID_ARGUMENT Invalid argument(s).
513
 */
514
extern int tc_read_tc(volatile avr32_tc_t *tc, unsigned int channel);
515
 
516
/*! \brief Reads the channel's RA register and returns the value.
517
 *
518
 * \param tc              Pointer to the TC instance to access.
519
 * \param channel         The TC instance channel to access.
520
 *
521
 * \retval >=0 RA register value.
522
 * \retval TC_INVALID_ARGUMENT Invalid argument(s).
523
 */
524
extern int tc_read_ra(volatile avr32_tc_t *tc, unsigned int channel);
525
 
526
/*! \brief Reads the channel's RB register and returns the value.
527
 *
528
 * \param tc              Pointer to the TC instance to access.
529
 * \param channel         The TC instance channel to access.
530
 *
531
 * \retval >=0 RB register value.
532
 * \retval TC_INVALID_ARGUMENT Invalid argument(s).
533
 */
534
extern int tc_read_rb(volatile avr32_tc_t *tc, unsigned int channel);
535
 
536
/*! \brief Reads the channel's RC register and returns the value.
537
 *
538
 * \param tc              Pointer to the TC instance to access.
539
 * \param channel         The TC instance channel to access.
540
 *
541
 * \retval >=0 RC register value.
542
 * \retval TC_INVALID_ARGUMENT Invalid argument(s).
543
 */
544
extern int tc_read_rc(volatile avr32_tc_t *tc, unsigned int channel);
545
 
546
/*! \brief Writes a value to the channel's RA register.
547
 *
548
 * \param tc              Pointer to the TC instance to access.
549
 * \param channel         The TC instance channel to access.
550
 * \param value           Value to write to the RA register.
551
 *
552
 * \retval >=0 Written value.
553
 * \retval TC_INVALID_ARGUMENT Invalid argument(s).
554
 */
555
extern int tc_write_ra(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value);
556
 
557
/*! \brief Writes a value to the channel's RB register.
558
 *
559
 * \param tc              Pointer to the TC instance to access.
560
 * \param channel         The TC instance channel to access.
561
 * \param value           Value to write to the RB register.
562
 *
563
 * \retval >=0 Written value.
564
 * \retval TC_INVALID_ARGUMENT Invalid argument(s).
565
 */
566
extern int tc_write_rb(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value);
567
 
568
/*! \brief Writes a value to the channel's RC register.
569
 *
570
 * \param tc              Pointer to the TC instance to access.
571
 * \param channel         The TC instance channel to access.
572
 * \param value           Value to write to the RC register.
573
 *
574
 * \retval >=0 Written value.
575
 * \retval TC_INVALID_ARGUMENT Invalid argument(s).
576
 */
577
extern int tc_write_rc(volatile avr32_tc_t *tc, unsigned int channel, unsigned short value);
578
 
579
 
580
#endif  // _TC_H_

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.