OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [lwIP_AVR32_UC3/] [SERVICES/] [USB/] [CLASS/] [DFU/] [EXAMPLES/] [ISP/] [BOOT/] [trampoline.s82] - Blame information for rev 583

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 583 jeremybenn
/*This file is prepared for Doxygen automatic documentation generation.*/
2
/*! \file *********************************************************************
3
 *
4
 * \brief AVR32 UC3 ISP trampoline.
5
 *
6
 * In order to be able to program a project with both BatchISP and JTAGICE mkII
7
 * without having to take the general-purpose fuses into consideration, add this
8
 * file to the project and change the program entry point to __trampoline.
9
 *
10
 * The pre-programmed ISP will be erased if JTAGICE mkII is used.
11
 *
12
 * - Compiler:           IAR EWAVR32
13
 * - Supported devices:  All AVR32UC devices can be used.
14
 *
15
 * \author               Atmel Corporation: http://www.atmel.com \n
16
 *                       Support and FAQ: http://support.atmel.no/
17
 *
18
 ******************************************************************************/
19
 
20
/* Copyright (c) 2007, Atmel Corporation All rights reserved.
21
 *
22
 * Redistribution and use in source and binary forms, with or without
23
 * modification, are permitted provided that the following conditions are met:
24
 *
25
 * 1. Redistributions of source code must retain the above copyright notice,
26
 * this list of conditions and the following disclaimer.
27
 *
28
 * 2. Redistributions in binary form must reproduce the above copyright notice,
29
 * this list of conditions and the following disclaimer in the documentation
30
 * and/or other materials provided with the distribution.
31
 *
32
 * 3. The name of ATMEL may not be used to endorse or promote products derived
33
 * from this software without specific prior written permission.
34
 *
35
 * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
36
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
37
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
38
 * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
39
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
40
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
41
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
42
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
43
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
44
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45
 */
46
 
47
 
48
#include "../conf_isp.h"
49
 
50
 
51
//! @{
52
//! \verbatim
53
 
54
 
55
  RSEG  SSTACK:DATA:NOROOT(2)
56
 
57
 
58
  // This must be linked @ 0x80000000 if it is to be run upon reset.
59
  RSEG  RESET:CODE:NOROOT(1)
60
 
61
 
62
  PUBLIC  __trampoline
63
__trampoline:
64
  // Jump to program start.
65
  rjmp    program_start
66
 
67
  ORG PROGRAM_START_OFFSET
68
program_start:
69
  // Initialize the stack pointer.
70
  lddpc   sp, ??SPS
71
  // Jump to the C runtime startup routine.
72
  lddpc   pc, ??cmain
73
 
74
 
75
// Constant data area.
76
 
77
  ALIGN 2
78
 
79
??SPS:
80
  DC32  SFE(SSTACK) & ~3
81
 
82
  EXTERN  ?main
83
??cmain:
84
  DC32  ?main
85
 
86
 
87
  END
88
 
89
 
90
//! \endverbatim
91
//! @}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.