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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [lwIP_Demo_Rowley_ARM7/] [AT91SAM7_Startup.s] - Blame information for rev 590

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Line No. Rev Author Line
1 583 jeremybenn
/*****************************************************************************
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  Exception handlers and startup code for ATMEL AT91SAM7.
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  Copyright (c) 2004 Rowley Associates Limited.
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  This file may be distributed under the terms of the License Agreement
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  provided with this software.
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  THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE
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  WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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 *****************************************************************************/
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#define REG_BASE 0xFFFFF000
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#define CKGR_MOR_OFFSET 0xC20
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#define CKGR_PLLR_OFFSET 0xC2C
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#define PMC_MCKR_OFFSET 0xC30
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#define PMC_SR_OFFSET 0xC68
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#define WDT_MR_OFFSET 0xD44
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#define MC_RCR_OFFSET 0xF00
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#define MC_FMR_OFFSET 0xF60
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#define CKGR_MOR_MOSCEN (1 << 0)
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#define CKGR_MOR_OSCBYPASS (1 << 1)
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#define CKGR_MOR_OSCOUNT_BIT_OFFSET (8)
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#define CKGR_PLLR_DIV_BIT_OFFSET (0)
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#define CKGR_PLLR_PLLCOUNT_BIT_OFFSET (8)
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#define CKGR_PLLR_OUT_BIT_OFFSET (14)
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#define CKGR_PLLR_MUL_BIT_OFFSET (16)
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#define CKGR_PLLR_USBDIV_BIT_OFFSET (28)
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#define PMC_MCKR_CSS_MAIN_CLOCK (0x1)
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#define PMC_MCKR_CSS_PLL_CLOCK (0x3)
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#define PMC_MCKR_PRES_CLK (0)
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#define PMC_MCKR_PRES_CLK_2 (1 << 2)
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#define PMC_MCKR_PRES_CLK_4 (2 << 2)
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#define PMC_MCKR_PRES_CLK_8 (3 << 2)
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#define PMC_MCKR_PRES_CLK_16 (4 << 2)
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#define PMC_MCKR_PRES_CLK_32 (5 << 2)
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#define PMC_MCKR_PRES_CLK_64 (6 << 2)
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#define PMC_SR_MOSCS (1 << 0)
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#define PMC_SR_LOCK (1 << 2)
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#define PMC_SR_MCKRDY (1 << 3)
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#define PMC_SR_PCKRDY0 (1 << 8)
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#define PMC_SR_PCKRDY1 (1 << 9)
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#define PMC_SR_PCKRDY2 (1 << 10)
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#define MC_RCR_RCB (1 << 0)
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#define MC_FMR_FWS_0FWS (0)
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#define MC_FMR_FWS_1FWS (1 << 8)
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#define MC_FMR_FWS_2FWS (2 << 8)
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#define MC_FMR_FWS_3FWS (3 << 8)
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#define MC_FMR_FMCN_BIT_OFFSET 16
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#define WDT_MR_WDDIS (1 << 15)
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  .section .vectors, "ax"
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  .code 32
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  .align 0
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/*****************************************************************************
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  Exception Vectors
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 *****************************************************************************/
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_vectors:
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  ldr pc, [pc, #reset_handler_address - . - 8]  /* reset */
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  ldr pc, [pc, #undef_handler_address - . - 8]  /* undefined instruction */
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  ldr pc, [pc, #swi_handler_address - . - 8]    /* swi handler */
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  ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */
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  ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */
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  nop
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  ldr pc, [PC, #-0xF20]    /* irq */
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  ldr pc, [pc, #fiq_handler_address - . - 8]    /* fiq */
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reset_handler_address:
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  .word reset_handler
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undef_handler_address:
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  .word undef_handler
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swi_handler_address:
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  .word swi_handler
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pabort_handler_address:
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  .word pabort_handler
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dabort_handler_address:
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  .word dabort_handler
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irq_handler_address:
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  .word irq_handler
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fiq_handler_address:
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  .word fiq_handler
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  .section .init, "ax"
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  .code 32
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  .align 0
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/******************************************************************************
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  Reset handler
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 ******************************************************************************/
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reset_handler:
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  ldr r10, =REG_BASE
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  /* Set up FLASH wait state */
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  ldr r0, =(50 << MC_FMR_FMCN_BIT_OFFSET) | MC_FMR_FWS_1FWS
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  str r0, [r10, #MC_FMR_OFFSET]
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  /* Disable Watchdog */
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  ldr r0, =WDT_MR_WDDIS
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  str r0, [r10, #WDT_MR_OFFSET]
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  /* Enable the main oscillator */
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  ldr r0, =(6 << CKGR_MOR_OSCOUNT_BIT_OFFSET) | CKGR_MOR_MOSCEN
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  str r0, [r10, #CKGR_MOR_OFFSET]
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1:/* Wait for main oscillator to stabilize */
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  ldr r0, [r10, #PMC_SR_OFFSET]
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  tst r0, #PMC_SR_MOSCS
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  beq 1b
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  /* Set up the PLL */
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  ldr r0, =(5 << CKGR_PLLR_DIV_BIT_OFFSET) | (28 << CKGR_PLLR_PLLCOUNT_BIT_OFFSET) | (25 << CKGR_PLLR_MUL_BIT_OFFSET)
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  str r0, [r10, #CKGR_PLLR_OFFSET]
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1:/* Wait for PLL to lock */
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  ldr r0, [r10, #PMC_SR_OFFSET]
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  tst r0, #PMC_SR_LOCK
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  beq 1b
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  /* Select PLL as clock source */
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  ldr r0, =(PMC_MCKR_CSS_PLL_CLOCK | PMC_MCKR_PRES_CLK_2)
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  str r0, [r10, #PMC_MCKR_OFFSET]
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#ifdef __FLASH_BUILD
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  /* Copy exception vectors into Internal SRAM */
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  mov r8, #0x00200000
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  ldr r9, =_vectors
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  ldmia r9!, {r0-r7}
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  stmia r8!, {r0-r7}
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  ldmia r9!, {r0-r6}
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  stmia r8!, {r0-r6}
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  /* Remap Internal SRAM to 0x00000000 */
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  ldr r0, =MC_RCR_RCB
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  strb r0, [r10, #MC_RCR_OFFSET]
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#endif
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  /* Jump to the default C runtime startup code. */
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  b _start
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/******************************************************************************
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  Default exception handlers
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  (These are declared weak symbols so they can be redefined in user code)
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 ******************************************************************************/
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undef_handler:
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  b undef_handler
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swi_handler:
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  b swi_handler
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pabort_handler:
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  b pabort_handler
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dabort_handler:
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  b dabort_handler
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irq_handler:
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  b irq_handler
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fiq_handler:
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  b fiq_handler
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  .weak undef_handler, swi_handler, pabort_handler, dabort_handler, irq_handler, fiq_handler

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