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jeremybenn |
/******************************************************************************
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Target Script for ATMEL AT91SAM7.
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Copyright (c) 2004 Rowley Associates Limited.
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This file may be distributed under the terms of the License Agreement
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provided with this software.
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THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE
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WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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******************************************************************************/
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function Reset()
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{
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/* Reset and stop target */
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TargetInterface.pokeWord(0xFFFFFD00, 0xA500000D); // RSTC_CR
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TargetInterface.waitForDebugState(1000);
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/* Configure Clock */
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TargetInterface.pokeWord(0xFFFFFC20, 0x00000601); // CKGR_MOR
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TargetInterface.delay(10);
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TargetInterface.pokeWord(0xFFFFFC2C, 0x00191C05); // CKGR_PLLR
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TargetInterface.delay(10);
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TargetInterface.pokeWord(0xFFFFFC30, 0x00000007); // CKGR_MCKR
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TargetInterface.delay(10);
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}
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function RAMReset()
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{
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Reset();
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/* Remap SRAM to 0x00000000 */
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TargetInterface.pokeWord(0xFFFFFF00, 1); // MC_RCR
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}
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function FLASHReset()
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{
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Reset();
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// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
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TargetInterface.pokeWord(0xffffffff,0xFFFFF124);
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TargetInterface.pokeWord(0xffffffff,0xFFFFF128);
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// disable peripheral clock Peripheral Clock Disable Register
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TargetInterface.pokeWord(0xffffffff,0xFFFFFC14);
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// #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
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// #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
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// #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
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TargetInterface.peekWord(0xFFFA0020);
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TargetInterface.peekWord(0xFFFA0060);
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TargetInterface.peekWord(0xFFFA00A0);
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// for (__mac_i=0;__mac_i < 8; __mac_i++)
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// {
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// AT91C_BASE_AIC->AIC_EOICR
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// __mac_pt = TargetInterface.peekWord(0xFFFFF130);
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// }
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// __message "------------------------------- AIC 2 INIT ---------------------------------------------";
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}
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