OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [lwIP_Demo_Rowley_ARM7/] [EMAC/] [mii.h] - Blame information for rev 620

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 583 jeremybenn
/* Generic MII registers. */
2
 
3
#define MII_BMCR            0x00        /* Basic mode control register */
4
#define MII_BMSR            0x01        /* Basic mode status register  */
5
#define MII_PHYSID1         0x02        /* PHYS ID 1                   */
6
#define MII_PHYSID2         0x03        /* PHYS ID 2                   */
7
#define MII_ADVERTISE       0x04        /* Advertisement control reg   */
8
#define MII_LPA             0x05        /* Link partner ability reg    */
9
#define MII_EXPANSION       0x06        /* Expansion register          */
10
#define MII_DCOUNTER        0x12        /* Disconnect counter          */
11
#define MII_FCSCOUNTER      0x13        /* False carrier counter       */
12
#define MII_NWAYTEST        0x14        /* N-way auto-neg test reg     */
13
#define MII_RERRCOUNTER     0x15        /* Receive error counter       */
14
#define MII_SREVISION       0x16        /* Silicon revision            */
15
#define MII_RESV1           0x17        /* Reserved...                 */
16
#define MII_LBRERROR        0x18        /* Lpback, rx, bypass error    */
17
#define MII_PHYADDR         0x19        /* PHY address                 */
18
#define MII_RESV2           0x1a        /* Reserved...                 */
19
#define MII_TPISTATUS       0x1b        /* TPI status for 10mbps       */
20
#define MII_NCONFIG         0x1c        /* Network interface config    */
21
 
22
/* Basic mode control register. */
23
#define BMCR_RESV               0x007f  /* Unused...                   */
24
#define BMCR_CTST               0x0080  /* Collision test              */
25
#define BMCR_FULLDPLX           0x0100  /* Full duplex                 */
26
#define BMCR_ANRESTART          0x0200  /* Auto negotiation restart    */
27
#define BMCR_ISOLATE            0x0400  /* Disconnect DP83840 from MII */
28
#define BMCR_PDOWN              0x0800  /* Powerdown the DP83840       */
29
#define BMCR_ANENABLE           0x1000  /* Enable auto negotiation     */
30
#define BMCR_SPEED100           0x2000  /* Select 100Mbps              */
31
#define BMCR_LOOPBACK           0x4000  /* TXD loopback bits           */
32
#define BMCR_RESET              0x8000  /* Reset the DP83840           */
33
 
34
/* Basic mode status register. */
35
#define BMSR_ERCAP              0x0001  /* Ext-reg capability          */
36
#define BMSR_JCD                0x0002  /* Jabber detected             */
37
#define BMSR_LSTATUS            0x0004  /* Link status                 */
38
#define BMSR_ANEGCAPABLE        0x0008  /* Able to do auto-negotiation */
39
#define BMSR_RFAULT             0x0010  /* Remote fault detected       */
40
#define BMSR_ANEGCOMPLETE       0x0020  /* Auto-negotiation complete   */
41
#define BMSR_RESV               0x07c0  /* Unused...                   */
42
#define BMSR_10HALF             0x0800  /* Can do 10mbps, half-duplex  */
43
#define BMSR_10FULL             0x1000  /* Can do 10mbps, full-duplex  */
44
#define BMSR_100HALF            0x2000  /* Can do 100mbps, half-duplex */
45
#define BMSR_100FULL            0x4000  /* Can do 100mbps, full-duplex */
46
#define BMSR_100BASE4           0x8000  /* Can do 100mbps, 4k packets  */
47
 
48
/* Advertisement control register. */
49
#define ADVERTISE_SLCT          0x001f  /* Selector bits               */
50
#define ADVERTISE_CSMA          0x0001  /* Only selector supported     */
51
#define ADVERTISE_10HALF        0x0020  /* Try for 10mbps half-duplex  */
52
#define ADVERTISE_10FULL        0x0040  /* Try for 10mbps full-duplex  */
53
#define ADVERTISE_100HALF       0x0080  /* Try for 100mbps half-duplex */
54
#define ADVERTISE_100FULL       0x0100  /* Try for 100mbps full-duplex */
55
#define ADVERTISE_100BASE4      0x0200  /* Try for 100mbps 4k packets  */
56
#define ADVERTISE_RESV          0x1c00  /* Unused...                   */
57
#define ADVERTISE_RFAULT        0x2000  /* Say we can detect faults    */
58
#define ADVERTISE_LPACK         0x4000  /* Ack link partners response  */
59
#define ADVERTISE_NPAGE         0x8000  /* Next page bit               */
60
 
61
#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \
62
                        ADVERTISE_CSMA)
63
#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \
64
                       ADVERTISE_100HALF | ADVERTISE_100FULL)
65
 
66
/* Link partner ability register. */
67
#define LPA_SLCT                0x001f  /* Same as advertise selector  */
68
#define LPA_10HALF              0x0020  /* Can do 10mbps half-duplex   */
69
#define LPA_10FULL              0x0040  /* Can do 10mbps full-duplex   */
70
#define LPA_100HALF             0x0080  /* Can do 100mbps half-duplex  */
71
#define LPA_100FULL             0x0100  /* Can do 100mbps full-duplex  */
72
#define LPA_100BASE4            0x0200  /* Can do 100mbps 4k packets   */
73
#define LPA_RESV                0x1c00  /* Unused...                   */
74
#define LPA_RFAULT              0x2000  /* Link partner faulted        */
75
#define LPA_LPACK               0x4000  /* Link partner acked us       */
76
#define LPA_NPAGE               0x8000  /* Next page bit               */
77
 
78
#define LPA_DUPLEX              (LPA_10FULL | LPA_100FULL)
79
#define LPA_100                 (LPA_100FULL | LPA_100HALF | LPA_100BASE4)
80
 
81
/* Expansion register for auto-negotiation. */
82
#define EXPANSION_NWAY          0x0001  /* Can do N-way auto-nego      */
83
#define EXPANSION_LCWP          0x0002  /* Got new RX page code word   */
84
#define EXPANSION_ENABLENPAGE   0x0004  /* This enables npage words    */
85
#define EXPANSION_NPCAPABLE     0x0008  /* Link partner supports npage */
86
#define EXPANSION_MFAULTS       0x0010  /* Multiple faults detected    */
87
#define EXPANSION_RESV          0xffe0  /* Unused...                   */
88
 
89
/* N-way test register. */
90
#define NWAYTEST_RESV1          0x00ff  /* Unused...                   */
91
#define NWAYTEST_LOOPBACK       0x0100  /* Enable loopback for N-way   */
92
#define NWAYTEST_RESV2          0xfe00  /* Unused...                   */
93
 
94
#define SPEED_10                                10
95
#define SPEED_100                               100
96
 
97
/* Duplex, half or full. */
98
#define DUPLEX_HALF                             0x00
99
#define DUPLEX_FULL                             0x01
100
 
101
/* PHY ID */
102
#define MII_DM9161_ID     0x0181b8a0
103
#define MII_AM79C875_ID   0x00225540    /* 0x00225541 */
104
 
105
#define AT91C_PHY_ADDR  31

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.