OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [lwIP_Demo_Rowley_ARM7/] [atmel-rom.ld] - Blame information for rev 590

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 583 jeremybenn
MEMORY
2
{
3
        flash   : ORIGIN = 0x00100000, LENGTH = 256K
4
        ram             : ORIGIN = 0x00200000, LENGTH = 64K
5
}
6
 
7
__stack_end__ = 0x00200000 + 64K - 4;
8
 
9
SECTIONS
10
{
11
        . = 0;
12
        startup : { *(.startup)} >flash
13
 
14
        prog :
15
        {
16
                *(.text)
17
                *(.rodata)
18
                *(.rodata*)
19
                *(.glue_7)
20
                *(.glue_7t)
21
        } >flash
22
 
23
        __end_of_text__ = .;
24
 
25
        .data :
26
        {
27
                __data_beg__ = .;
28
                __data_beg_src__ = __end_of_text__;
29
                *(.data)
30
                __data_end__ = .;
31
        } >ram AT>flash
32
 
33
        .bss :
34
        {
35
                __bss_beg__ = .;
36
                *(.bss)
37
        } >ram
38
 
39
        /* Align here to ensure that the .bss section occupies space up to
40
        _end.  Align after .bss to ensure correct alignment even if the
41
        .bss section disappears because there are no input sections.  */
42
        . = ALIGN(32 / 8);
43
}
44
        . = ALIGN(32 / 8);
45
        _end = .;
46
        _bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
47
        PROVIDE (end = .);
48
 
49
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.