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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [lwIP_MCF5235_GCC/] [include/] [arch/] [mcf523x/] [mcf523x_eport.h] - Blame information for rev 594

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Line No. Rev Author Line
1 583 jeremybenn
/*
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 * These files are taken from the MCF523X source code example package
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 * which is available on the Freescale website. Freescale explicitly
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 * grants the redistribution and modification of these source files.
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 * The complete licensing information is available in the file
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 * LICENSE_FREESCALE.TXT.
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 *
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 * File:        mcf523x_eport.h
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 * Purpose:     Register and bit definitions for the MCF523X
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 *
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 * Notes:
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 *
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 */
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#ifndef __MCF523X_EPORT_H__
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#define __MCF523X_EPORT_H__
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/*********************************************************************
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*
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* Edge Port Module (EPORT)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_EPORT_EPPAR    (*(vuint16*)(void*)(&__IPSBAR[0x130000]))
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#define MCF_EPORT_EPDDR    (*(vuint8 *)(void*)(&__IPSBAR[0x130002]))
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#define MCF_EPORT_EPIER    (*(vuint8 *)(void*)(&__IPSBAR[0x130003]))
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#define MCF_EPORT_EPDR     (*(vuint8 *)(void*)(&__IPSBAR[0x130004]))
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#define MCF_EPORT_EPPDR    (*(vuint8 *)(void*)(&__IPSBAR[0x130005]))
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#define MCF_EPORT_EPFR     (*(vuint8 *)(void*)(&__IPSBAR[0x130006]))
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/* Bit definitions and macros for MCF_EPORT_EPPAR */
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#define MCF_EPORT_EPPAR_EPPA1(x)         (((x)&0x0003)<<2)
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#define MCF_EPORT_EPPAR_EPPA2(x)         (((x)&0x0003)<<4)
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#define MCF_EPORT_EPPAR_EPPA3(x)         (((x)&0x0003)<<6)
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#define MCF_EPORT_EPPAR_EPPA4(x)         (((x)&0x0003)<<8)
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#define MCF_EPORT_EPPAR_EPPA5(x)         (((x)&0x0003)<<10)
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#define MCF_EPORT_EPPAR_EPPA6(x)         (((x)&0x0003)<<12)
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#define MCF_EPORT_EPPAR_EPPA7(x)         (((x)&0x0003)<<14)
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#define MCF_EPORT_EPPAR_EPPAx_LEVEL      (0)
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#define MCF_EPORT_EPPAR_EPPAx_RISING     (1)
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#define MCF_EPORT_EPPAR_EPPAx_FALLING    (2)
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#define MCF_EPORT_EPPAR_EPPAx_BOTH       (3)
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/* Bit definitions and macros for MCF_EPORT_EPDDR */
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#define MCF_EPORT_EPDDR_EPDD1            (0x02)
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#define MCF_EPORT_EPDDR_EPDD2            (0x04)
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#define MCF_EPORT_EPDDR_EPDD3            (0x08)
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#define MCF_EPORT_EPDDR_EPDD4            (0x10)
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#define MCF_EPORT_EPDDR_EPDD5            (0x20)
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#define MCF_EPORT_EPDDR_EPDD6            (0x40)
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#define MCF_EPORT_EPDDR_EPDD7            (0x80)
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/* Bit definitions and macros for MCF_EPORT_EPIER */
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#define MCF_EPORT_EPIER_EPIE1            (0x02)
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#define MCF_EPORT_EPIER_EPIE2            (0x04)
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#define MCF_EPORT_EPIER_EPIE3            (0x08)
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#define MCF_EPORT_EPIER_EPIE4            (0x10)
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#define MCF_EPORT_EPIER_EPIE5            (0x20)
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#define MCF_EPORT_EPIER_EPIE6            (0x40)
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#define MCF_EPORT_EPIER_EPIE7            (0x80)
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/* Bit definitions and macros for MCF_EPORT_EPDR */
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#define MCF_EPORT_EPDR_EPD1              (0x02)
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#define MCF_EPORT_EPDR_EPD2              (0x04)
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#define MCF_EPORT_EPDR_EPD3              (0x08)
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#define MCF_EPORT_EPDR_EPD4              (0x10)
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#define MCF_EPORT_EPDR_EPD5              (0x20)
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#define MCF_EPORT_EPDR_EPD6              (0x40)
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#define MCF_EPORT_EPDR_EPD7              (0x80)
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/* Bit definitions and macros for MCF_EPORT_EPPDR */
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#define MCF_EPORT_EPPDR_EPPD1            (0x02)
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#define MCF_EPORT_EPPDR_EPPD2            (0x04)
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#define MCF_EPORT_EPPDR_EPPD3            (0x08)
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#define MCF_EPORT_EPPDR_EPPD4            (0x10)
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#define MCF_EPORT_EPPDR_EPPD5            (0x20)
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#define MCF_EPORT_EPPDR_EPPD6            (0x40)
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#define MCF_EPORT_EPPDR_EPPD7            (0x80)
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/* Bit definitions and macros for MCF_EPORT_EPFR */
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#define MCF_EPORT_EPFR_EPF1              (0x02)
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#define MCF_EPORT_EPFR_EPF2              (0x04)
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#define MCF_EPORT_EPFR_EPF3              (0x08)
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#define MCF_EPORT_EPFR_EPF4              (0x10)
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#define MCF_EPORT_EPFR_EPF5              (0x20)
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#define MCF_EPORT_EPFR_EPF6              (0x40)
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#define MCF_EPORT_EPFR_EPF7              (0x80)
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/********************************************************************/
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#endif /* __MCF523X_EPORT_H__ */

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