OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [lwIP_MCF5235_GCC/] [include/] [arch/] [mcf523x/] [mcf523x_fmpll.h] - Blame information for rev 583

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 583 jeremybenn
/*
2
 * These files are taken from the MCF523X source code example package
3
 * which is available on the Freescale website. Freescale explicitly
4
 * grants the redistribution and modification of these source files.
5
 * The complete licensing information is available in the file
6
 * LICENSE_FREESCALE.TXT.
7
 *
8
 * File:        mcf523x_fmpll.h
9
 * Purpose:     Register and bit definitions for the MCF523X
10
 *
11
 * Notes:
12
 *
13
 */
14
 
15
#ifndef __MCF523X_FMPLL_H__
16
#define __MCF523X_FMPLL_H__
17
 
18
/*********************************************************************
19
*
20
* Frequency Modulated Phase Locked Loop (FMPLL)
21
*
22
*********************************************************************/
23
 
24
/* Register read/write macros */
25
#define MCF_FMPLL_SYNCR    (*(vuint32*)(void*)(&__IPSBAR[0x120000]))
26
#define MCF_FMPLL_SYNSR    (*(vuint32*)(void*)(&__IPSBAR[0x120004]))
27
 
28
/* Bit definitions and macros for MCF_FMPLL_SYNCR */
29
#define MCF_FMPLL_SYNCR_EXP(x)       (((x)&0x000003FF)<<0)
30
#define MCF_FMPLL_SYNCR_DEPTH(x)     (((x)&0x00000003)<<10)
31
#define MCF_FMPLL_SYNCR_RATE         (0x00001000)
32
#define MCF_FMPLL_SYNCR_LOCIRQ       (0x00002000)
33
#define MCF_FMPLL_SYNCR_LOLIRQ       (0x00004000)
34
#define MCF_FMPLL_SYNCR_DISCLK       (0x00008000)
35
#define MCF_FMPLL_SYNCR_LOCRE        (0x00010000)
36
#define MCF_FMPLL_SYNCR_LOLRE        (0x00020000)
37
#define MCF_FMPLL_SYNCR_LOCEN        (0x00040000)
38
#define MCF_FMPLL_SYNCR_RFD(x)       (((x)&0x00000007)<<19)
39
#define MCF_FMPLL_SYNCR_MFD(x)       (((x)&0x00000007)<<24)
40
 
41
/* Bit definitions and macros for MCF_FMPLL_SYNSR */
42
#define MCF_FMPLL_SYNSR_CALPASS      (0x00000001)
43
#define MCF_FMPLL_SYNSR_CALDONE      (0x00000002)
44
#define MCF_FMPLL_SYNSR_LOCF         (0x00000004)
45
#define MCF_FMPLL_SYNSR_LOCK         (0x00000008)
46
#define MCF_FMPLL_SYNSR_LOCKS        (0x00000010)
47
#define MCF_FMPLL_SYNSR_PLLREF       (0x00000020)
48
#define MCF_FMPLL_SYNSR_PLLSEL       (0x00000040)
49
#define MCF_FMPLL_SYNSR_MODE         (0x00000080)
50
#define MCF_FMPLL_SYNSR_LOC          (0x00000100)
51
#define MCF_FMPLL_SYNSR_LOLF         (0x00000200)
52
 
53
/********************************************************************/
54
 
55
#endif /* __MCF523X_FMPLL_H__ */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.