OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [lwIP_MCF5235_GCC/] [include/] [arch/] [mcf523x/] [mcf523x_i2c.h] - Blame information for rev 609

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 583 jeremybenn
/*
2
 * These files are taken from the MCF523X source code example package
3
 * which is available on the Freescale website. Freescale explicitly
4
 * grants the redistribution and modification of these source files.
5
 * The complete licensing information is available in the file
6
 * LICENSE_FREESCALE.TXT.
7
 *
8
 * File:        mcf523x_i2c.h
9
 * Purpose:     Register and bit definitions for the MCF523X
10
 *
11
 * Notes:
12
 *
13
 */
14
 
15
#ifndef __MCF523X_I2C_H__
16
#define __MCF523X_I2C_H__
17
 
18
/*********************************************************************
19
*
20
* I2C Module (I2C)
21
*
22
*********************************************************************/
23
 
24
/* Register read/write macros */
25
#define MCF_I2C_I2AR     (*(vuint8 *)(void*)(&__IPSBAR[0x000300]))
26
#define MCF_I2C_I2FDR    (*(vuint8 *)(void*)(&__IPSBAR[0x000304]))
27
#define MCF_I2C_I2CR     (*(vuint8 *)(void*)(&__IPSBAR[0x000308]))
28
#define MCF_I2C_I2SR     (*(vuint8 *)(void*)(&__IPSBAR[0x00030C]))
29
#define MCF_I2C_I2DR     (*(vuint8 *)(void*)(&__IPSBAR[0x000310]))
30
#define MCF_I2C_I2ICR    (*(vuint8 *)(void*)(&__IPSBAR[0x000320]))
31
 
32
/* Bit definitions and macros for MCF_I2C_I2AR */
33
#define MCF_I2C_I2AR_ADR(x)    (((x)&0x7F)<<1)
34
 
35
/* Bit definitions and macros for MCF_I2C_I2FDR */
36
#define MCF_I2C_I2FDR_IC(x)    (((x)&0x3F)<<0)
37
 
38
/* Bit definitions and macros for MCF_I2C_I2CR */
39
#define MCF_I2C_I2CR_RSTA      (0x04)
40
#define MCF_I2C_I2CR_TXAK      (0x08)
41
#define MCF_I2C_I2CR_MTX       (0x10)
42
#define MCF_I2C_I2CR_MSTA      (0x20)
43
#define MCF_I2C_I2CR_IIEN      (0x40)
44
#define MCF_I2C_I2CR_IEN       (0x80)
45
 
46
/* Bit definitions and macros for MCF_I2C_I2SR */
47
#define MCF_I2C_I2SR_RXAK      (0x01)
48
#define MCF_I2C_I2SR_IIF       (0x02)
49
#define MCF_I2C_I2SR_SRW       (0x04)
50
#define MCF_I2C_I2SR_IAL       (0x10)
51
#define MCF_I2C_I2SR_IBB       (0x20)
52
#define MCF_I2C_I2SR_IAAS      (0x40)
53
#define MCF_I2C_I2SR_ICF       (0x80)
54
 
55
/* Bit definitions and macros for MCF_I2C_I2ICR */
56
#define MCF_I2C_I2ICR_IE       (0x01)
57
#define MCF_I2C_I2ICR_RE       (0x02)
58
#define MCF_I2C_I2ICR_TE       (0x04)
59
#define MCF_I2C_I2ICR_BNBE     (0x08)
60
 
61
/********************************************************************/
62
 
63
#endif /* __MCF523X_I2C_H__ */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.