OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [lwIP_MCF5235_GCC/] [include/] [arch/] [mcf523x/] [mcf523x_wtm.h] - Blame information for rev 594

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 583 jeremybenn
/*
2
 * These files are taken from the MCF523X source code example package
3
 * which is available on the Freescale website. Freescale explicitly
4
 * grants the redistribution and modification of these source files.
5
 * The complete licensing information is available in the file
6
 * LICENSE_FREESCALE.TXT.
7
 *
8
 * File:        mcf523x_wtm.h
9
 * Purpose:     Register and bit definitions for the MCF523X
10
 *
11
 * Notes:
12
 *
13
 */
14
 
15
#ifndef __MCF523X_WTM_H__
16
#define __MCF523X_WTM_H__
17
 
18
/*********************************************************************
19
*
20
* Watchdog Timer Modules (WTM)
21
*
22
*********************************************************************/
23
 
24
/* Register read/write macros */
25
#define MCF_WTM_WCR      (*(vuint16*)(void*)(&__IPSBAR[0x140000]))
26
#define MCF_WTM_WMR      (*(vuint16*)(void*)(&__IPSBAR[0x140002]))
27
#define MCF_WTM_WCNTR    (*(vuint16*)(void*)(&__IPSBAR[0x140004]))
28
#define MCF_WTM_WSR      (*(vuint16*)(void*)(&__IPSBAR[0x140006]))
29
 
30
/* Bit definitions and macros for MCF_WTM_WCR */
31
#define MCF_WTM_WCR_EN        (0x0001)
32
#define MCF_WTM_WCR_HALTED    (0x0002)
33
#define MCF_WTM_WCR_DOZE      (0x0004)
34
#define MCF_WTM_WCR_WAIT      (0x0008)
35
 
36
/* Bit definitions and macros for MCF_WTM_WMR */
37
#define MCF_WTM_WMR_WM0       (0x0001)
38
#define MCF_WTM_WMR_WM1       (0x0002)
39
#define MCF_WTM_WMR_WM2       (0x0004)
40
#define MCF_WTM_WMR_WM3       (0x0008)
41
#define MCF_WTM_WMR_WM4       (0x0010)
42
#define MCF_WTM_WMR_WM5       (0x0020)
43
#define MCF_WTM_WMR_WM6       (0x0040)
44
#define MCF_WTM_WMR_WM7       (0x0080)
45
#define MCF_WTM_WMR_WM8       (0x0100)
46
#define MCF_WTM_WMR_WM9       (0x0200)
47
#define MCF_WTM_WMR_WM10      (0x0400)
48
#define MCF_WTM_WMR_WM11      (0x0800)
49
#define MCF_WTM_WMR_WM12      (0x1000)
50
#define MCF_WTM_WMR_WM13      (0x2000)
51
#define MCF_WTM_WMR_WM14      (0x4000)
52
#define MCF_WTM_WMR_WM15      (0x8000)
53
 
54
/* Bit definitions and macros for MCF_WTM_WCNTR */
55
#define MCF_WTM_WCNTR_WC0     (0x0001)
56
#define MCF_WTM_WCNTR_WC1     (0x0002)
57
#define MCF_WTM_WCNTR_WC2     (0x0004)
58
#define MCF_WTM_WCNTR_WC3     (0x0008)
59
#define MCF_WTM_WCNTR_WC4     (0x0010)
60
#define MCF_WTM_WCNTR_WC5     (0x0020)
61
#define MCF_WTM_WCNTR_WC6     (0x0040)
62
#define MCF_WTM_WCNTR_WC7     (0x0080)
63
#define MCF_WTM_WCNTR_WC8     (0x0100)
64
#define MCF_WTM_WCNTR_WC9     (0x0200)
65
#define MCF_WTM_WCNTR_WC10    (0x0400)
66
#define MCF_WTM_WCNTR_WC11    (0x0800)
67
#define MCF_WTM_WCNTR_WC12    (0x1000)
68
#define MCF_WTM_WCNTR_WC13    (0x2000)
69
#define MCF_WTM_WCNTR_WC14    (0x4000)
70
#define MCF_WTM_WCNTR_WC15    (0x8000)
71
 
72
/* Bit definitions and macros for MCF_WTM_WSR */
73
#define MCF_WTM_WSR_WS0       (0x0001)
74
#define MCF_WTM_WSR_WS1       (0x0002)
75
#define MCF_WTM_WSR_WS2       (0x0004)
76
#define MCF_WTM_WSR_WS3       (0x0008)
77
#define MCF_WTM_WSR_WS4       (0x0010)
78
#define MCF_WTM_WSR_WS5       (0x0020)
79
#define MCF_WTM_WSR_WS6       (0x0040)
80
#define MCF_WTM_WSR_WS7       (0x0080)
81
#define MCF_WTM_WSR_WS8       (0x0100)
82
#define MCF_WTM_WSR_WS9       (0x0200)
83
#define MCF_WTM_WSR_WS10      (0x0400)
84
#define MCF_WTM_WSR_WS11      (0x0800)
85
#define MCF_WTM_WSR_WS12      (0x1000)
86
#define MCF_WTM_WSR_WS13      (0x2000)
87
#define MCF_WTM_WSR_WS14      (0x4000)
88
#define MCF_WTM_WSR_WS15      (0x8000)
89
 
90
/********************************************************************/
91
 
92
#endif /* __MCF523X_WTM_H__ */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.