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jeremybenn |
/*
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* These files are taken from the MCF523X source code example package
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* which is available on the Freescale website. Freescale explicitly
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* grants the redistribution and modification of these source files.
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* The complete licensing information is available in the file
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* LICENSE_FREESCALE.TXT.
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*
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* File: mcf5xxx.h
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* Purpose: Definitions common to all ColdFire processors
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*
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* Notes:
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*/
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#ifndef _CPU_MCF5XXX_H
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#define _CPU_MCF5XXX_H
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/***********************************************************************/
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/*
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* Misc. Defines
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*/
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#ifdef FALSE
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#undef FALSE
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#endif
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#define FALSE (0)
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#ifdef TRUE
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#undef TRUE
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#endif
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#define TRUE (1)
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#ifdef NULL
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#undef NULL
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#endif
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#define NULL (0)
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/***********************************************************************/
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/*
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* The basic data types
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*/
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typedef unsigned char uint8; /* 8 bits */
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typedef unsigned short int uint16; /* 16 bits */
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typedef unsigned long int uint32; /* 32 bits */
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typedef signed char int8; /* 8 bits */
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typedef signed short int int16; /* 16 bits */
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typedef signed long int int32; /* 32 bits */
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typedef volatile uint8 vuint8; /* 8 bits */
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typedef volatile uint16 vuint16; /* 16 bits */
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typedef volatile uint32 vuint32; /* 32 bits */
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/***********************************************************************/
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/*
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* Common M68K & ColdFire definitions
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*/
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#define ADDRESS uint32
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#define INSTRUCTION uint16
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#define ILLEGAL 0x4AFC
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#define CPU_WORD_SIZE 16
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#define MCF5XXX_SR_T (0x8000)
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#define MCF5XXX_SR_S (0x2000)
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#define MCF5XXX_SR_M (0x1000)
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#define MCF5XXX_SR_IPL (0x0700)
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#define MCF5XXX_SR_IPL_0 (0x0000)
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#define MCF5XXX_SR_IPL_1 (0x0100)
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#define MCF5XXX_SR_IPL_2 (0x0200)
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#define MCF5XXX_SR_IPL_3 (0x0300)
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#define MCF5XXX_SR_IPL_4 (0x0400)
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#define MCF5XXX_SR_IPL_5 (0x0500)
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#define MCF5XXX_SR_IPL_6 (0x0600)
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#define MCF5XXX_SR_IPL_7 (0x0700)
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#define MCF5XXX_SR_X (0x0010)
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#define MCF5XXX_SR_N (0x0008)
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#define MCF5XXX_SR_Z (0x0004)
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#define MCF5XXX_SR_V (0x0002)
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#define MCF5XXX_SR_C (0x0001)
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#define MCF5XXX_CACR_CENB (0x80000000)
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#define MCF5XXX_CACR_CPDI (0x10000000)
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#define MCF5XXX_CACR_CPD (0x10000000)
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#define MCF5XXX_CACR_CFRZ (0x08000000)
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#define MCF5XXX_CACR_CINV (0x01000000)
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#define MCF5XXX_CACR_DIDI (0x00800000)
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#define MCF5XXX_CACR_DISD (0x00400000)
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#define MCF5XXX_CACR_INVI (0x00200000)
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#define MCF5XXX_CACR_INVD (0x00100000)
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#define MCF5XXX_CACR_CEIB (0x00000400)
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#define MCF5XXX_CACR_DCM_WR (0x00000000)
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#define MCF5XXX_CACR_DCM_CB (0x00000100)
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#define MCF5XXX_CACR_DCM_IP (0x00000200)
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#define MCF5XXX_CACR_DCM (0x00000200)
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#define MCF5XXX_CACR_DCM_II (0x00000300)
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#define MCF5XXX_CACR_DBWE (0x00000100)
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#define MCF5XXX_CACR_DWP (0x00000020)
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#define MCF5XXX_CACR_EUST (0x00000010)
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#define MCF5XXX_CACR_CLNF_00 (0x00000000)
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#define MCF5XXX_CACR_CLNF_01 (0x00000002)
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#define MCF5XXX_CACR_CLNF_10 (0x00000004)
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#define MCF5XXX_CACR_CLNF_11 (0x00000006)
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#define MCF5XXX_ACR_AB(a) ((a)&0xFF000000)
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#define MCF5XXX_ACR_AM(a) (((a)&0xFF000000) >> 8)
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#define MCF5XXX_ACR_EN (0x00008000)
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#define MCF5XXX_ACR_SM_USER (0x00000000)
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#define MCF5XXX_ACR_SM_SUPER (0x00002000)
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#define MCF5XXX_ACR_SM_IGNORE (0x00006000)
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#define MCF5XXX_ACR_ENIB (0x00000080)
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#define MCF5XXX_ACR_CM (0x00000040)
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#define MCF5XXX_ACR_DCM_WR (0x00000000)
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#define MCF5XXX_ACR_DCM_CB (0x00000020)
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#define MCF5XXX_ACR_DCM_IP (0x00000040)
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#define MCF5XXX_ACR_DCM_II (0x00000060)
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#define MCF5XXX_ACR_CM (0x00000040)
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#define MCF5XXX_ACR_BWE (0x00000020)
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#define MCF5XXX_ACR_WP (0x00000004)
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#define MCF5XXX_RAMBAR_BA(a) ((a)&0xFFFFC000)
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#define MCF5XXX_RAMBAR_PRI_00 (0x00000000)
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#define MCF5XXX_RAMBAR_PRI_01 (0x00004000)
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#define MCF5XXX_RAMBAR_PRI_10 (0x00008000)
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#define MCF5XXX_RAMBAR_PRI_11 (0x0000C000)
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#define MCF5XXX_RAMBAR_WP (0x00000100)
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#define MCF5XXX_RAMBAR_CI (0x00000020)
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#define MCF5XXX_RAMBAR_SC (0x00000010)
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#define MCF5XXX_RAMBAR_SD (0x00000008)
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#define MCF5XXX_RAMBAR_UC (0x00000004)
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#define MCF5XXX_RAMBAR_UD (0x00000002)
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#define MCF5XXX_RAMBAR_V (0x00000001)
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/***********************************************************************/
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/*
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* The ColdFire family of processors has a simplified exception stack
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* frame that looks like the following:
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*
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* 3322222222221111 111111
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* 1098765432109876 5432109876543210
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* 8 +----------------+----------------+
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* | Program Counter |
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* 4 +----------------+----------------+
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* |FS/Fmt/Vector/FS| SR |
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* SP --> 0 +----------------+----------------+
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*
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* The stack self-aligns to a 4-byte boundary at an exception, with
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* the FS/Fmt/Vector/FS field indicating the size of the adjustment
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* (SP += 0,1,2,3 bytes).
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*/
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#define MCF5XXX_RD_SF_FORMAT(PTR) \
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((*((uint16 *)(PTR)) >> 12) & 0x00FF)
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#define MCF5XXX_RD_SF_VECTOR(PTR) \
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((*((uint16 *)(PTR)) >> 2) & 0x00FF)
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#define MCF5XXX_RD_SF_FS(PTR) \
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( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )
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#define MCF5XXX_SF_SR(PTR) *((uint16 *)(PTR)+1)
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#define MCF5XXX_SF_PC(PTR) *((uint32 *)(PTR)+1)
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/********************************************************************/
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/*
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* Functions provided by mcf5xxx.s
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*/
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int asm_set_ipl (uint32);
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void mcf5xxx_wr_cacr (uint32);
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void mcf5xxx_wr_acr0 (uint32);
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void mcf5xxx_wr_acr1 (uint32);
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void mcf5xxx_wr_acr2 (uint32);
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void mcf5xxx_wr_acr3 (uint32);
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void mcf5xxx_wr_other_a7 (uint32);
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void mcf5xxx_wr_other_sp (uint32);
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void mcf5xxx_wr_vbr (uint32);
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void mcf5xxx_wr_macsr (uint32);
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void mcf5xxx_wr_mask (uint32);
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void mcf5xxx_wr_acc0 (uint32);
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void mcf5xxx_wr_accext01 (uint32);
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void mcf5xxx_wr_accext23 (uint32);
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void mcf5xxx_wr_acc1 (uint32);
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void mcf5xxx_wr_acc2 (uint32);
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void mcf5xxx_wr_acc3 (uint32);
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void mcf5xxx_wr_sr (uint32);
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void mcf5xxx_wr_rambar0 (uint32);
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void mcf5xxx_wr_rambar1 (uint32);
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void mcf5xxx_wr_mbar (uint32);
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void mcf5xxx_wr_mbar0 (uint32);
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void mcf5xxx_wr_mbar1 (uint32);
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/********************************************************************/
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#endif /* _CPU_MCF5XXX_H */
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