OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [lwIP_MCF5235_GCC/] [m5235.gdb] - Blame information for rev 794

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 583 jeremybenn
set $IPSBAR = 0x40000000
2
 
3
set $DCR    = $IPSBAR + 0x000040
4
set $DACR0  = $IPSBAR + 0x000048
5
set $DMR0   = $IPSBAR + 0x00004C
6
 
7
set $CSAR0  = $IPSBAR + 0x000080
8
set $CSMR0  = $IPSBAR + 0x000084
9
set $CSCR0  = $IPSBAR + 0x00008A
10
 
11
set $PAR_SDRAM = $IPSBAR + 0x100046
12
set $PAR_AD    = $IPSBAR + 0x100040
13
 
14
set $WCR    = $IPSBAR + 0x140000
15
 
16
define delay
17
  set $delay = 0
18
  while ($delay < 20000)
19
    set $delay += 1
20
  end
21
end
22
 
23
define delay_memsync
24
  set $delay = 0
25
  while ($delay < 10000)
26
    set $delay += 1
27
  end
28
end
29
 
30
define setup-cs
31
  # 2MB FLASH on CS0 at 0x80000000
32
  set *(unsigned short *)$CSAR0 = 0x00008000
33
  set *(unsigned long  *)$CSMR0 = 0x001F0101
34
  set *(unsigned short *)$CSCR0 = 0x00001980
35
end
36
 
37
define setup-sdram
38
  # Set PAR_SDRAM to allow SDRAM signals to be enable
39
  set *(unsigned char *)$PAR_SDRAM = 0x3F
40
  # Set PAR_AD to allow 32-bit SDRAM if the external boot device is 16-bit
41
  set *(unsigned char *)$PAR_AD = 0xE1
42
 
43
  # SDRAM
44
  set *(unsigned short *)$DCR   = 0x0446
45
  set *(unsigned long *)$DACR0  = 0x00001300
46
  set *(unsigned long *)$DMR0   = 0x00FC0001
47
 
48
  # Set IP in DACR and init precharge.
49
  set *(unsigned long *)$DACR0 |= 0x00000008
50
  set *(0x00000000)             = 0xAA55AA55
51
  delay
52
 
53
  # Set RE in DACR
54
  set *(unsigned long *)$DACR0 |= 0x00008000
55
  # Issue IMRS
56
  set *(unsigned long *)$DACR0 |= 0x00000040
57
  set *(0x00000400)             = 0xAA55AA55
58
  delay
59
end
60
 
61
define setup-other
62
  # Turn Off WCR
63
  set *(unsigned char *)$WCR = 0x00
64
end
65
 
66
define setup-and-load
67
  bdm-reset
68
 
69
  # Set VBR to the vector table.
70
  set $vbr = 0x00000000
71
  # Set internal SRAM to start at 0x20000000
72
  set $rambar = 0x20000001
73
 
74
  setup-other
75
  setup-cs
76
  setup-sdram
77
end
78
 
79
define debug-sramtest
80
  set $srambase = 0x20000000
81
  set $sramsize = 0x00010000
82
  set $j = 0
83
  printf "Testing SRAM : 0x%08X - 0x%08X\n", $srambase, ($srambase + $sramsize)
84
  set $i = $srambase
85
  while $i < ($srambase + $sramsize)
86
    set *(unsigned long *)($i) = 0xAA55AA55
87
    delay_memsync
88
    if 0xAA55AA55 != *(unsigned long *)$i
89
      printf "  0x%08X = FAIL\n", $i
90
    else
91
      printf "  0x%08X = OK", $i
92
      if $j % 4 == 3
93
        printf "\n"
94
      end
95
      set $j = $j + 1
96
    end
97
    set $i = $i + 0x400
98
  end
99
en
100
 
101
define debug-ramtest
102
  set $sdrambase = 0x00000000
103
  set $sdramsize = 0x01000000
104
  set $j = 0
105
  printf "Testing SDRAM : 0x%08X - 0x%08X\n", $sdrambase, ($sdrambase + $sdramsize)
106
  set $i = $sdrambase
107
  while $i < ($sdrambase + $sdramsize)
108
    set *(unsigned long *)($i) = 0xAA55AA55
109
    delay_memsync
110
    if 0xAA55AA55 != *(unsigned long *)$i
111
      printf "  0x%08X = FAIL\n", $i
112
    else
113
      printf "  0x%08X = OK", $i
114
      if $j % 4 == 3
115
        printf "\n"
116
      end
117
      set $j = $j + 1
118
    end
119
    set $i = $i + 0x10000
120
  end
121
  printf "\n"
122
end
123
 
124
define execute
125
  set $pc = *(long *)0x00000004
126
  tbreak main
127
  tk gdbtk_update
128
end
129
 
130
define debug-printexception
131
  printf "vector: %d", *(unsigned short *)$sp >> 2 &0x1F
132
  printf "old pc: 0x%08x", *(unsigned long *)($sp + 4)
133
  printf "old sr: 0x%02x", *(unsigned short *)($sp + 2)
134
end

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.