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URL https://opencores.org/ocsvn/openrisc_2011-10-31/openrisc_2011-10-31/trunk

Subversion Repositories openrisc_2011-10-31

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [lwIP_MCF5235_GCC/] [m5235.gdb] - Blame information for rev 611

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Line No. Rev Author Line
1 583 jeremybenn
set $IPSBAR = 0x40000000
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set $DCR    = $IPSBAR + 0x000040
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set $DACR0  = $IPSBAR + 0x000048
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set $DMR0   = $IPSBAR + 0x00004C
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set $CSAR0  = $IPSBAR + 0x000080
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set $CSMR0  = $IPSBAR + 0x000084
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set $CSCR0  = $IPSBAR + 0x00008A
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set $PAR_SDRAM = $IPSBAR + 0x100046
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set $PAR_AD    = $IPSBAR + 0x100040
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set $WCR    = $IPSBAR + 0x140000
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define delay
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  set $delay = 0
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  while ($delay < 20000)
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    set $delay += 1
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  end
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end
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define delay_memsync
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  set $delay = 0
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  while ($delay < 10000)
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    set $delay += 1
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  end
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end
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define setup-cs
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  # 2MB FLASH on CS0 at 0x80000000
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  set *(unsigned short *)$CSAR0 = 0x00008000
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  set *(unsigned long  *)$CSMR0 = 0x001F0101
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  set *(unsigned short *)$CSCR0 = 0x00001980
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end
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define setup-sdram
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  # Set PAR_SDRAM to allow SDRAM signals to be enable
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  set *(unsigned char *)$PAR_SDRAM = 0x3F
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  # Set PAR_AD to allow 32-bit SDRAM if the external boot device is 16-bit
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  set *(unsigned char *)$PAR_AD = 0xE1
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  # SDRAM
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  set *(unsigned short *)$DCR   = 0x0446
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  set *(unsigned long *)$DACR0  = 0x00001300
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  set *(unsigned long *)$DMR0   = 0x00FC0001
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  # Set IP in DACR and init precharge.
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  set *(unsigned long *)$DACR0 |= 0x00000008
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  set *(0x00000000)             = 0xAA55AA55
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  delay
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  # Set RE in DACR
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  set *(unsigned long *)$DACR0 |= 0x00008000
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  # Issue IMRS
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  set *(unsigned long *)$DACR0 |= 0x00000040
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  set *(0x00000400)             = 0xAA55AA55
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  delay
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end
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define setup-other
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  # Turn Off WCR
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  set *(unsigned char *)$WCR = 0x00
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end
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define setup-and-load
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  bdm-reset
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  # Set VBR to the vector table.
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  set $vbr = 0x00000000
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  # Set internal SRAM to start at 0x20000000
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  set $rambar = 0x20000001
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  setup-other
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  setup-cs
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  setup-sdram
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end
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define debug-sramtest
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  set $srambase = 0x20000000
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  set $sramsize = 0x00010000
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  set $j = 0
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  printf "Testing SRAM : 0x%08X - 0x%08X\n", $srambase, ($srambase + $sramsize)
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  set $i = $srambase
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  while $i < ($srambase + $sramsize)
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    set *(unsigned long *)($i) = 0xAA55AA55
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    delay_memsync
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    if 0xAA55AA55 != *(unsigned long *)$i
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      printf "  0x%08X = FAIL\n", $i
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    else
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      printf "  0x%08X = OK", $i
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      if $j % 4 == 3
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        printf "\n"
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      end
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      set $j = $j + 1
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    end
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    set $i = $i + 0x400
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  end
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en
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define debug-ramtest
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  set $sdrambase = 0x00000000
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  set $sdramsize = 0x01000000
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  set $j = 0
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  printf "Testing SDRAM : 0x%08X - 0x%08X\n", $sdrambase, ($sdrambase + $sdramsize)
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  set $i = $sdrambase
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  while $i < ($sdrambase + $sdramsize)
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    set *(unsigned long *)($i) = 0xAA55AA55
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    delay_memsync
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    if 0xAA55AA55 != *(unsigned long *)$i
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      printf "  0x%08X = FAIL\n", $i
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    else
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      printf "  0x%08X = OK", $i
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      if $j % 4 == 3
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        printf "\n"
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      end
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      set $j = $j + 1
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    end
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    set $i = $i + 0x10000
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  end
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  printf "\n"
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end
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define execute
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  set $pc = *(long *)0x00000004
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  tbreak main
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  tk gdbtk_update
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end
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define debug-printexception
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  printf "vector: %d", *(unsigned short *)$sp >> 2 &0x1F
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  printf "old pc: 0x%08x", *(unsigned long *)($sp + 4)
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  printf "old sr: 0x%02x", *(unsigned short *)($sp + 2)
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end

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