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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Demo/] [uIP_Demo_Rowley_ARM7/] [Philips_LPC210X_Startup.s] - Blame information for rev 593

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Line No. Rev Author Line
1 583 jeremybenn
/*****************************************************************************
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 * Copyright (c) 2001, 2002 Rowley Associates Limited.                       *
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 *                                                                           *
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 * This file may be distributed under the terms of the License Agreement     *
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 * provided with this software.                                              *
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 *                                                                           *
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 * THIS FILE IS PROVIDED AS IS WITH NO WARRANTY OF ANY KIND, INCLUDING THE   *
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 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. *
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 *****************************************************************************/
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/*****************************************************************************
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 *                           Preprocessor Definitions
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 *                           ------------------------
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 *
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 * VECTORED_IRQ_INTERRUPTS
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 *
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 *   Enable vectored IRQ interrupts. If defined, the PC register will be loaded
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 *   with the contents of the VICVectAddr register on an IRQ exception.
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 *
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 * USE_PLL
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 *
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 *   If defined, connect PLL as processor clock source. If undefined, the
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 *   oscillator clock will be used.
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 *
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 * PLLCFG_VAL
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 *
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 *   Override the default PLL configuration (multiplier = 5, divider = 2)
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 *   by defining PLLCFG_VAL.
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 *
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 * USE_MAM
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 *
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 *   If defined then the memory accelerator module (MAM) will be enabled.
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 *
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 * MAMCR_VAL & MAMTIM_VAL
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 *
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 *   Override the default MAM configuration (fully enabled, 3 fetch cycles)
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 *   by defining MAMCR_VAL and MAMTIM_VAL.
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 *
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 * VPBDIV_VAL
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 *
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 *   If defined then this value will be used to configure the VPB divider.
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 *
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 * SRAM_EXCEPTIONS
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 *
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 *   If defined, enable copying and re-mapping of interrupt vectors from User
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 *   FLASH to SRAM. If undefined, interrupt vectors will be mapped in User
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 *   FLASH.
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 *
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 *****************************************************************************/
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#ifndef PLLCFG_VAL
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#define PLLCFG_VAL 0x24
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#endif
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#ifndef MAMCR_VAL
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#define MAMCR_VAL 2
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#endif
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#ifndef MAMTIM_VAL
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#define MAMTIM_VAL 3
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#endif
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#define MAMCR_OFFS   0x000
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#define MAMTIM_OFFS  0x004
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#define PLLCON_OFFS  0x080
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#define PLLCFG_OFFS  0x084
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#define PLLSTAT_OFFS 0x088
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#define PLLFEED_OFFS 0x08C
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#define VPBDIV_OFFS  0x100
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  .section .vectors, "ax"
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  .code 32
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  .align 0
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/*****************************************************************************
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 * Exception Vectors                                                         *
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 *****************************************************************************/
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_vectors:
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  ldr pc, [pc, #reset_handler_address - . - 8]  /* reset */
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  ldr pc, [pc, #undef_handler_address - . - 8]  /* undefined instruction */
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  ldr pc, [pc, #swi_handler_address - . - 8]    /* swi handler */
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  ldr pc, [pc, #pabort_handler_address - . - 8] /* abort prefetch */
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  ldr pc, [pc, #dabort_handler_address - . - 8] /* abort data */
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#ifdef VECTORED_IRQ_INTERRUPTS
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  .word 0xB9205F84                              /* boot loader checksum */
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  ldr pc, [pc, #-0xFF0]                         /* irq handler */
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#else
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  .word 0xB8A06F60                              /* boot loader checksum */
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  ldr pc, [pc, #irq_handler_address - . - 8]    /* irq handler */
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#endif
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  ldr pc, [pc, #fiq_handler_address - . - 8]    /* fiq handler */
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reset_handler_address:
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  .word reset_handler
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undef_handler_address:
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  .word undef_handler
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swi_handler_address:
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  .word swi_handler
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pabort_handler_address:
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  .word pabort_handler
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dabort_handler_address:
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  .word dabort_handler
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irq_handler_address:
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  .word irq_handler
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fiq_handler_address:
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  .word fiq_handler
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  .section .init, "ax"
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  .code 32
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  .align 0
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/******************************************************************************
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 *                                                                            *
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 * Default exception handlers                                                 *
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 *                                                                            *
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 ******************************************************************************/
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reset_handler:
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#if defined(USE_PLL) || defined(USE_MAM) || defined(VPBDIV_VAL)
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  ldr r0, =0xE01FC000
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#endif
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#if defined(USE_PLL)
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  /* Configure PLL Multiplier/Divider */
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  ldr r1, =PLLCFG_VAL
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  str r1, [r0, #PLLCFG_OFFS]
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  /* Enable PLL */
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  mov r1, #0x1
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  str r1, [r0, #PLLCON_OFFS]
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  mov r1, #0xAA
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  str r1, [r0, #PLLFEED_OFFS]
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  mov r1, #0x55
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  str r1, [r0, #PLLFEED_OFFS]
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  /* Wait for PLL to lock */
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pll_lock_loop:
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  ldr r1, [r0, #PLLSTAT_OFFS]
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  tst r1, #0x400
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  beq pll_lock_loop
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  /* PLL Locked, connect PLL as clock source */
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  mov r1, #0x3
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  str r1, [r0, #PLLCON_OFFS]
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  mov r1, #0xAA
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  str r1, [r0, #PLLFEED_OFFS]
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  mov r1, #0x55
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  str r1, [r0, #PLLFEED_OFFS]
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#endif
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#if defined(USE_MAM)
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  mov r1, #0
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  str r1, [r0, #MAMCR_OFFS]
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  ldr r1, =MAMTIM_VAL
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  str r1, [r0, #MAMTIM_OFFS]
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  ldr r1, =MAMCR_VAL
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  str r1, [r0, #MAMCR_OFFS]
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#endif
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#if defined(VPBDIV_VAL)
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  ldr r1, =VPBDIV_VAL
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  str r1, [r0, #VPBDIV_OFFS]
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#endif
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#if defined(SRAM_EXCEPTIONS)
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  /* Copy exception vectors into SRAM */
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  mov r8, #0x40000000
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  ldr r9, =_vectors
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  ldmia r9!, {r0-r7}
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  stmia r8!, {r0-r7}
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  ldmia r9!, {r0-r6}
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  stmia r8!, {r0-r6}
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  /* Re-map interrupt vectors from SRAM */
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  ldr r0, MEMMAP
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  mov r1, #2 /* User RAM Mode. Interrupt vectors are re-mapped from SRAM */
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  str r1, [r0]
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#endif /* SRAM_EXCEPTIONS */
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  b _start
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#ifdef SRAM_EXCEPTIONS
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MEMMAP:
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  .word 0xE01FC040
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#endif
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/******************************************************************************
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 *                                                                            *
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 * Default exception handlers                                                 *
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 * These are declared weak symbols so they can be redefined in user code.     *
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 *                                                                            *
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 ******************************************************************************/
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undef_handler:
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  b undef_handler
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swi_handler:
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  b swi_handler
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pabort_handler:
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  b pabort_handler
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dabort_handler:
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  b dabort_handler
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irq_handler:
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  b irq_handler
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fiq_handler:
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  b fiq_handler
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  .weak undef_handler, swi_handler, pabort_handler, dabort_handler, irq_handler, fiq_handler
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