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jeremybenn |
#ifndef lpc210x_h
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#define lpc210x_h
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/*******************************************************************************
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lpc210x.h - Register defs for Philips LPC210X: LPC2104, LPC2105 and LPC2106
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THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND,
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EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY
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WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY
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PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS
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OF OTHERS.
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This file may be freely used for commercial and non-commercial applications,
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including being redistributed with any tools.
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If you find a problem with the file, please report it so that it can be fixed.
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Created by Sten Larsson (sten_larsson at yahoo com)
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Edited by Richard Barry.
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*******************************************************************************/
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#define REG8 (volatile unsigned char*)
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#define REG16 (volatile unsigned short*)
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#define REG32 (volatile unsigned int*)
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/*##############################################################################
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## MISC
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##############################################################################*/
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/* Constants for data to put in IRQ/FIQ Exception Vectors */
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#define VECTDATA_IRQ 0xE51FFFF0 /* LDR PC,[PC,#-0xFF0] */
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#define VECTDATA_FIQ /* __TODO */
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/*##############################################################################
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## VECTORED INTERRUPT CONTROLLER
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##############################################################################*/
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#define VICIRQStatus (*(REG32 (0xFFFFF000)))
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#define VICFIQStatus (*(REG32 (0xFFFFF004)))
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#define VICRawIntr (*(REG32 (0xFFFFF008)))
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#define VICIntSelect (*(REG32 (0xFFFFF00C)))
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#define VICIntEnable (*(REG32 (0xFFFFF010)))
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#define VICIntEnClear (*(REG32 (0xFFFFF014)))
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#define VICSoftInt (*(REG32 (0xFFFFF018)))
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#define VICSoftIntClear (*(REG32 (0xFFFFF01C)))
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#define VICProtection (*(REG32 (0xFFFFF020)))
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#define VICVectAddr (*(REG32 (0xFFFFF030)))
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#define VICDefVectAddr (*(REG32 (0xFFFFF034)))
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#define VICVectAddr0 (*(REG32 (0xFFFFF100)))
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#define VICVectAddr1 (*(REG32 (0xFFFFF104)))
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#define VICVectAddr2 (*(REG32 (0xFFFFF108)))
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#define VICVectAddr3 (*(REG32 (0xFFFFF10C)))
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#define VICVectAddr4 (*(REG32 (0xFFFFF110)))
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#define VICVectAddr5 (*(REG32 (0xFFFFF114)))
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#define VICVectAddr6 (*(REG32 (0xFFFFF118)))
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#define VICVectAddr7 (*(REG32 (0xFFFFF11C)))
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#define VICVectAddr8 (*(REG32 (0xFFFFF120)))
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#define VICVectAddr9 (*(REG32 (0xFFFFF124)))
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#define VICVectAddr10 (*(REG32 (0xFFFFF128)))
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#define VICVectAddr11 (*(REG32 (0xFFFFF12C)))
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#define VICVectAddr12 (*(REG32 (0xFFFFF130)))
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#define VICVectAddr13 (*(REG32 (0xFFFFF134)))
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#define VICVectAddr14 (*(REG32 (0xFFFFF138)))
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#define VICVectAddr15 (*(REG32 (0xFFFFF13C)))
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#define VICVectCntl0 (*(REG32 (0xFFFFF200)))
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#define VICVectCntl1 (*(REG32 (0xFFFFF204)))
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#define VICVectCntl2 (*(REG32 (0xFFFFF208)))
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#define VICVectCntl3 (*(REG32 (0xFFFFF20C)))
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#define VICVectCntl4 (*(REG32 (0xFFFFF210)))
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#define VICVectCntl5 (*(REG32 (0xFFFFF214)))
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#define VICVectCntl6 (*(REG32 (0xFFFFF218)))
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#define VICVectCntl7 (*(REG32 (0xFFFFF21C)))
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#define VICVectCntl8 (*(REG32 (0xFFFFF220)))
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#define VICVectCntl9 (*(REG32 (0xFFFFF224)))
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#define VICVectCntl10 (*(REG32 (0xFFFFF228)))
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#define VICVectCntl11 (*(REG32 (0xFFFFF22C)))
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#define VICVectCntl12 (*(REG32 (0xFFFFF230)))
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#define VICVectCntl13 (*(REG32 (0xFFFFF234)))
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#define VICVectCntl14 (*(REG32 (0xFFFFF238)))
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#define VICVectCntl15 (*(REG32 (0xFFFFF23C)))
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#define VICITCR (*(REG32 (0xFFFFF300)))
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#define VICITIP1 (*(REG32 (0xFFFFF304)))
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#define VICITIP2 (*(REG32 (0xFFFFF308)))
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#define VICITOP1 (*(REG32 (0xFFFFF30C)))
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#define VICITOP2 (*(REG32 (0xFFFFF310)))
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#define VICPeriphID0 (*(REG32 (0xFFFFFFE0)))
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#define VICPeriphID1 (*(REG32 (0xFFFFFFE4)))
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#define VICPeriphID2 (*(REG32 (0xFFFFFFE8)))
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#define VICPeriphID3 (*(REG32 (0xFFFFFFEC)))
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#define VICIntEnClr VICIntEnClear
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#define VICSoftIntClr VICSoftIntClear
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/*##############################################################################
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## PCB - Pin Connect Block
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##############################################################################*/
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#define PCB_PINSEL0 (*(REG32 (0xE002C000)))
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#define PCB_PINSEL1 (*(REG32 (0xE002C004)))
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/*##############################################################################
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## GPIO - General Purpose I/O
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##############################################################################*/
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#define GPIO_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */
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#define GPIO_IOSET (*(REG32 (0xE0028004)))
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#define GPIO_IODIR (*(REG32 (0xE0028008)))
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#define GPIO_IOCLR (*(REG32 (0xE002800C)))
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#define GPIO0_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */
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#define GPIO0_IOSET (*(REG32 (0xE0028004)))
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#define GPIO0_IODIR (*(REG32 (0xE0028008)))
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#define GPIO0_IOCLR (*(REG32 (0xE002800C)))
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/*##############################################################################
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## UART0 / UART1
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##############################################################################*/
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/* ---- UART 0 --------------------------------------------- */
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#define UART0_RBR (*(REG32 (0xE000C000)))
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#define UART0_THR (*(REG32 (0xE000C000)))
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#define UART0_IER (*(REG32 (0xE000C004)))
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#define UART0_IIR (*(REG32 (0xE000C008)))
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#define UART0_FCR (*(REG32 (0xE000C008)))
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#define UART0_LCR (*(REG32 (0xE000C00C)))
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#define UART0_LSR (*(REG32 (0xE000C014)))
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#define UART0_SCR (*(REG32 (0xE000C01C)))
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#define UART0_DLL (*(REG32 (0xE000C000)))
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#define UART0_DLM (*(REG32 (0xE000C004)))
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/* ---- UART 1 --------------------------------------------- */
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#define UART1_RBR (*(REG32 (0xE0010000)))
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#define UART1_THR (*(REG32 (0xE0010000)))
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#define UART1_IER (*(REG32 (0xE0010004)))
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#define UART1_IIR (*(REG32 (0xE0010008)))
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#define UART1_FCR (*(REG32 (0xE0010008)))
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#define UART1_LCR (*(REG32 (0xE001000C)))
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#define UART1_LSR (*(REG32 (0xE0010014)))
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#define UART1_SCR (*(REG32 (0xE001001C)))
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#define UART1_DLL (*(REG32 (0xE0010000)))
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#define UART1_DLM (*(REG32 (0xE0010004)))
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#define UART1_MCR (*(REG32 (0xE0010010)))
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#define UART1_MSR (*(REG32 (0xE0010018)))
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/*##############################################################################
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## I2C
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##############################################################################*/
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#define I2C_I2CONSET (*(REG32 (0xE001C000)))
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#define I2C_I2STAT (*(REG32 (0xE001C004)))
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#define I2C_I2DAT (*(REG32 (0xE001C008)))
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#define I2C_I2ADR (*(REG32 (0xE001C00C)))
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#define I2C_I2SCLH (*(REG32 (0xE001C010)))
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#define I2C_I2SCLL (*(REG32 (0xE001C014)))
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#define I2C_I2CONCLR (*(REG32 (0xE001C018)))
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/*##############################################################################
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## SPI - Serial Peripheral Interface
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##############################################################################*/
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#define SPI_SPCR (*(REG32 (0xE0020000)))
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#define SPI_SPSR (*(REG32 (0xE0020004)))
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#define SPI_SPDR (*(REG32 (0xE0020008)))
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#define SPI_SPCCR (*(REG32 (0xE002000C)))
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#define SPI_SPTCR (*(REG32 (0xE0020010)))
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#define SPI_SPTSR (*(REG32 (0xE0020014)))
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#define SPI_SPTOR (*(REG32 (0xE0020018)))
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#define SPI_SPINT (*(REG32 (0xE002001C)))
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/*##############################################################################
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## Timer 0 and Timer 1
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##############################################################################*/
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/* ---- Timer 0 -------------------------------------------- */
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#define T0_IR (*(REG32 (0xE0004000)))
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#define T0_TCR (*(REG32 (0xE0004004)))
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#define T0_TC (*(REG32 (0xE0004008)))
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#define T0_PR (*(REG32 (0xE000400C)))
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#define T0_PC (*(REG32 (0xE0004010)))
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#define T0_MCR (*(REG32 (0xE0004014)))
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#define T0_MR0 (*(REG32 (0xE0004018)))
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#define T0_MR1 (*(REG32 (0xE000401C)))
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#define T0_MR2 (*(REG32 (0xE0004020)))
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#define T0_MR3 (*(REG32 (0xE0004024)))
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#define T0_CCR (*(REG32 (0xE0004028)))
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#define T0_CR0 (*(REG32 (0xE000402C)))
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#define T0_CR1 (*(REG32 (0xE0004030)))
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#define T0_CR2 (*(REG32 (0xE0004034)))
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#define T0_CR3 (*(REG32 (0xE0004038)))
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#define T0_EMR (*(REG32 (0xE000403C)))
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| 204 |
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/* ---- Timer 1 -------------------------------------------- */
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#define T1_IR (*(REG32 (0xE0008000)))
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#define T1_TCR (*(REG32 (0xE0008004)))
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#define T1_TC (*(REG32 (0xE0008008)))
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#define T1_PR (*(REG32 (0xE000800C)))
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#define T1_PC (*(REG32 (0xE0008010)))
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#define T1_MCR (*(REG32 (0xE0008014)))
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#define T1_MR0 (*(REG32 (0xE0008018)))
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#define T1_MR1 (*(REG32 (0xE000801C)))
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#define T1_MR2 (*(REG32 (0xE0008020)))
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#define T1_MR3 (*(REG32 (0xE0008024)))
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#define T1_CCR (*(REG32 (0xE0008028)))
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#define T1_CR0 (*(REG32 (0xE000802C)))
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#define T1_CR1 (*(REG32 (0xE0008030)))
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| 218 |
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#define T1_CR2 (*(REG32 (0xE0008034)))
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| 219 |
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#define T1_CR3 (*(REG32 (0xE0008038)))
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#define T1_EMR (*(REG32 (0xE000803C)))
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| 222 |
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/*##############################################################################
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## PWM
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##############################################################################*/
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| 226 |
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| 227 |
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#define PWM_IR (*(REG32 (0xE0014000)))
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#define PWM_TCR (*(REG32 (0xE0014004)))
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#define PWM_TC (*(REG32 (0xE0014008)))
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| 230 |
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#define PWM_PR (*(REG32 (0xE001400C)))
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| 231 |
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#define PWM_PC (*(REG32 (0xE0014010)))
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| 232 |
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#define PWM_MCR (*(REG32 (0xE0014014)))
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| 233 |
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#define PWM_MR0 (*(REG32 (0xE0014018)))
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#define PWM_MR1 (*(REG32 (0xE001401C)))
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| 235 |
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#define PWM_MR2 (*(REG32 (0xE0014020)))
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#define PWM_MR3 (*(REG32 (0xE0014024)))
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| 237 |
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#define PWM_MR4 (*(REG32 (0xE0014040)))
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| 238 |
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#define PWM_MR5 (*(REG32 (0xE0014044)))
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| 239 |
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#define PWM_MR6 (*(REG32 (0xE0014048)))
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| 240 |
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#define PWM_EMR (*(REG32 (0xE001403C)))
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| 241 |
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#define PWM_PCR (*(REG32 (0xE001404C)))
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| 242 |
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#define PWM_LER (*(REG32 (0xE0014050)))
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| 243 |
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#define PWM_CCR (*(REG32 (0xE0014028)))
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| 244 |
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#define PWM_CR0 (*(REG32 (0xE001402C)))
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| 245 |
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#define PWM_CR1 (*(REG32 (0xE0014030)))
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| 246 |
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#define PWM_CR2 (*(REG32 (0xE0014034)))
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| 247 |
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#define PWM_CR3 (*(REG32 (0xE0014038)))
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| 248 |
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| 249 |
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/*##############################################################################
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| 250 |
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## RTC
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| 251 |
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##############################################################################*/
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| 252 |
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| 253 |
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/* ---- RTC: Miscellaneous Register Group ------------------ */
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| 254 |
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#define RTC_ILR (*(REG32 (0xE0024000)))
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| 255 |
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#define RTC_CTC (*(REG32 (0xE0024004)))
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| 256 |
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#define RTC_CCR (*(REG32 (0xE0024008)))
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| 257 |
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#define RTC_CIIR (*(REG32 (0xE002400C)))
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| 258 |
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#define RTC_AMR (*(REG32 (0xE0024010)))
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| 259 |
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#define RTC_CTIME0 (*(REG32 (0xE0024014)))
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| 260 |
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#define RTC_CTIME1 (*(REG32 (0xE0024018)))
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| 261 |
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#define RTC_CTIME2 (*(REG32 (0xE002401C)))
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| 262 |
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| 263 |
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/* ---- RTC: Timer Control Group --------------------------- */
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| 264 |
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#define RTC_SEC (*(REG32 (0xE0024020)))
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| 265 |
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#define RTC_MIN (*(REG32 (0xE0024024)))
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| 266 |
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#define RTC_HOUR (*(REG32 (0xE0024028)))
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| 267 |
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#define RTC_DOM (*(REG32 (0xE002402C)))
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| 268 |
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#define RTC_DOW (*(REG32 (0xE0024030)))
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| 269 |
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#define RTC_DOY (*(REG32 (0xE0024034)))
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| 270 |
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#define RTC_MONTH (*(REG32 (0xE0024038)))
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| 271 |
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#define RTC_YEAR (*(REG32 (0xE002403C)))
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| 272 |
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| 273 |
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/* ---- RTC: Alarm Control Group --------------------------- */
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| 274 |
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#define RTC_ALSEC (*(REG32 (0xE0024060)))
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| 275 |
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#define RTC_ALMIN (*(REG32 (0xE0024064)))
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| 276 |
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#define RTC_ALHOUR (*(REG32 (0xE0024068)))
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| 277 |
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#define RTC_ALDOM (*(REG32 (0xE002406C)))
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| 278 |
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#define RTC_ALDOW (*(REG32 (0xE0024070)))
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| 279 |
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#define RTC_ALDOY (*(REG32 (0xE0024074)))
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| 280 |
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#define RTC_ALMON (*(REG32 (0xE0024078)))
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| 281 |
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#define RTC_ALYEAR (*(REG32 (0xE002407C)))
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| 282 |
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| 283 |
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|
/* ---- RTC: Reference Clock Divider Group ----------------- */
|
| 284 |
|
|
#define RTC_PREINT (*(REG32 (0xE0024080)))
|
| 285 |
|
|
#define RTC_PREFRAC (*(REG32 (0xE0024084)))
|
| 286 |
|
|
|
| 287 |
|
|
|
| 288 |
|
|
/*##############################################################################
|
| 289 |
|
|
## WD - Watchdog
|
| 290 |
|
|
##############################################################################*/
|
| 291 |
|
|
|
| 292 |
|
|
#define WD_WDMOD (*(REG32 (0xE0000000)))
|
| 293 |
|
|
#define WD_WDTC (*(REG32 (0xE0000004)))
|
| 294 |
|
|
#define WD_WDFEED (*(REG32 (0xE0000008)))
|
| 295 |
|
|
#define WD_WDTV (*(REG32 (0xE000000C)))
|
| 296 |
|
|
|
| 297 |
|
|
|
| 298 |
|
|
/*##############################################################################
|
| 299 |
|
|
## System Control Block
|
| 300 |
|
|
##############################################################################*/
|
| 301 |
|
|
|
| 302 |
|
|
#define SCB_EXTINT (*(REG32 (0xE01FC140)))
|
| 303 |
|
|
#define SCB_EXTWAKE (*(REG32 (0xE01FC144)))
|
| 304 |
|
|
#define SCB_MEMMAP (*(REG32 (0xE01FC040)))
|
| 305 |
|
|
#define SCB_PLLCON (*(REG32 (0xE01FC080)))
|
| 306 |
|
|
#define SCB_PLLCFG (*(REG32 (0xE01FC084)))
|
| 307 |
|
|
#define SCB_PLLSTAT (*(REG32 (0xE01FC088)))
|
| 308 |
|
|
#define SCB_PLLFEED (*(REG32 (0xE01FC08C)))
|
| 309 |
|
|
#define SCB_PCON (*(REG32 (0xE01FC0C0)))
|
| 310 |
|
|
#define SCB_PCONP (*(REG32 (0xE01FC0C4)))
|
| 311 |
|
|
#define SCB_VPBDIV (*(REG32 (0xE01FC100)))
|
| 312 |
|
|
|
| 313 |
|
|
/*##############################################################################
|
| 314 |
|
|
## Memory Accelerator Module (MAM)
|
| 315 |
|
|
##############################################################################*/
|
| 316 |
|
|
|
| 317 |
|
|
#define MAM_TIM (*(REG32 (0xE01FC004)))
|
| 318 |
|
|
#define MAM_CR (*(REG32 (0xE01FC000)))
|
| 319 |
|
|
|
| 320 |
|
|
#endif /* lpc210x_h */
|
| 321 |
|
|
|
