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// - ----------------------------------------------------------------------------

// -          ATMEL Microcontroller Software Support  -  ROUSSET  -

// - ----------------------------------------------------------------------------

// -  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR

// -  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF

// -  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE

// -  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,

// -  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT

// -  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,

// -  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF

// -  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING

// -  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,

// -  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

// - ----------------------------------------------------------------------------

// - File Name           : AT91SAM7X256.h

// - Object              : AT91SAM7X256 definitions

// - Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)

// - 

// - CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//

// - CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//

// - CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//

// - CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//

// - CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//

// - CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//

// - CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//

// - CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//

// - CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//

// - CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//

// - CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//

// - CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//

// - CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//

// - CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//

// - CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//

// - CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//

// - CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//

// - CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//

// - CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//

// - CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//

// - CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//

// - CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//

// - CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//

// - CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//

// - CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//

// - ----------------------------------------------------------------------------

#ifndef AT91SAM7X256_H

#define AT91SAM7X256_H

typedef volatile unsigned int AT91_REG;// Hardware register definition

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR System Peripherals

// *****************************************************************************

typedef struct _AT91S_SYS {

        AT91_REG         AIC_SMR[32];   // Source Mode Register

        AT91_REG         AIC_SVR[32];   // Source Vector Register

        AT91_REG         AIC_IVR;       // IRQ Vector Register

        AT91_REG         AIC_FVR;       // FIQ Vector Register

        AT91_REG         AIC_ISR;       // Interrupt Status Register

        AT91_REG         AIC_IPR;       // Interrupt Pending Register

        AT91_REG         AIC_IMR;       // Interrupt Mask Register

        AT91_REG         AIC_CISR;      // Core Interrupt Status Register

        AT91_REG         Reserved0[2];  // 

        AT91_REG         AIC_IECR;      // Interrupt Enable Command Register

        AT91_REG         AIC_IDCR;      // Interrupt Disable Command Register

        AT91_REG         AIC_ICCR;      // Interrupt Clear Command Register

        AT91_REG         AIC_ISCR;      // Interrupt Set Command Register

        AT91_REG         AIC_EOICR;     // End of Interrupt Command Register

        AT91_REG         AIC_SPU;       // Spurious Vector Register

        AT91_REG         AIC_DCR;       // Debug Control Register (Protect)

        AT91_REG         Reserved1[1];  // 

        AT91_REG         AIC_FFER;      // Fast Forcing Enable Register

        AT91_REG         AIC_FFDR;      // Fast Forcing Disable Register

        AT91_REG         AIC_FFSR;      // Fast Forcing Status Register

        AT91_REG         Reserved2[45];         // 

        AT91_REG         DBGU_CR;       // Control Register

        AT91_REG         DBGU_MR;       // Mode Register

        AT91_REG         DBGU_IER;      // Interrupt Enable Register

        AT91_REG         DBGU_IDR;      // Interrupt Disable Register

        AT91_REG         DBGU_IMR;      // Interrupt Mask Register

        AT91_REG         DBGU_CSR;      // Channel Status Register

        AT91_REG         DBGU_RHR;      // Receiver Holding Register

        AT91_REG         DBGU_THR;      // Transmitter Holding Register

        AT91_REG         DBGU_BRGR;     // Baud Rate Generator Register

        AT91_REG         Reserved3[7];  // 

        AT91_REG         DBGU_CIDR;     // Chip ID Register

        AT91_REG         DBGU_EXID;     // Chip ID Extension Register

        AT91_REG         DBGU_FNTR;     // Force NTRST Register

        AT91_REG         Reserved4[45];         // 

        AT91_REG         DBGU_RPR;      // Receive Pointer Register

        AT91_REG         DBGU_RCR;      // Receive Counter Register

        AT91_REG         DBGU_TPR;      // Transmit Pointer Register

        AT91_REG         DBGU_TCR;      // Transmit Counter Register

        AT91_REG         DBGU_RNPR;     // Receive Next Pointer Register

        AT91_REG         DBGU_RNCR;     // Receive Next Counter Register

        AT91_REG         DBGU_TNPR;     // Transmit Next Pointer Register

        AT91_REG         DBGU_TNCR;     // Transmit Next Counter Register

        AT91_REG         DBGU_PTCR;     // PDC Transfer Control Register

        AT91_REG         DBGU_PTSR;     // PDC Transfer Status Register

        AT91_REG         Reserved5[54];         // 

        AT91_REG         PIOA_PER;      // PIO Enable Register

        AT91_REG         PIOA_PDR;      // PIO Disable Register

        AT91_REG         PIOA_PSR;      // PIO Status Register

        AT91_REG         Reserved6[1];  // 

        AT91_REG         PIOA_OER;      // Output Enable Register

        AT91_REG         PIOA_ODR;      // Output Disable Registerr

        AT91_REG         PIOA_OSR;      // Output Status Register

        AT91_REG         Reserved7[1];  // 

        AT91_REG         PIOA_IFER;     // Input Filter Enable Register

        AT91_REG         PIOA_IFDR;     // Input Filter Disable Register

        AT91_REG         PIOA_IFSR;     // Input Filter Status Register

        AT91_REG         Reserved8[1];  // 

        AT91_REG         PIOA_SODR;     // Set Output Data Register

        AT91_REG         PIOA_CODR;     // Clear Output Data Register

        AT91_REG         PIOA_ODSR;     // Output Data Status Register

        AT91_REG         PIOA_PDSR;     // Pin Data Status Register

        AT91_REG         PIOA_IER;      // Interrupt Enable Register

        AT91_REG         PIOA_IDR;      // Interrupt Disable Register

        AT91_REG         PIOA_IMR;      // Interrupt Mask Register

        AT91_REG         PIOA_ISR;      // Interrupt Status Register

        AT91_REG         PIOA_MDER;     // Multi-driver Enable Register

        AT91_REG         PIOA_MDDR;     // Multi-driver Disable Register

        AT91_REG         PIOA_MDSR;     // Multi-driver Status Register

        AT91_REG         Reserved9[1];  // 

        AT91_REG         PIOA_PPUDR;    // Pull-up Disable Register

        AT91_REG         PIOA_PPUER;    // Pull-up Enable Register

        AT91_REG         PIOA_PPUSR;    // Pull-up Status Register

        AT91_REG         Reserved10[1];         // 

        AT91_REG         PIOA_ASR;      // Select A Register

        AT91_REG         PIOA_BSR;      // Select B Register

        AT91_REG         PIOA_ABSR;     // AB Select Status Register

        AT91_REG         Reserved11[9];         // 

        AT91_REG         PIOA_OWER;     // Output Write Enable Register

        AT91_REG         PIOA_OWDR;     // Output Write Disable Register

        AT91_REG         PIOA_OWSR;     // Output Write Status Register

        AT91_REG         Reserved12[85];        // 

        AT91_REG         PIOB_PER;      // PIO Enable Register

        AT91_REG         PIOB_PDR;      // PIO Disable Register

        AT91_REG         PIOB_PSR;      // PIO Status Register

        AT91_REG         Reserved13[1];         // 

        AT91_REG         PIOB_OER;      // Output Enable Register

        AT91_REG         PIOB_ODR;      // Output Disable Registerr

        AT91_REG         PIOB_OSR;      // Output Status Register

        AT91_REG         Reserved14[1];         // 

        AT91_REG         PIOB_IFER;     // Input Filter Enable Register

        AT91_REG         PIOB_IFDR;     // Input Filter Disable Register

        AT91_REG         PIOB_IFSR;     // Input Filter Status Register

        AT91_REG         Reserved15[1];         // 

        AT91_REG         PIOB_SODR;     // Set Output Data Register

        AT91_REG         PIOB_CODR;     // Clear Output Data Register

        AT91_REG         PIOB_ODSR;     // Output Data Status Register

        AT91_REG         PIOB_PDSR;     // Pin Data Status Register

        AT91_REG         PIOB_IER;      // Interrupt Enable Register

        AT91_REG         PIOB_IDR;      // Interrupt Disable Register

        AT91_REG         PIOB_IMR;      // Interrupt Mask Register

        AT91_REG         PIOB_ISR;      // Interrupt Status Register

        AT91_REG         PIOB_MDER;     // Multi-driver Enable Register

        AT91_REG         PIOB_MDDR;     // Multi-driver Disable Register

        AT91_REG         PIOB_MDSR;     // Multi-driver Status Register

        AT91_REG         Reserved16[1];         // 

        AT91_REG         PIOB_PPUDR;    // Pull-up Disable Register

        AT91_REG         PIOB_PPUER;    // Pull-up Enable Register

        AT91_REG         PIOB_PPUSR;    // Pull-up Status Register

        AT91_REG         Reserved17[1];         // 

        AT91_REG         PIOB_ASR;      // Select A Register

        AT91_REG         PIOB_BSR;      // Select B Register

        AT91_REG         PIOB_ABSR;     // AB Select Status Register

        AT91_REG         Reserved18[9];         // 

        AT91_REG         PIOB_OWER;     // Output Write Enable Register

        AT91_REG         PIOB_OWDR;     // Output Write Disable Register

        AT91_REG         PIOB_OWSR;     // Output Write Status Register

        AT91_REG         Reserved19[341];       // 

        AT91_REG         PMC_SCER;      // System Clock Enable Register

        AT91_REG         PMC_SCDR;      // System Clock Disable Register

        AT91_REG         PMC_SCSR;      // System Clock Status Register

        AT91_REG         Reserved20[1];         // 

        AT91_REG         PMC_PCER;      // Peripheral Clock Enable Register

        AT91_REG         PMC_PCDR;      // Peripheral Clock Disable Register

        AT91_REG         PMC_PCSR;      // Peripheral Clock Status Register

        AT91_REG         Reserved21[1];         // 

        AT91_REG         PMC_MOR;       // Main Oscillator Register

        AT91_REG         PMC_MCFR;      // Main Clock  Frequency Register

        AT91_REG         Reserved22[1];         // 

        AT91_REG         PMC_PLLR;      // PLL Register

        AT91_REG         PMC_MCKR;      // Master Clock Register

        AT91_REG         Reserved23[3];         // 

        AT91_REG         PMC_PCKR[4];   // Programmable Clock Register

        AT91_REG         Reserved24[4];         // 

        AT91_REG         PMC_IER;       // Interrupt Enable Register

        AT91_REG         PMC_IDR;       // Interrupt Disable Register

        AT91_REG         PMC_SR;        // Status Register

        AT91_REG         PMC_IMR;       // Interrupt Mask Register

        AT91_REG         Reserved25[36];        // 

        AT91_REG         RSTC_RCR;      // Reset Control Register

        AT91_REG         RSTC_RSR;      // Reset Status Register

        AT91_REG         RSTC_RMR;      // Reset Mode Register

        AT91_REG         Reserved26[5];         // 

        AT91_REG         RTTC_RTMR;     // Real-time Mode Register

        AT91_REG         RTTC_RTAR;     // Real-time Alarm Register

        AT91_REG         RTTC_RTVR;     // Real-time Value Register

        AT91_REG         RTTC_RTSR;     // Real-time Status Register

        AT91_REG         PITC_PIMR;     // Period Interval Mode Register

        AT91_REG         PITC_PISR;     // Period Interval Status Register

        AT91_REG         PITC_PIVR;     // Period Interval Value Register

        AT91_REG         PITC_PIIR;     // Period Interval Image Register

        AT91_REG         WDTC_WDCR;     // Watchdog Control Register

        AT91_REG         WDTC_WDMR;     // Watchdog Mode Register

        AT91_REG         WDTC_WDSR;     // Watchdog Status Register

        AT91_REG         Reserved27[5];         // 

        AT91_REG         VREG_MR;       // Voltage Regulator Mode Register

} AT91S_SYS, *AT91PS_SYS;

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller

// *****************************************************************************

typedef struct _AT91S_AIC {

        AT91_REG         AIC_SMR[32];   // Source Mode Register

        AT91_REG         AIC_SVR[32];   // Source Vector Register

        AT91_REG         AIC_IVR;       // IRQ Vector Register

        AT91_REG         AIC_FVR;       // FIQ Vector Register

        AT91_REG         AIC_ISR;       // Interrupt Status Register

        AT91_REG         AIC_IPR;       // Interrupt Pending Register

        AT91_REG         AIC_IMR;       // Interrupt Mask Register

        AT91_REG         AIC_CISR;      // Core Interrupt Status Register

        AT91_REG         Reserved0[2];  // 

        AT91_REG         AIC_IECR;      // Interrupt Enable Command Register

        AT91_REG         AIC_IDCR;      // Interrupt Disable Command Register

        AT91_REG         AIC_ICCR;      // Interrupt Clear Command Register

        AT91_REG         AIC_ISCR;      // Interrupt Set Command Register

        AT91_REG         AIC_EOICR;     // End of Interrupt Command Register

        AT91_REG         AIC_SPU;       // Spurious Vector Register

        AT91_REG         AIC_DCR;       // Debug Control Register (Protect)

        AT91_REG         Reserved1[1];  // 

        AT91_REG         AIC_FFER;      // Fast Forcing Enable Register

        AT91_REG         AIC_FFDR;      // Fast Forcing Disable Register

        AT91_REG         AIC_FFSR;      // Fast Forcing Status Register

} AT91S_AIC, *AT91PS_AIC;

// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 

#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level

#define         AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level

#define         AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level

#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type

#define         AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive

#define         AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive

#define         AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered

#define         AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered

#define         AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive

#define         AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered

// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 

#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status

#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status

// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 

#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode

#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller

// *****************************************************************************

typedef struct _AT91S_PDC {

        AT91_REG         PDC_RPR;       // Receive Pointer Register

        AT91_REG         PDC_RCR;       // Receive Counter Register

        AT91_REG         PDC_TPR;       // Transmit Pointer Register

        AT91_REG         PDC_TCR;       // Transmit Counter Register

        AT91_REG         PDC_RNPR;      // Receive Next Pointer Register

        AT91_REG         PDC_RNCR;      // Receive Next Counter Register

        AT91_REG         PDC_TNPR;      // Transmit Next Pointer Register

        AT91_REG         PDC_TNCR;      // Transmit Next Counter Register

        AT91_REG         PDC_PTCR;      // PDC Transfer Control Register

        AT91_REG         PDC_PTSR;      // PDC Transfer Status Register

} AT91S_PDC, *AT91PS_PDC;

// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 

#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable

#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable

#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable

#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable

// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Debug Unit

// *****************************************************************************

typedef struct _AT91S_DBGU {

        AT91_REG         DBGU_CR;       // Control Register

        AT91_REG         DBGU_MR;       // Mode Register

        AT91_REG         DBGU_IER;      // Interrupt Enable Register

        AT91_REG         DBGU_IDR;      // Interrupt Disable Register

        AT91_REG         DBGU_IMR;      // Interrupt Mask Register

        AT91_REG         DBGU_CSR;      // Channel Status Register

        AT91_REG         DBGU_RHR;      // Receiver Holding Register

        AT91_REG         DBGU_THR;      // Transmitter Holding Register

        AT91_REG         DBGU_BRGR;     // Baud Rate Generator Register

        AT91_REG         Reserved0[7];  // 

        AT91_REG         DBGU_CIDR;     // Chip ID Register

        AT91_REG         DBGU_EXID;     // Chip ID Extension Register

        AT91_REG         DBGU_FNTR;     // Force NTRST Register

        AT91_REG         Reserved1[45];         // 

        AT91_REG         DBGU_RPR;      // Receive Pointer Register

        AT91_REG         DBGU_RCR;      // Receive Counter Register

        AT91_REG         DBGU_TPR;      // Transmit Pointer Register

        AT91_REG         DBGU_TCR;      // Transmit Counter Register

        AT91_REG         DBGU_RNPR;     // Receive Next Pointer Register

        AT91_REG         DBGU_RNCR;     // Receive Next Counter Register

        AT91_REG         DBGU_TNPR;     // Transmit Next Pointer Register

        AT91_REG         DBGU_TNCR;     // Transmit Next Counter Register

        AT91_REG         DBGU_PTCR;     // PDC Transfer Control Register

        AT91_REG         DBGU_PTSR;     // PDC Transfer Status Register

} AT91S_DBGU, *AT91PS_DBGU;

// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 

#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver

#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter

#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable

#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable

#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable

#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable

#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits

// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 

#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type

#define         AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity

#define         AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity

#define         AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)

#define         AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)

#define         AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity

#define         AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode

#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode

#define         AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.

#define         AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.

#define         AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.

#define         AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.

// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 

#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt

#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt

#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt

#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt

#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt

#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt

#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt

#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt

#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt

#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt

#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt

#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt

// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 

// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 

// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 

// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 

#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler

// *****************************************************************************

typedef struct _AT91S_PIO {

        AT91_REG         PIO_PER;       // PIO Enable Register

        AT91_REG         PIO_PDR;       // PIO Disable Register

        AT91_REG         PIO_PSR;       // PIO Status Register

        AT91_REG         Reserved0[1];  // 

        AT91_REG         PIO_OER;       // Output Enable Register

        AT91_REG         PIO_ODR;       // Output Disable Registerr

        AT91_REG         PIO_OSR;       // Output Status Register

        AT91_REG         Reserved1[1];  // 

        AT91_REG         PIO_IFER;      // Input Filter Enable Register

        AT91_REG         PIO_IFDR;      // Input Filter Disable Register

        AT91_REG         PIO_IFSR;      // Input Filter Status Register

        AT91_REG         Reserved2[1];  // 

        AT91_REG         PIO_SODR;      // Set Output Data Register

        AT91_REG         PIO_CODR;      // Clear Output Data Register

        AT91_REG         PIO_ODSR;      // Output Data Status Register

        AT91_REG         PIO_PDSR;      // Pin Data Status Register

        AT91_REG         PIO_IER;       // Interrupt Enable Register

        AT91_REG         PIO_IDR;       // Interrupt Disable Register

        AT91_REG         PIO_IMR;       // Interrupt Mask Register

        AT91_REG         PIO_ISR;       // Interrupt Status Register

        AT91_REG         PIO_MDER;      // Multi-driver Enable Register

        AT91_REG         PIO_MDDR;      // Multi-driver Disable Register

        AT91_REG         PIO_MDSR;      // Multi-driver Status Register

        AT91_REG         Reserved3[1];  // 

        AT91_REG         PIO_PPUDR;     // Pull-up Disable Register

        AT91_REG         PIO_PPUER;     // Pull-up Enable Register

        AT91_REG         PIO_PPUSR;     // Pull-up Status Register

        AT91_REG         Reserved4[1];  // 

        AT91_REG         PIO_ASR;       // Select A Register

        AT91_REG         PIO_BSR;       // Select B Register

        AT91_REG         PIO_ABSR;      // AB Select Status Register

        AT91_REG         Reserved5[9];  // 

        AT91_REG         PIO_OWER;      // Output Write Enable Register

        AT91_REG         PIO_OWDR;      // Output Write Disable Register

        AT91_REG         PIO_OWSR;      // Output Write Status Register

} AT91S_PIO, *AT91PS_PIO;

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Clock Generator Controler

// *****************************************************************************

typedef struct _AT91S_CKGR {

        AT91_REG         CKGR_MOR;      // Main Oscillator Register

        AT91_REG         CKGR_MCFR;     // Main Clock  Frequency Register

        AT91_REG         Reserved0[1];  // 

        AT91_REG         CKGR_PLLR;     // PLL Register

} AT91S_CKGR, *AT91PS_CKGR;

// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 

#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable

#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass

#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time

// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 

#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency

#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready

// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 

#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected

#define         AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0

#define         AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed

#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter

#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range

#define         AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet

#define         AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet

#define         AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet

#define         AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet

#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier

#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks

#define         AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output

#define         AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2

#define         AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Power Management Controler

// *****************************************************************************

typedef struct _AT91S_PMC {

        AT91_REG         PMC_SCER;      // System Clock Enable Register

        AT91_REG         PMC_SCDR;      // System Clock Disable Register

        AT91_REG         PMC_SCSR;      // System Clock Status Register

        AT91_REG         Reserved0[1];  // 

        AT91_REG         PMC_PCER;      // Peripheral Clock Enable Register

        AT91_REG         PMC_PCDR;      // Peripheral Clock Disable Register

        AT91_REG         PMC_PCSR;      // Peripheral Clock Status Register

        AT91_REG         Reserved1[1];  // 

        AT91_REG         PMC_MOR;       // Main Oscillator Register

        AT91_REG         PMC_MCFR;      // Main Clock  Frequency Register

        AT91_REG         Reserved2[1];  // 

        AT91_REG         PMC_PLLR;      // PLL Register

        AT91_REG         PMC_MCKR;      // Master Clock Register

        AT91_REG         Reserved3[3];  // 

        AT91_REG         PMC_PCKR[4];   // Programmable Clock Register

        AT91_REG         Reserved4[4];  // 

        AT91_REG         PMC_IER;       // Interrupt Enable Register

        AT91_REG         PMC_IDR;       // Interrupt Disable Register

        AT91_REG         PMC_SR;        // Status Register

        AT91_REG         PMC_IMR;       // Interrupt Mask Register

} AT91S_PMC, *AT91PS_PMC;

// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 

#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock

#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock

#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output

#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output

#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output

#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output

// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 

// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 

// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 

// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 

// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 

// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 

#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection

#define         AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected

#define         AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected

#define         AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected

#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler

#define         AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock

#define         AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2

#define         AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4

#define         AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8

#define         AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16

#define         AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32

#define         AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64

// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 

// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 

#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask

#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask

#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask

// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 

// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 

// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Reset Controller Interface

// *****************************************************************************

typedef struct _AT91S_RSTC {

        AT91_REG         RSTC_RCR;      // Reset Control Register

        AT91_REG         RSTC_RSR;      // Reset Status Register

        AT91_REG         RSTC_RMR;      // Reset Mode Register

} AT91S_RSTC, *AT91PS_RSTC;

// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 

#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset

#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset

#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset

#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password

// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 

#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status

#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status

#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type

#define         AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.

#define         AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.

#define         AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.

#define         AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.

#define         AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.

#define         AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.

#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level

#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.

// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 

#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable

#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable

#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable

#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface

// *****************************************************************************

typedef struct _AT91S_RTTC {

        AT91_REG         RTTC_RTMR;     // Real-time Mode Register

        AT91_REG         RTTC_RTAR;     // Real-time Alarm Register

        AT91_REG         RTTC_RTVR;     // Real-time Value Register

        AT91_REG         RTTC_RTSR;     // Real-time Status Register

} AT91S_RTTC, *AT91PS_RTTC;

// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 

#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value

#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable

#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable

#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart

// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 

#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value

// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 

#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value

// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 

#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status

#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface

// *****************************************************************************

typedef struct _AT91S_PITC {

        AT91_REG         PITC_PIMR;     // Period Interval Mode Register

        AT91_REG         PITC_PISR;     // Period Interval Status Register

        AT91_REG         PITC_PIVR;     // Period Interval Value Register

        AT91_REG         PITC_PIIR;     // Period Interval Image Register

} AT91S_PITC, *AT91PS_PITC;

// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 

#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value

#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled

#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable

// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 

#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status

// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 

#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value

#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter

// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface

// *****************************************************************************

typedef struct _AT91S_WDTC {

        AT91_REG         WDTC_WDCR;     // Watchdog Control Register

        AT91_REG         WDTC_WDMR;     // Watchdog Mode Register

        AT91_REG         WDTC_WDSR;     // Watchdog Status Register

} AT91S_WDTC, *AT91PS_WDTC;

// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 

#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart

#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password

// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 

#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart

#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable

#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable

#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart

#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable

#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value

#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt

#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt

// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 

#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow

#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface

// *****************************************************************************

typedef struct _AT91S_VREG {

        AT91_REG         VREG_MR;       // Voltage Regulator Mode Register

} AT91S_VREG, *AT91PS_VREG;

// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 

#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Memory Controller Interface

// *****************************************************************************

typedef struct _AT91S_MC {

        AT91_REG         MC_RCR;        // MC Remap Control Register

        AT91_REG         MC_ASR;        // MC Abort Status Register

        AT91_REG         MC_AASR;       // MC Abort Address Status Register

        AT91_REG         Reserved0[21];         // 

        AT91_REG         MC_FMR;        // MC Flash Mode Register

        AT91_REG         MC_FCR;        // MC Flash Command Register

        AT91_REG         MC_FSR;        // MC Flash Status Register

} AT91S_MC, *AT91PS_MC;

// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 

#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit

// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 

#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status

#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status

#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status

#define         AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte

#define         AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word

#define         AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word

#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status

#define         AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read

#define         AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write

#define         AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch

#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source

#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source

#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source

#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source

// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 

#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready

#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error

#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error

#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming

#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State

#define         AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations

#define         AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations

#define         AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations

#define         AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations

#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number

// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 

#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command

#define         AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.

#define         AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.

#define         AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.

#define         AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.

#define         AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.

#define         AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.

#define         AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.

#define         AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.

#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number

#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key

// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 

#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status

#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status

#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status

#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status

#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status

#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status

#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status

#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status

#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status

#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status

#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status

#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status

#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status

#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status

#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status

#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status

#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status

#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status

#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status

#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status

#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status

#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status

#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status

#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status

#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface

// *****************************************************************************

typedef struct _AT91S_SPI {

        AT91_REG         SPI_CR;        // Control Register

        AT91_REG         SPI_MR;        // Mode Register

        AT91_REG         SPI_RDR;       // Receive Data Register

        AT91_REG         SPI_TDR;       // Transmit Data Register

        AT91_REG         SPI_SR;        // Status Register

        AT91_REG         SPI_IER;       // Interrupt Enable Register

        AT91_REG         SPI_IDR;       // Interrupt Disable Register

        AT91_REG         SPI_IMR;       // Interrupt Mask Register

        AT91_REG         Reserved0[4];  // 

        AT91_REG         SPI_CSR[4];    // Chip Select Register

        AT91_REG         Reserved1[48];         // 

        AT91_REG         SPI_RPR;       // Receive Pointer Register

        AT91_REG         SPI_RCR;       // Receive Counter Register

        AT91_REG         SPI_TPR;       // Transmit Pointer Register

        AT91_REG         SPI_TCR;       // Transmit Counter Register

        AT91_REG         SPI_RNPR;      // Receive Next Pointer Register

        AT91_REG         SPI_RNCR;      // Receive Next Counter Register

        AT91_REG         SPI_TNPR;      // Transmit Next Pointer Register

        AT91_REG         SPI_TNCR;      // Transmit Next Counter Register

        AT91_REG         SPI_PTCR;      // PDC Transfer Control Register

        AT91_REG         SPI_PTSR;      // PDC Transfer Status Register

} AT91S_SPI, *AT91PS_SPI;

// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 

#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable

#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable

#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset

#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer

// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 

#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode

#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select

#define         AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select

#define         AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select

#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode

#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection

#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection

#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection

#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select

#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects

// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 

#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data

#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status

// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 

#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data

#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status

// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 

#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full

#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty

#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error

#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status

#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer

#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer

#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt

#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt

#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt

#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt

#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status

// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 

// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 

// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 

// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 

#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity

#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase

#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer

#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer

#define         AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer

#define         AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer

#define         AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer

#define         AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer

#define         AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer

#define         AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer

#define         AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer

#define         AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer