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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Source/] [portable/] [GCC/] [ARM7_AT91SAM7S/] [portISR.c] - Blame information for rev 857

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1 572 jeremybenn
/*
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    FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
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    ***************************************************************************
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    *                                                                         *
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    * If you are:                                                             *
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    *                                                                         *
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    *    + New to FreeRTOS,                                                   *
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    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *
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    *    + Looking for basic training,                                        *
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    *    + Wanting to improve your FreeRTOS skills and productivity           *
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    *                                                                         *
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    * then take a look at the FreeRTOS books - available as PDF or paperback  *
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    *                                                                         *
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    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *
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    *                  http://www.FreeRTOS.org/Documentation                  *
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    *                                                                         *
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    * A pdf reference manual is also available.  Both are usually delivered   *
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    * to your inbox within 20 minutes to two hours when purchased between 8am *
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    * and 8pm GMT (although please allow up to 24 hours in case of            *
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    * exceptional circumstances).  Thank you for your support!                *
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    *                                                                         *
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    ***************************************************************************
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    This file is part of the FreeRTOS distribution.
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    FreeRTOS is free software; you can redistribute it and/or modify it under
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    the terms of the GNU General Public License (version 2) as published by the
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    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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    ***NOTE*** The exception to the GPL is included to allow you to distribute
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    a combined work that includes FreeRTOS without being obliged to provide the
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    source code for proprietary components outside of the FreeRTOS kernel.
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    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
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    more details. You should have received a copy of the GNU General Public
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    License and the FreeRTOS license exception along with FreeRTOS; if not it
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    can be viewed here: http://www.freertos.org/a00114.html and also obtained
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    by writing to Richard Barry, contact details for whom are available on the
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    FreeRTOS WEB site.
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    1 tab == 4 spaces!
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    http://www.FreeRTOS.org - Documentation, latest information, license and
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    contact details.
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    http://www.SafeRTOS.com - A version that is certified for use in safety
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    critical systems.
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    http://www.OpenRTOS.com - Commercial support, development, porting,
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    licensing and training services.
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*/
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/*-----------------------------------------------------------
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 * Components that can be compiled to either ARM or THUMB mode are
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 * contained in port.c  The ISR routines, which can only be compiled
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 * to ARM mode, are contained in this file.
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 *----------------------------------------------------------*/
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/*
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        Changes from V3.2.4
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        + The assembler statements are now included in a single asm block rather
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          than each line having its own asm block.
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*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#include "AT91SAM7X256.h"
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/* Constants required to handle interrupts. */
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#define portTIMER_MATCH_ISR_BIT         ( ( unsigned char ) 0x01 )
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#define portCLEAR_VIC_INTERRUPT         ( ( unsigned long ) 0 )
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/* Constants required to handle critical sections. */
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#define portNO_CRITICAL_NESTING         ( ( unsigned long ) 0 )
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volatile unsigned long ulCriticalNesting = 9999UL;
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/*-----------------------------------------------------------*/
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/* ISR to handle manual context switches (from a call to taskYIELD()). */
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void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
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/*
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 * The scheduler can only be started from ARM mode, hence the inclusion of this
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 * function here.
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 */
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void vPortISRStartFirstTask( void );
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/*-----------------------------------------------------------*/
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void vPortISRStartFirstTask( void )
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{
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        /* Simply start the scheduler.  This is included here as it can only be
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        called from ARM mode. */
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        portRESTORE_CONTEXT();
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}
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/*-----------------------------------------------------------*/
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/*
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 * Called by portYIELD() or taskYIELD() to manually force a context switch.
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 *
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 * When a context switch is performed from the task level the saved task
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 * context is made to look as if it occurred from within the tick ISR.  This
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 * way the same restore context function can be used when restoring the context
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 * saved from the ISR or that saved from a call to vPortYieldProcessor.
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 */
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void vPortYieldProcessor( void )
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{
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        /* Within an IRQ ISR the link register has an offset from the true return
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        address, but an SWI ISR does not.  Add the offset manually so the same
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        ISR return code can be used in both cases. */
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        asm volatile ( "ADD             LR, LR, #4" );
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        /* Perform the context switch.  First save the context of the current task. */
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        portSAVE_CONTEXT();
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        /* Find the highest priority task that is ready to run. */
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        vTaskSwitchContext();
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        /* Restore the context of the new task. */
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        portRESTORE_CONTEXT();
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}
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/*-----------------------------------------------------------*/
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/*
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 * The ISR used for the scheduler tick depends on whether the cooperative or
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 * the preemptive scheduler is being used.
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 */
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#if configUSE_PREEMPTION == 0
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        /* The cooperative scheduler requires a normal IRQ service routine to
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        simply increment the system tick. */
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        void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
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        void vNonPreemptiveTick( void )
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        {
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                unsigned long ulDummy;
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                /* Increment the tick count - which may wake some tasks but as the
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                preemptive scheduler is not being used any woken task is not given
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                processor time no matter what its priority. */
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                vTaskIncrementTick();
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                /* Clear the PIT interrupt. */
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                ulDummy = AT91C_BASE_PITC->PITC_PIVR;
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                /* End the interrupt in the AIC. */
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                AT91C_BASE_AIC->AIC_EOICR = ulDummy;
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        }
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#else
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        /* The preemptive scheduler is defined as "naked" as the full context is
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        saved on entry as part of the context switch. */
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        void vPreemptiveTick( void ) __attribute__((naked));
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        void vPreemptiveTick( void )
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        {
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                /* Save the context of the current task. */
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                portSAVE_CONTEXT();
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                /* Increment the tick count - this may wake a task. */
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                vTaskIncrementTick();
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                /* Find the highest priority task that is ready to run. */
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                vTaskSwitchContext();
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                /* End the interrupt in the AIC. */
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                AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;;
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                portRESTORE_CONTEXT();
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        }
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#endif
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/*-----------------------------------------------------------*/
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/*
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 * The interrupt management utilities can only be called from ARM mode.  When
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 * THUMB_INTERWORK is defined the utilities are defined as functions here to
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 * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
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 * the utilities are defined as macros in portmacro.h - as per other ports.
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 */
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void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
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void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
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void vPortDisableInterruptsFromThumb( void )
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{
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        asm volatile (
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                "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */
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                "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */
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                "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                                            */
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                "MSR    CPSR, R0                \n\t"   /* Write back modified value.                           */
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                "LDMIA  SP!, {R0}               \n\t"   /* Pop R0.                                                                      */
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                "BX             R14" );                                 /* Return back to thumb.                                        */
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}
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void vPortEnableInterruptsFromThumb( void )
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{
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        asm volatile (
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                "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */
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                "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */
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                "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                                                     */
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                "MSR    CPSR, R0                \n\t"   /* Write back modified value.                           */
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                "LDMIA  SP!, {R0}               \n\t"   /* Pop R0.                                                                      */
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                "BX             R14" );                                 /* Return back to thumb.                                        */
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}
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/* The code generated by the GCC compiler uses the stack in different ways at
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different optimisation levels.  The interrupt flags can therefore not always
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be saved to the stack.  Instead the critical section nesting level is stored
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in a variable, which is then saved as part of the stack context. */
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void vPortEnterCritical( void )
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{
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        /* Disable interrupts as per portDISABLE_INTERRUPTS();                                                  */
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        asm volatile (
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                "STMDB  SP!, {R0}                       \n\t"   /* Push R0.                                                             */
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                "MRS    R0, CPSR                        \n\t"   /* Get CPSR.                                                    */
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                "ORR    R0, R0, #0xC0           \n\t"   /* Disable IRQ, FIQ.                                    */
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                "MSR    CPSR, R0                        \n\t"   /* Write back modified value.                   */
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                "LDMIA  SP!, {R0}" );                           /* Pop R0.                                                              */
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        /* Now interrupts are disabled ulCriticalNesting can be accessed
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        directly.  Increment ulCriticalNesting to keep a count of how many times
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        portENTER_CRITICAL() has been called. */
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        ulCriticalNesting++;
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}
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void vPortExitCritical( void )
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{
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        if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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        {
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                /* Decrement the nesting count as we are leaving a critical section. */
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                ulCriticalNesting--;
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                /* If the nesting level has reached zero then interrupts should be
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                re-enabled. */
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                if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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                {
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                        /* Enable interrupts as per portEXIT_CRITICAL().                                        */
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                        asm volatile (
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                                "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */
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                                "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */
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                                "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                             */
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                                "MSR    CPSR, R0                \n\t"   /* Write back modified value.   */
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                                "LDMIA  SP!, {R0}" );                   /* Pop R0.                                              */
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                }
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        }
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}
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