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jeremybenn |
/*
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FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
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***************************************************************************
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* *
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* If you are: *
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* *
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* + New to FreeRTOS, *
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* + Wanting to learn FreeRTOS or multitasking in general quickly *
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* + Looking for basic training, *
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* + Wanting to improve your FreeRTOS skills and productivity *
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* *
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* then take a look at the FreeRTOS books - available as PDF or paperback *
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* *
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* "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
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* http://www.FreeRTOS.org/Documentation *
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* *
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* A pdf reference manual is also available. Both are usually delivered *
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* to your inbox within 20 minutes to two hours when purchased between 8am *
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* and 8pm GMT (although please allow up to 24 hours in case of *
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* exceptional circumstances). Thank you for your support! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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***NOTE*** The exception to the GPL is included to allow you to distribute
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a combined work that includes FreeRTOS without being obliged to provide the
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source code for proprietary components outside of the FreeRTOS kernel.
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FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details. You should have received a copy of the GNU General Public
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License and the FreeRTOS license exception along with FreeRTOS; if not it
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can be viewed here: http://www.freertos.org/a00114.html and also obtained
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by writing to Richard Barry, contact details for whom are available on the
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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http://www.FreeRTOS.org - Documentation, latest information, license and
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contact details.
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http://www.SafeRTOS.com - A version that is certified for use in safety
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critical systems.
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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*/
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#ifndef PORTMACRO_H
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#define PORTMACRO_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*-----------------------------------------------------------
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* Port specific definitions.
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*
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* The settings in this file configure FreeRTOS correctly for the
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* given hardware and compiler.
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*
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* These settings should not be altered.
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*-----------------------------------------------------------
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*/
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/* Type definitions. */
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#define portCHAR char
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#define portFLOAT float
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#define portDOUBLE double
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#define portLONG long
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#define portSHORT short
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#define portSTACK_TYPE unsigned portLONG
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#define portBASE_TYPE portLONG
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#if( configUSE_16_BIT_TICKS == 1 )
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typedef unsigned portSHORT portTickType;
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#define portMAX_DELAY ( portTickType ) 0xffff
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#else
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typedef unsigned portLONG portTickType;
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#define portMAX_DELAY ( portTickType ) 0xffffffff
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#endif
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/*-----------------------------------------------------------*/
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/* Architecture specifics. */
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#define portSTACK_GROWTH ( -1 )
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#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
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#define portBYTE_ALIGNMENT 8
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#define portNOP() __asm volatile ( "NOP" );
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/*-----------------------------------------------------------*/
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/* Scheduler utilities. */
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/*
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* portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
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* and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
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* are included here for efficiency. An attempt to call one from
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* THUMB mode code will result in a compile time error.
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*/
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#define portRESTORE_CONTEXT() \
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{ \
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extern volatile void * volatile pxCurrentTCB; \
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extern volatile unsigned portLONG ulCriticalNesting; \
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\
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/* Set the LR to the task stack. */ \
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__asm volatile ( \
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"LDR R0, =pxCurrentTCB \n\t" \
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"LDR R0, [R0] \n\t" \
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"LDR LR, [R0] \n\t" \
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\
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/* The critical nesting depth is the first item on the stack. */ \
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/* Load it into the ulCriticalNesting variable. */ \
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"LDR R0, =ulCriticalNesting \n\t" \
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"LDMFD LR!, {R1} \n\t" \
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"STR R1, [R0] \n\t" \
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\
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/* Get the SPSR from the stack. */ \
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"LDMFD LR!, {R0} \n\t" \
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"MSR SPSR, R0 \n\t" \
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\
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/* Restore all system mode registers for the task. */ \
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"LDMFD LR, {R0-R14}^ \n\t" \
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"NOP \n\t" \
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\
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/* Restore the return address. */ \
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"LDR LR, [LR, #+60] \n\t" \
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\
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/* And return - correcting the offset in the LR to obtain the */ \
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/* correct address. */ \
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"SUBS PC, LR, #4 \n\t" \
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); \
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( void ) ulCriticalNesting; \
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( void ) pxCurrentTCB; \
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}
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/*-----------------------------------------------------------*/
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#define portSAVE_CONTEXT() \
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{ \
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extern volatile void * volatile pxCurrentTCB; \
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extern volatile unsigned portLONG ulCriticalNesting; \
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\
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/* Push R0 as we are going to use the register. */ \
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__asm volatile ( \
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"STMDB SP!, {R0} \n\t" \
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\
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/* Set R0 to point to the task stack pointer. */ \
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"STMDB SP,{SP}^ \n\t" \
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"NOP \n\t" \
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"SUB SP, SP, #4 \n\t" \
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"LDMIA SP!,{R0} \n\t" \
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\
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/* Push the return address onto the stack. */ \
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"STMDB R0!, {LR} \n\t" \
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\
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/* Now we have saved LR we can use it instead of R0. */ \
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"MOV LR, R0 \n\t" \
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\
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/* Pop R0 so we can save it onto the system mode stack. */ \
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"LDMIA SP!, {R0} \n\t" \
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\
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/* Push all the system mode registers onto the task stack. */ \
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"STMDB LR,{R0-LR}^ \n\t" \
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"NOP \n\t" \
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"SUB LR, LR, #60 \n\t" \
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\
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/* Push the SPSR onto the task stack. */ \
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"MRS R0, SPSR \n\t" \
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"STMDB LR!, {R0} \n\t" \
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\
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"LDR R0, =ulCriticalNesting \n\t" \
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"LDR R0, [R0] \n\t" \
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"STMDB LR!, {R0} \n\t" \
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\
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/* Store the new top of stack for the task. */ \
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"LDR R0, =pxCurrentTCB \n\t" \
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"LDR R0, [R0] \n\t" \
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"STR LR, [R0] \n\t" \
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); \
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( void ) ulCriticalNesting; \
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( void ) pxCurrentTCB; \
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}
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extern void vTaskSwitchContext( void );
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#define portYIELD_FROM_ISR() vTaskSwitchContext()
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#define portYIELD() __asm volatile ( "SWI 0" )
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/*-----------------------------------------------------------*/
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/* Critical section management. */
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/*
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* The interrupt management utilities can only be called from ARM mode. When
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* THUMB_INTERWORK is defined the utilities are defined as functions in
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* portISR.c to ensure a switch to ARM mode. When THUMB_INTERWORK is not
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* defined then the utilities are defined as macros here - as per other ports.
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*/
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#ifdef THUMB_INTERWORK
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extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
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extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
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#define portDISABLE_INTERRUPTS() vPortDisableInterruptsFromThumb()
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#define portENABLE_INTERRUPTS() vPortEnableInterruptsFromThumb()
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#else
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#define portDISABLE_INTERRUPTS() \
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__asm volatile ( \
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"STMDB SP!, {R0} \n\t" /* Push R0. */ \
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"MRS R0, CPSR \n\t" /* Get CPSR. */ \
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"ORR R0, R0, #0xC0 \n\t" /* Disable IRQ, FIQ. */ \
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"MSR CPSR, R0 \n\t" /* Write back modified value. */ \
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"LDMIA SP!, {R0} " ) /* Pop R0. */
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#define portENABLE_INTERRUPTS() \
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__asm volatile ( \
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"STMDB SP!, {R0} \n\t" /* Push R0. */ \
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"MRS R0, CPSR \n\t" /* Get CPSR. */ \
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"BIC R0, R0, #0xC0 \n\t" /* Enable IRQ, FIQ. */ \
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"MSR CPSR, R0 \n\t" /* Write back modified value. */ \
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"LDMIA SP!, {R0} " ) /* Pop R0. */
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#endif /* THUMB_INTERWORK */
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extern void vPortEnterCritical( void );
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extern void vPortExitCritical( void );
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#define portENTER_CRITICAL() vPortEnterCritical();
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#define portEXIT_CRITICAL() vPortExitCritical();
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/*-----------------------------------------------------------*/
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/* Task function macros as described on the FreeRTOS.org WEB site. */
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#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
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#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
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#ifdef __cplusplus
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}
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#endif
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#endif /* PORTMACRO_H */
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