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572 |
jeremybenn |
/*This file has been prepared for Doxygen automatic documentation generation.*/
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/*! \file *********************************************************************
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*
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* \brief FreeRTOS port source for AVR32 UC3.
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*
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* - Compiler: GNU GCC for AVR32
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* - Supported devices: All AVR32 devices can be used.
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* - AppNote:
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*
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* \author Atmel Corporation: http://www.atmel.com \n
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* Support and FAQ: http://support.atmel.no/
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*
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*****************************************************************************/
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/*
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FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
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***************************************************************************
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* *
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* If you are: *
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* *
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* + New to FreeRTOS, *
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* + Wanting to learn FreeRTOS or multitasking in general quickly *
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* + Looking for basic training, *
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* + Wanting to improve your FreeRTOS skills and productivity *
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* *
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* then take a look at the FreeRTOS books - available as PDF or paperback *
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* *
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* "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
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* http://www.FreeRTOS.org/Documentation *
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* *
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* A pdf reference manual is also available. Both are usually delivered *
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* to your inbox within 20 minutes to two hours when purchased between 8am *
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* and 8pm GMT (although please allow up to 24 hours in case of *
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* exceptional circumstances). Thank you for your support! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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***NOTE*** The exception to the GPL is included to allow you to distribute
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a combined work that includes FreeRTOS without being obliged to provide the
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source code for proprietary components outside of the FreeRTOS kernel.
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FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details. You should have received a copy of the GNU General Public
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License and the FreeRTOS license exception along with FreeRTOS; if not it
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can be viewed here: http://www.freertos.org/a00114.html and also obtained
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by writing to Richard Barry, contact details for whom are available on the
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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http://www.FreeRTOS.org - Documentation, latest information, license and
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contact details.
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http://www.SafeRTOS.com - A version that is certified for use in safety
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critical systems.
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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*/
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#ifndef PORTMACRO_H
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#define PORTMACRO_H
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/*-----------------------------------------------------------
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* Port specific definitions.
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*
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* The settings in this file configure FreeRTOS correctly for the
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* given hardware and compiler.
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*
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* These settings should not be altered.
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*-----------------------------------------------------------
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*/
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#include <avr32/io.h>
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#include "intc.h"
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#include "compiler.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Type definitions. */
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#define portCHAR char
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#define portFLOAT float
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#define portDOUBLE double
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#define portLONG long
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#define portSHORT short
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#define portSTACK_TYPE unsigned portLONG
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#define portBASE_TYPE portLONG
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#define TASK_DELAY_MS(x) ( (x) /portTICK_RATE_MS )
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#define TASK_DELAY_S(x) ( (x)*1000 /portTICK_RATE_MS )
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#define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_RATE_MS )
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#define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
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#if( configUSE_16_BIT_TICKS == 1 )
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typedef unsigned portSHORT portTickType;
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#define portMAX_DELAY ( portTickType ) 0xffff
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#else
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typedef unsigned portLONG portTickType;
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#define portMAX_DELAY ( portTickType ) 0xffffffff
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#endif
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/*-----------------------------------------------------------*/
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/* Architecture specifics. */
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#define portSTACK_GROWTH ( -1 )
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#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
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#define portBYTE_ALIGNMENT 4
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#define portNOP() {__asm__ __volatile__ ("nop");}
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/*-----------------------------------------------------------*/
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/*-----------------------------------------------------------*/
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/* INTC-specific. */
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#define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
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#define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
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#define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
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#define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
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#define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev)
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#define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev)
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/*
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* Debug trace.
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* Activated if and only if configDBG is nonzero.
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* Prints a formatted string to stdout.
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* The current source file name and line number are output with a colon before
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* the formatted string.
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* A carriage return and a linefeed are appended to the output.
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* stdout is redirected to the USART configured by configDBG_USART.
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* The parameters are the same as for the standard printf function.
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* There is no return value.
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* SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
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* which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
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*/
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#if configDBG
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#define portDBG_TRACE(...) \
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{\
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fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\
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printf(__VA_ARGS__);\
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fputs("\r\n", stdout);\
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}
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#else
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#define portDBG_TRACE(...)
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#endif
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/* Critical section management. */
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#define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
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#define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
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extern void vPortEnterCritical( void );
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extern void vPortExitCritical( void );
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#define portENTER_CRITICAL() vPortEnterCritical();
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#define portEXIT_CRITICAL() vPortExitCritical();
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/* Added as there is no such function in FreeRTOS. */
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extern void *pvPortRealloc( void *pv, size_t xSize );
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/*-----------------------------------------------------------*/
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/*=============================================================================================*/
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/*
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* Restore Context for cases other than INTi.
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*/
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#define portRESTORE_CONTEXT() \
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{ \
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extern volatile unsigned portLONG ulCriticalNesting; \
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extern volatile void *volatile pxCurrentTCB; \
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\
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__asm__ __volatile__ ( \
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/* Set SP to point to new stack */ \
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"mov r8, LO(%[pxCurrentTCB]) \n\t"\
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"orh r8, HI(%[pxCurrentTCB]) \n\t"\
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"ld.w r0, r8[0] \n\t"\
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"ld.w sp, r0[0] \n\t"\
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\
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/* Restore ulCriticalNesting variable */ \
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"ld.w r0, sp++ \n\t"\
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"mov r8, LO(%[ulCriticalNesting]) \n\t"\
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"orh r8, HI(%[ulCriticalNesting]) \n\t"\
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"st.w r8[0], r0 \n\t"\
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\
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/* Restore R0..R7 */ \
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"ldm sp++, r0-r7 \n\t"\
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/* R0-R7 should not be used below this line */ \
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/* Skip PC and SR (will do it at the end) */ \
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"sub sp, -2*4 \n\t"\
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/* Restore R8..R12 and LR */ \
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"ldm sp++, r8-r12, lr \n\t"\
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/* Restore SR */ \
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"ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */ \
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"mtsr %[SR], r0 \n\t"\
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/* Restore r0 */ \
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"ld.w r0, sp[-9*4] \n\t"\
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/* Restore PC */ \
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"ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
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: \
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: [ulCriticalNesting] "i" (&ulCriticalNesting), \
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[pxCurrentTCB] "i" (&pxCurrentTCB), \
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[SR] "i" (AVR32_SR) \
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); \
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}
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| 222 |
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/*
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* portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
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* portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
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*
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| 226 |
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* Had to make different versions because registers saved on the system stack
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* are not the same between INT0..3 exceptions and the scall exception.
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*/
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// Task context stack layout:
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// R8 (*)
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// R9 (*)
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// R10 (*)
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// R11 (*)
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// R12 (*)
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// R14/LR (*)
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// R15/PC (*)
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// SR (*)
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// R0
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// R1
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// R2
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// R3
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| 243 |
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// R4
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// R5
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// R6
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| 246 |
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// R7
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| 247 |
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// ulCriticalNesting
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// (*) automatically done for INT0..INT3, but not for SCALL
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/*
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| 251 |
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* The ISR used for the scheduler tick depends on whether the cooperative or
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| 252 |
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* the preemptive scheduler is being used.
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| 253 |
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*/
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| 254 |
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#if configUSE_PREEMPTION == 0
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| 255 |
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| 256 |
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/*
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| 257 |
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* portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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| 258 |
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*/
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| 259 |
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#define portSAVE_CONTEXT_OS_INT() \
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| 260 |
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{ \
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| 261 |
|
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/* Save R0..R7 */ \
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| 262 |
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__asm__ __volatile__ ("stm --sp, r0-r7"); \
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| 263 |
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\
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| 264 |
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/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
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| 265 |
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/* there is also no context save. */ \
|
| 266 |
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}
|
| 267 |
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| 268 |
|
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/*
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| 269 |
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* portRESTORE_CONTEXT_OS_INT() for Tick exception.
|
| 270 |
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*/
|
| 271 |
|
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#define portRESTORE_CONTEXT_OS_INT() \
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| 272 |
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{ \
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| 273 |
|
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__asm__ __volatile__ ( \
|
| 274 |
|
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/* Restore R0..R7 */ \
|
| 275 |
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"ldm sp++, r0-r7\n\t" \
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| 276 |
|
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\
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| 277 |
|
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/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
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| 278 |
|
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/* there is also no context restore. */ \
|
| 279 |
|
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"rete" \
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| 280 |
|
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); \
|
| 281 |
|
|
}
|
| 282 |
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|
| 283 |
|
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#else
|
| 284 |
|
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|
| 285 |
|
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/*
|
| 286 |
|
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* portSAVE_CONTEXT_OS_INT() for OS Tick exception.
|
| 287 |
|
|
*/
|
| 288 |
|
|
#define portSAVE_CONTEXT_OS_INT() \
|
| 289 |
|
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{ \
|
| 290 |
|
|
extern volatile unsigned portLONG ulCriticalNesting; \
|
| 291 |
|
|
extern volatile void *volatile pxCurrentTCB; \
|
| 292 |
|
|
\
|
| 293 |
|
|
/* When we come here */ \
|
| 294 |
|
|
/* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
|
| 295 |
|
|
\
|
| 296 |
|
|
__asm__ __volatile__ ( \
|
| 297 |
|
|
/* Save R0..R7 */ \
|
| 298 |
|
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"stm --sp, r0-r7 \n\t"\
|
| 299 |
|
|
\
|
| 300 |
|
|
/* Save ulCriticalNesting variable - R0 is overwritten */ \
|
| 301 |
|
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"mov r8, LO(%[ulCriticalNesting])\n\t" \
|
| 302 |
|
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"orh r8, HI(%[ulCriticalNesting])\n\t" \
|
| 303 |
|
|
"ld.w r0, r8[0] \n\t"\
|
| 304 |
|
|
"st.w --sp, r0 \n\t"\
|
| 305 |
|
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\
|
| 306 |
|
|
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
|
| 307 |
|
|
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
|
| 308 |
|
|
/* level and allow other lower interrupt level to occur). */ \
|
| 309 |
|
|
/* In this case we don't want to do a task switch because we don't know what the stack */ \
|
| 310 |
|
|
/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
|
| 311 |
|
|
/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
|
| 312 |
|
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/* will just be restoring the interrupt handler, no way!!! */ \
|
| 313 |
|
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/* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
|
| 314 |
|
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"ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
|
| 315 |
|
|
"bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
|
| 316 |
|
|
"cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
|
| 317 |
|
|
"brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
|
| 318 |
|
|
\
|
| 319 |
|
|
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
|
| 320 |
|
|
/* NOTE: we don't enter a critical section here because all interrupt handlers */ \
|
| 321 |
|
|
/* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
|
| 322 |
|
|
/* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
|
| 323 |
|
|
/* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
|
| 324 |
|
|
"mov r8, LO(%[pxCurrentTCB])\n\t" \
|
| 325 |
|
|
"orh r8, HI(%[pxCurrentTCB])\n\t" \
|
| 326 |
|
|
"ld.w r0, r8[0]\n\t" \
|
| 327 |
|
|
"st.w r0[0], sp\n" \
|
| 328 |
|
|
\
|
| 329 |
|
|
"LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \
|
| 330 |
|
|
: \
|
| 331 |
|
|
: [ulCriticalNesting] "i" (&ulCriticalNesting), \
|
| 332 |
|
|
[pxCurrentTCB] "i" (&pxCurrentTCB), \
|
| 333 |
|
|
[LINE] "i" (__LINE__) \
|
| 334 |
|
|
); \
|
| 335 |
|
|
}
|
| 336 |
|
|
|
| 337 |
|
|
/*
|
| 338 |
|
|
* portRESTORE_CONTEXT_OS_INT() for Tick exception.
|
| 339 |
|
|
*/
|
| 340 |
|
|
#define portRESTORE_CONTEXT_OS_INT() \
|
| 341 |
|
|
{ \
|
| 342 |
|
|
extern volatile unsigned portLONG ulCriticalNesting; \
|
| 343 |
|
|
extern volatile void *volatile pxCurrentTCB; \
|
| 344 |
|
|
\
|
| 345 |
|
|
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
|
| 346 |
|
|
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
|
| 347 |
|
|
/* level and allow other lower interrupt level to occur). */ \
|
| 348 |
|
|
/* In this case we don't want to do a task switch because we don't know what the stack */ \
|
| 349 |
|
|
/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
|
| 350 |
|
|
/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
|
| 351 |
|
|
/* will just be restoring the interrupt handler, no way!!! */ \
|
| 352 |
|
|
__asm__ __volatile__ ( \
|
| 353 |
|
|
"ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
|
| 354 |
|
|
"bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
|
| 355 |
|
|
"cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
|
| 356 |
|
|
"brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \
|
| 357 |
|
|
: \
|
| 358 |
|
|
: [LINE] "i" (__LINE__) \
|
| 359 |
|
|
); \
|
| 360 |
|
|
\
|
| 361 |
|
|
/* Else */ \
|
| 362 |
|
|
/* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
|
| 363 |
|
|
/* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
|
| 364 |
|
|
portENTER_CRITICAL(); \
|
| 365 |
|
|
vTaskSwitchContext(); \
|
| 366 |
|
|
portEXIT_CRITICAL(); \
|
| 367 |
|
|
\
|
| 368 |
|
|
/* Restore all registers */ \
|
| 369 |
|
|
\
|
| 370 |
|
|
__asm__ __volatile__ ( \
|
| 371 |
|
|
/* Set SP to point to new stack */ \
|
| 372 |
|
|
"mov r8, LO(%[pxCurrentTCB]) \n\t"\
|
| 373 |
|
|
"orh r8, HI(%[pxCurrentTCB]) \n\t"\
|
| 374 |
|
|
"ld.w r0, r8[0] \n\t"\
|
| 375 |
|
|
"ld.w sp, r0[0] \n"\
|
| 376 |
|
|
\
|
| 377 |
|
|
"LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
|
| 378 |
|
|
\
|
| 379 |
|
|
/* Restore ulCriticalNesting variable */ \
|
| 380 |
|
|
"ld.w r0, sp++ \n\t" \
|
| 381 |
|
|
"mov r8, LO(%[ulCriticalNesting]) \n\t"\
|
| 382 |
|
|
"orh r8, HI(%[ulCriticalNesting]) \n\t"\
|
| 383 |
|
|
"st.w r8[0], r0 \n\t"\
|
| 384 |
|
|
\
|
| 385 |
|
|
/* Restore R0..R7 */ \
|
| 386 |
|
|
"ldm sp++, r0-r7 \n\t"\
|
| 387 |
|
|
\
|
| 388 |
|
|
/* Now, the stack should be R8..R12, LR, PC and SR */ \
|
| 389 |
|
|
"rete" \
|
| 390 |
|
|
: \
|
| 391 |
|
|
: [ulCriticalNesting] "i" (&ulCriticalNesting), \
|
| 392 |
|
|
[pxCurrentTCB] "i" (&pxCurrentTCB), \
|
| 393 |
|
|
[LINE] "i" (__LINE__) \
|
| 394 |
|
|
); \
|
| 395 |
|
|
}
|
| 396 |
|
|
|
| 397 |
|
|
#endif
|
| 398 |
|
|
|
| 399 |
|
|
|
| 400 |
|
|
/*
|
| 401 |
|
|
* portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
|
| 402 |
|
|
*
|
| 403 |
|
|
* NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
|
| 404 |
|
|
*
|
| 405 |
|
|
*/
|
| 406 |
|
|
#define portSAVE_CONTEXT_SCALL() \
|
| 407 |
|
|
{ \
|
| 408 |
|
|
extern volatile unsigned portLONG ulCriticalNesting; \
|
| 409 |
|
|
extern volatile void *volatile pxCurrentTCB; \
|
| 410 |
|
|
\
|
| 411 |
|
|
/* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
|
| 412 |
|
|
/* If SR[M2:M0] == 001 */ \
|
| 413 |
|
|
/* PC and SR are on the stack. */ \
|
| 414 |
|
|
/* Else (other modes) */ \
|
| 415 |
|
|
/* Nothing on the stack. */ \
|
| 416 |
|
|
\
|
| 417 |
|
|
/* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
|
| 418 |
|
|
/* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
|
| 419 |
|
|
/* in an interrupt|exception handler. */ \
|
| 420 |
|
|
\
|
| 421 |
|
|
__asm__ __volatile__ ( \
|
| 422 |
|
|
/* in order to save R0-R7 */ \
|
| 423 |
|
|
"sub sp, 6*4 \n\t"\
|
| 424 |
|
|
/* Save R0..R7 */ \
|
| 425 |
|
|
"stm --sp, r0-r7 \n\t"\
|
| 426 |
|
|
\
|
| 427 |
|
|
/* in order to save R8-R12 and LR */ \
|
| 428 |
|
|
/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
|
| 429 |
|
|
"sub r7, sp,-16*4 \n\t"\
|
| 430 |
|
|
/* Copy PC and SR in other places in the stack. */ \
|
| 431 |
|
|
"ld.w r0, r7[-2*4] \n\t" /* Read SR */\
|
| 432 |
|
|
"st.w r7[-8*4], r0 \n\t" /* Copy SR */\
|
| 433 |
|
|
"ld.w r0, r7[-1*4] \n\t" /* Read PC */\
|
| 434 |
|
|
"st.w r7[-7*4], r0 \n\t" /* Copy PC */\
|
| 435 |
|
|
\
|
| 436 |
|
|
/* Save R8..R12 and LR on the stack. */ \
|
| 437 |
|
|
"stm --r7, r8-r12, lr \n\t"\
|
| 438 |
|
|
\
|
| 439 |
|
|
/* Arriving here we have the following stack organizations: */ \
|
| 440 |
|
|
/* R8..R12, LR, PC, SR, R0..R7. */ \
|
| 441 |
|
|
\
|
| 442 |
|
|
/* Now we can finalize the save. */ \
|
| 443 |
|
|
\
|
| 444 |
|
|
/* Save ulCriticalNesting variable - R0 is overwritten */ \
|
| 445 |
|
|
"mov r8, LO(%[ulCriticalNesting]) \n\t"\
|
| 446 |
|
|
"orh r8, HI(%[ulCriticalNesting]) \n\t"\
|
| 447 |
|
|
"ld.w r0, r8[0] \n\t"\
|
| 448 |
|
|
"st.w --sp, r0" \
|
| 449 |
|
|
: \
|
| 450 |
|
|
: [ulCriticalNesting] "i" (&ulCriticalNesting) \
|
| 451 |
|
|
); \
|
| 452 |
|
|
\
|
| 453 |
|
|
/* Disable the its which may cause a context switch (i.e. cause a change of */ \
|
| 454 |
|
|
/* pxCurrentTCB). */ \
|
| 455 |
|
|
/* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
|
| 456 |
|
|
/* critical section because it is a global structure. */ \
|
| 457 |
|
|
portENTER_CRITICAL(); \
|
| 458 |
|
|
\
|
| 459 |
|
|
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
|
| 460 |
|
|
__asm__ __volatile__ ( \
|
| 461 |
|
|
"mov r8, LO(%[pxCurrentTCB]) \n\t"\
|
| 462 |
|
|
"orh r8, HI(%[pxCurrentTCB]) \n\t"\
|
| 463 |
|
|
"ld.w r0, r8[0] \n\t"\
|
| 464 |
|
|
"st.w r0[0], sp" \
|
| 465 |
|
|
: \
|
| 466 |
|
|
: [pxCurrentTCB] "i" (&pxCurrentTCB) \
|
| 467 |
|
|
); \
|
| 468 |
|
|
}
|
| 469 |
|
|
|
| 470 |
|
|
/*
|
| 471 |
|
|
* portRESTORE_CONTEXT() for SupervisorCALL exception.
|
| 472 |
|
|
*/
|
| 473 |
|
|
#define portRESTORE_CONTEXT_SCALL() \
|
| 474 |
|
|
{ \
|
| 475 |
|
|
extern volatile unsigned portLONG ulCriticalNesting; \
|
| 476 |
|
|
extern volatile void *volatile pxCurrentTCB; \
|
| 477 |
|
|
\
|
| 478 |
|
|
/* Restore all registers */ \
|
| 479 |
|
|
\
|
| 480 |
|
|
/* Set SP to point to new stack */ \
|
| 481 |
|
|
__asm__ __volatile__ ( \
|
| 482 |
|
|
"mov r8, LO(%[pxCurrentTCB]) \n\t"\
|
| 483 |
|
|
"orh r8, HI(%[pxCurrentTCB]) \n\t"\
|
| 484 |
|
|
"ld.w r0, r8[0] \n\t"\
|
| 485 |
|
|
"ld.w sp, r0[0]" \
|
| 486 |
|
|
: \
|
| 487 |
|
|
: [pxCurrentTCB] "i" (&pxCurrentTCB) \
|
| 488 |
|
|
); \
|
| 489 |
|
|
\
|
| 490 |
|
|
/* Leave pxCurrentTCB variable access critical section */ \
|
| 491 |
|
|
portEXIT_CRITICAL(); \
|
| 492 |
|
|
\
|
| 493 |
|
|
__asm__ __volatile__ ( \
|
| 494 |
|
|
/* Restore ulCriticalNesting variable */ \
|
| 495 |
|
|
"ld.w r0, sp++ \n\t"\
|
| 496 |
|
|
"mov r8, LO(%[ulCriticalNesting]) \n\t"\
|
| 497 |
|
|
"orh r8, HI(%[ulCriticalNesting]) \n\t"\
|
| 498 |
|
|
"st.w r8[0], r0 \n\t"\
|
| 499 |
|
|
\
|
| 500 |
|
|
/* skip PC and SR */ \
|
| 501 |
|
|
/* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
|
| 502 |
|
|
"sub r7, sp, -10*4 \n\t"\
|
| 503 |
|
|
/* Restore r8-r12 and LR */ \
|
| 504 |
|
|
"ldm r7++, r8-r12, lr \n\t"\
|
| 505 |
|
|
\
|
| 506 |
|
|
/* RETS will take care of the extra PC and SR restore. */ \
|
| 507 |
|
|
/* So, we have to prepare the stack for this. */ \
|
| 508 |
|
|
"ld.w r0, r7[-8*4] \n\t" /* Read SR */\
|
| 509 |
|
|
"st.w r7[-2*4], r0 \n\t" /* Copy SR */\
|
| 510 |
|
|
"ld.w r0, r7[-7*4] \n\t" /* Read PC */\
|
| 511 |
|
|
"st.w r7[-1*4], r0 \n\t" /* Copy PC */\
|
| 512 |
|
|
\
|
| 513 |
|
|
/* Restore R0..R7 */ \
|
| 514 |
|
|
"ldm sp++, r0-r7 \n\t"\
|
| 515 |
|
|
\
|
| 516 |
|
|
"sub sp, -6*4 \n\t"\
|
| 517 |
|
|
\
|
| 518 |
|
|
"rets" \
|
| 519 |
|
|
: \
|
| 520 |
|
|
: [ulCriticalNesting] "i" (&ulCriticalNesting) \
|
| 521 |
|
|
); \
|
| 522 |
|
|
}
|
| 523 |
|
|
|
| 524 |
|
|
|
| 525 |
|
|
/*
|
| 526 |
|
|
* The ISR used depends on whether the cooperative or
|
| 527 |
|
|
* the preemptive scheduler is being used.
|
| 528 |
|
|
*/
|
| 529 |
|
|
#if configUSE_PREEMPTION == 0
|
| 530 |
|
|
|
| 531 |
|
|
/*
|
| 532 |
|
|
* ISR entry and exit macros. These are only required if a task switch
|
| 533 |
|
|
* is required from the ISR.
|
| 534 |
|
|
*/
|
| 535 |
|
|
#define portENTER_SWITCHING_ISR() \
|
| 536 |
|
|
{ \
|
| 537 |
|
|
/* Save R0..R7 */ \
|
| 538 |
|
|
__asm__ __volatile__ ("stm --sp, r0-r7"); \
|
| 539 |
|
|
\
|
| 540 |
|
|
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
|
| 541 |
|
|
/* there is also no context save. */ \
|
| 542 |
|
|
}
|
| 543 |
|
|
|
| 544 |
|
|
/*
|
| 545 |
|
|
* Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
|
| 546 |
|
|
*/
|
| 547 |
|
|
#define portEXIT_SWITCHING_ISR() \
|
| 548 |
|
|
{ \
|
| 549 |
|
|
__asm__ __volatile__ ( \
|
| 550 |
|
|
/* Restore R0..R7 */ \
|
| 551 |
|
|
"ldm sp++, r0-r7 \n\t"\
|
| 552 |
|
|
\
|
| 553 |
|
|
/* With the cooperative scheduler, as there is no context switch by interrupt, */ \
|
| 554 |
|
|
/* there is also no context restore. */ \
|
| 555 |
|
|
"rete" \
|
| 556 |
|
|
); \
|
| 557 |
|
|
}
|
| 558 |
|
|
|
| 559 |
|
|
#else
|
| 560 |
|
|
|
| 561 |
|
|
/*
|
| 562 |
|
|
* ISR entry and exit macros. These are only required if a task switch
|
| 563 |
|
|
* is required from the ISR.
|
| 564 |
|
|
*/
|
| 565 |
|
|
#define portENTER_SWITCHING_ISR() \
|
| 566 |
|
|
{ \
|
| 567 |
|
|
extern volatile unsigned portLONG ulCriticalNesting; \
|
| 568 |
|
|
extern volatile void *volatile pxCurrentTCB; \
|
| 569 |
|
|
\
|
| 570 |
|
|
/* When we come here */ \
|
| 571 |
|
|
/* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
|
| 572 |
|
|
\
|
| 573 |
|
|
__asm__ __volatile__ ( \
|
| 574 |
|
|
/* Save R0..R7 */ \
|
| 575 |
|
|
"stm --sp, r0-r7 \n\t"\
|
| 576 |
|
|
\
|
| 577 |
|
|
/* Save ulCriticalNesting variable - R0 is overwritten */ \
|
| 578 |
|
|
"mov r8, LO(%[ulCriticalNesting]) \n\t"\
|
| 579 |
|
|
"orh r8, HI(%[ulCriticalNesting]) \n\t"\
|
| 580 |
|
|
"ld.w r0, r8[0] \n\t"\
|
| 581 |
|
|
"st.w --sp, r0 \n\t"\
|
| 582 |
|
|
\
|
| 583 |
|
|
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
|
| 584 |
|
|
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
|
| 585 |
|
|
/* level and allow other lower interrupt level to occur). */ \
|
| 586 |
|
|
/* In this case we don't want to do a task switch because we don't know what the stack */ \
|
| 587 |
|
|
/* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
|
| 588 |
|
|
/* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
|
| 589 |
|
|
/* will just be restoring the interrupt handler, no way!!! */ \
|
| 590 |
|
|
/* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
|
| 591 |
|
|
"ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
|
| 592 |
|
|
"bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
|
| 593 |
|
|
"cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
|
| 594 |
|
|
"brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
|
| 595 |
|
|
\
|
| 596 |
|
|
/* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
|
| 597 |
|
|
"mov r8, LO(%[pxCurrentTCB]) \n\t"\
|
| 598 |
|
|
"orh r8, HI(%[pxCurrentTCB]) \n\t"\
|
| 599 |
|
|
"ld.w r0, r8[0] \n\t"\
|
| 600 |
|
|
"st.w r0[0], sp \n"\
|
| 601 |
|
|
\
|
| 602 |
|
|
"LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \
|
| 603 |
|
|
: \
|
| 604 |
|
|
: [ulCriticalNesting] "i" (&ulCriticalNesting), \
|
| 605 |
|
|
[pxCurrentTCB] "i" (&pxCurrentTCB), \
|
| 606 |
|
|
[LINE] "i" (__LINE__) \
|
| 607 |
|
|
); \
|
| 608 |
|
|
}
|
| 609 |
|
|
|
| 610 |
|
|
/*
|
| 611 |
|
|
* Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
|
| 612 |
|
|
*/
|
| 613 |
|
|
#define portEXIT_SWITCHING_ISR() \
|
| 614 |
|
|
{ \
|
| 615 |
|
|
extern volatile unsigned portLONG ulCriticalNesting; \
|
| 616 |
|
|
extern volatile void *volatile pxCurrentTCB; \
|
| 617 |
|
|
\
|
| 618 |
|
|
__asm__ __volatile__ ( \
|
| 619 |
|
|
/* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
|
| 620 |
|
|
/* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
|
| 621 |
|
|
/* level and allow other lower interrupt level to occur). */ \
|
| 622 |
|
|
/* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
|
| 623 |
|
|
/* did not previously save SP in its TCB. */ \
|
| 624 |
|
|
"ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
|
| 625 |
|
|
"bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
|
| 626 |
|
|
"cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
|
| 627 |
|
|
"brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t"\
|
| 628 |
|
|
\
|
| 629 |
|
|
/* If a switch is required then we just need to call */ \
|
| 630 |
|
|
/* vTaskSwitchContext() as the context has already been */ \
|
| 631 |
|
|
/* saved. */ \
|
| 632 |
|
|
"cp.w r12, 1 \n\t" /* Check if Switch context is required. */\
|
| 633 |
|
|
"brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \
|
| 634 |
|
|
: \
|
| 635 |
|
|
: [LINE] "i" (__LINE__) \
|
| 636 |
|
|
); \
|
| 637 |
|
|
\
|
| 638 |
|
|
/* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
|
| 639 |
|
|
portENTER_CRITICAL(); \
|
| 640 |
|
|
vTaskSwitchContext(); \
|
| 641 |
|
|
portEXIT_CRITICAL(); \
|
| 642 |
|
|
\
|
| 643 |
|
|
__asm__ __volatile__ ( \
|
| 644 |
|
|
"LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t"\
|
| 645 |
|
|
/* Restore the context of which ever task is now the highest */ \
|
| 646 |
|
|
/* priority that is ready to run. */ \
|
| 647 |
|
|
\
|
| 648 |
|
|
/* Restore all registers */ \
|
| 649 |
|
|
\
|
| 650 |
|
|
/* Set SP to point to new stack */ \
|
| 651 |
|
|
"mov r8, LO(%[pxCurrentTCB]) \n\t"\
|
| 652 |
|
|
"orh r8, HI(%[pxCurrentTCB]) \n\t"\
|
| 653 |
|
|
"ld.w r0, r8[0] \n\t"\
|
| 654 |
|
|
"ld.w sp, r0[0] \n"\
|
| 655 |
|
|
\
|
| 656 |
|
|
"LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
|
| 657 |
|
|
\
|
| 658 |
|
|
/* Restore ulCriticalNesting variable */ \
|
| 659 |
|
|
"ld.w r0, sp++ \n\t"\
|
| 660 |
|
|
"mov r8, LO(%[ulCriticalNesting]) \n\t"\
|
| 661 |
|
|
"orh r8, HI(%[ulCriticalNesting]) \n\t"\
|
| 662 |
|
|
"st.w r8[0], r0 \n\t"\
|
| 663 |
|
|
\
|
| 664 |
|
|
/* Restore R0..R7 */ \
|
| 665 |
|
|
"ldm sp++, r0-r7 \n\t"\
|
| 666 |
|
|
\
|
| 667 |
|
|
/* Now, the stack should be R8..R12, LR, PC and SR */ \
|
| 668 |
|
|
"rete" \
|
| 669 |
|
|
: \
|
| 670 |
|
|
: [ulCriticalNesting] "i" (&ulCriticalNesting), \
|
| 671 |
|
|
[pxCurrentTCB] "i" (&pxCurrentTCB), \
|
| 672 |
|
|
[LINE] "i" (__LINE__) \
|
| 673 |
|
|
); \
|
| 674 |
|
|
}
|
| 675 |
|
|
|
| 676 |
|
|
#endif
|
| 677 |
|
|
|
| 678 |
|
|
|
| 679 |
|
|
#define portYIELD() {__asm__ __volatile__ ("scall");}
|
| 680 |
|
|
|
| 681 |
|
|
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
| 682 |
|
|
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
| 683 |
|
|
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
| 684 |
|
|
|
| 685 |
|
|
#ifdef __cplusplus
|
| 686 |
|
|
}
|
| 687 |
|
|
#endif
|
| 688 |
|
|
|
| 689 |
|
|
#endif /* PORTMACRO_H */
|
