OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Source/] [portable/] [GCC/] [OpenRISC/] [portasm.S] - Blame information for rev 675

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 572 jeremybenn
#include "port_spr_defs.h"
2 675 filepang
#include "portmacro.h"
3
#include "FreeRTOSConfig.h"
4
 
5 572 jeremybenn
 
6
        .file           "portasm.S"
7
        .section        .text
8
 
9 621 filepang
.macro portSAVE_CONTEXT
10 572 jeremybenn
        .global pxCurrentTCB
11
        # make rooms in stack
12 675 filepang
        l.addi  r1, r1, -STACKFRAME_SIZE
13 572 jeremybenn
        # early save r3-r5, these are clobber register
14
        l.sw    0x08(r1), r3
15
        l.sw    0x0C(r1), r4
16
        l.sw    0x10(r1), r5
17
        # save SPR_ESR_BASE(0), SPR_EPCR_BASE(0)
18 621 filepang
        l.mfspr r3, r0, SPR_ESR_BASE
19
        l.mfspr r4, r0, SPR_EPCR_BASE
20 572 jeremybenn
        l.sw    0x78(r1), r3
21
        l.sw    0x7C(r1), r4
22 675 filepang
        # Save Context
23 572 jeremybenn
        l.sw    0x00(r1), r9
24
        l.sw    0x04(r1), r2
25
        l.sw    0x14(r1), r6
26
        l.sw    0x18(r1), r7
27
        l.sw    0x1C(r1), r8
28
        l.sw    0x20(r1), r10
29
        l.sw    0x24(r1), r11
30
        l.sw    0x28(r1), r12
31
        l.sw    0x2C(r1), r13
32
        l.sw    0x30(r1), r14
33
        l.sw    0x34(r1), r15
34
        l.sw    0x38(r1), r16
35
        l.sw    0x3C(r1), r17
36
        l.sw    0x40(r1), r18
37
        l.sw    0x44(r1), r19
38
        l.sw    0x48(r1), r20
39
        l.sw    0x4C(r1), r21
40
        l.sw    0x50(r1), r22
41
        l.sw    0x54(r1), r23
42
        l.sw    0x58(r1), r24
43
        l.sw    0x5C(r1), r25
44
        l.sw    0x60(r1), r26
45
        l.sw    0x64(r1), r27
46
        l.sw    0x68(r1), r28
47
        l.sw    0x6C(r1), r29
48
        l.sw    0x70(r1), r30
49
        l.sw    0x74(r1), r31
50
        # Save the top of stack in TCB
51
        l.movhi r3, hi(pxCurrentTCB)
52
        l.ori   r3, r3, lo(pxCurrentTCB)
53
        l.lwz   r3, 0x0(r3)
54
        l.sw    0x0(r3), r1
55
        # restore clobber register
56
        l.lwz   r3, 0x08(r1)
57
        l.lwz   r4, 0x0C(r1)
58
        l.lwz   r5, 0x10(r1)
59 621 filepang
.endm
60 572 jeremybenn
 
61 621 filepang
 
62
.macro portRESTORE_CONTEXT
63 572 jeremybenn
        l.movhi r3, hi(pxCurrentTCB)
64
        l.ori   r3, r3, lo(pxCurrentTCB)
65
        l.lwz   r3, 0x0(r3)
66
        l.lwz   r1, 0x0(r3)
67
        # restore context
68 675 filepang
        l.lwz   r9,  0x00(r1)
69
        l.lwz   r2,  0x04(r1)
70
        l.lwz   r6,  0x14(r1)
71
        l.lwz   r7,  0x18(r1)
72
        l.lwz   r8,  0x1C(r1)
73 572 jeremybenn
        l.lwz   r10, 0x20(r1)
74
        l.lwz   r11, 0x24(r1)
75
        l.lwz   r12, 0x28(r1)
76
        l.lwz   r13, 0x2C(r1)
77
        l.lwz   r14, 0x30(r1)
78
        l.lwz   r15, 0x34(r1)
79
        l.lwz   r16, 0x38(r1)
80
        l.lwz   r17, 0x3C(r1)
81
        l.lwz   r18, 0x40(r1)
82
        l.lwz   r19, 0x44(r1)
83
        l.lwz   r20, 0x48(r1)
84
        l.lwz   r21, 0x4C(r1)
85
        l.lwz   r22, 0x50(r1)
86
        l.lwz   r23, 0x54(r1)
87
        l.lwz   r24, 0x58(r1)
88
        l.lwz   r25, 0x5C(r1)
89
        l.lwz   r26, 0x60(r1)
90
        l.lwz   r27, 0x64(r1)
91
        l.lwz   r28, 0x68(r1)
92
        l.lwz   r29, 0x6C(r1)
93
        l.lwz   r30, 0x70(r1)
94
        l.lwz   r31, 0x74(r1)
95
        # restore SPR_ESR_BASE(0), SPR_EPCR_BASE(0)
96 675 filepang
        l.lwz   r3,  0x78(r1)
97
        l.lwz   r4,  0x7C(r1)
98
        l.mtspr r0,  r3, SPR_ESR_BASE
99
        l.mtspr r0,  r4, SPR_EPCR_BASE
100 572 jeremybenn
        # restore clobber register
101 675 filepang
        l.lwz   r3,  0x08(r1)
102
        l.lwz   r4,  0x0C(r1)
103
        l.lwz   r5,  0x10(r1)
104
        l.addi  r1,  r1, STACKFRAME_SIZE
105 572 jeremybenn
        l.rfe
106
        l.nop
107 621 filepang
.endm
108 572 jeremybenn
 
109
 
110 621 filepang
.text
111
.global vPortTickHandler
112
.type   vPortTickHandler, %function
113
vPortTickHandler:
114
        portSAVE_CONTEXT
115
 
116
        l.mfspr r3, r0, SPR_TTMR
117
        l.movhi r4, hi(SPR_TTMR_IP)
118
        l.ori   r4, r4, lo(SPR_TTMR_IP)
119
        l.xori  r4, r4, 0xffffffff
120
        l.and   r3, r3, r4                              # clear tick timer interrupt
121
        l.mtspr r0, r3, SPR_TTMR
122 572 jeremybenn
 
123 621 filepang
        l.jal   vTaskIncrementTick
124
        l.nop
125
.if configUSE_PREEMPTION == 0
126
        # do nothing
127
.else
128
        l.jal   vTaskSwitchContext
129
        l.nop
130
.endif
131
 
132
        portRESTORE_CONTEXT
133
.size   vPortTickHandler, .-vPortTickHandler
134
 
135
 
136 572 jeremybenn
.text
137 621 filepang
.global vPortSystemCall
138
.type   vPortSystemCall, %function
139
vPortSystemCall:
140 664 filepang
        portSAVE_CONTEXT
141 621 filepang
 
142 664 filepang
        l.jal   vTaskSwitchContext
143 572 jeremybenn
        l.nop
144 621 filepang
 
145
        portRESTORE_CONTEXT
146
.size   vPortSystemCall, .-vPortSystemCall
147
 
148
 
149
.text
150
.global vPortExtIntHandler
151
.type   vPortExtIntHandler, %function
152
vPortExtIntHandler:
153
        portSAVE_CONTEXT
154
 
155
    l.jal       int_main
156
        l.nop
157
 
158
.if configUSE_PREEMPTION == 0
159
        # do nothing
160
.else
161 572 jeremybenn
        l.jal   vTaskSwitchContext
162
        l.nop
163 621 filepang
.endif
164 572 jeremybenn
 
165 621 filepang
        portRESTORE_CONTEXT
166
.size   vPortExtIntHandler, .-vPortExtIntHandler
167 572 jeremybenn
 
168 621 filepang
 
169
.text
170
.global vPortMiscIntHandler
171
.type   vPortMiscIntHandler, %function
172
vPortMiscIntHandler:
173
        portSAVE_CONTEXT
174
 
175
    l.jal       misc_int_handler
176
        l.lwz   r3, -4(r1)
177
 
178
.if configUSE_PREEMPTION == 0
179
        # do nothing
180
.else
181
        l.jal   vTaskSwitchContext
182
        l.nop
183
.endif
184
 
185
        portRESTORE_CONTEXT
186
.size   vPortMiscIntHandler, .-vPortMiscIntHandler

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.