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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Source/] [portable/] [GCC/] [PPC405_Xilinx/] [portasm.S] - Blame information for rev 572

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1 572 jeremybenn
/*
2
    FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
3
 
4
    ***************************************************************************
5
    *                                                                         *
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    * If you are:                                                             *
7
    *                                                                         *
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    *    + New to FreeRTOS,                                                   *
9
    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *
10
    *    + Looking for basic training,                                        *
11
    *    + Wanting to improve your FreeRTOS skills and productivity           *
12
    *                                                                         *
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    * then take a look at the FreeRTOS books - available as PDF or paperback  *
14
    *                                                                         *
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    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *
16
    *                  http://www.FreeRTOS.org/Documentation                  *
17
    *                                                                         *
18
    * A pdf reference manual is also available.  Both are usually delivered   *
19
    * to your inbox within 20 minutes to two hours when purchased between 8am *
20
    * and 8pm GMT (although please allow up to 24 hours in case of            *
21
    * exceptional circumstances).  Thank you for your support!                *
22
    *                                                                         *
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    ***************************************************************************
24
 
25
    This file is part of the FreeRTOS distribution.
26
 
27
    FreeRTOS is free software; you can redistribute it and/or modify it under
28
    the terms of the GNU General Public License (version 2) as published by the
29
    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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    ***NOTE*** The exception to the GPL is included to allow you to distribute
31
    a combined work that includes FreeRTOS without being obliged to provide the
32
    source code for proprietary components outside of the FreeRTOS kernel.
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    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
34
    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
35
    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
36
    more details. You should have received a copy of the GNU General Public
37
    License and the FreeRTOS license exception along with FreeRTOS; if not it
38
    can be viewed here: http://www.freertos.org/a00114.html and also obtained
39
    by writing to Richard Barry, contact details for whom are available on the
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    FreeRTOS WEB site.
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42
    1 tab == 4 spaces!
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    http://www.FreeRTOS.org - Documentation, latest information, license and
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    contact details.
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47
    http://www.SafeRTOS.com - A version that is certified for use in safety
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    critical systems.
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50
    http://www.OpenRTOS.com - Commercial support, development, porting,
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    licensing and training services.
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*/
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54
#include "FreeRTOSConfig.h"
55
 
56
        .extern pxCurrentTCB
57
        .extern vTaskSwitchContext
58
        .extern vTaskIncrementTick
59
        .extern vPortISRHandler
60
 
61
        .global vPortStartFirstTask
62
        .global vPortYield
63
        .global vPortTickISR
64
        .global vPortISRWrapper
65
        .global vPortSaveFPURegisters
66
        .global vPortRestoreFPURegisters
67
 
68
.set    BChainField, 0
69
.set    NextLRField, BChainField + 4
70
.set    MSRField,    NextLRField + 4
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.set    PCField,     MSRField    + 4
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.set    LRField,     PCField     + 4
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.set    CTRField,    LRField     + 4
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.set    XERField,    CTRField    + 4
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.set    CRField,     XERField    + 4
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.set    USPRG0Field, CRField     + 4
77
.set    r0Field,     USPRG0Field + 4
78
.set    r2Field,     r0Field     + 4
79
.set    r3r31Field,  r2Field     + 4
80
.set    IFrameSize,  r3r31Field  + ( ( 31 - 3 ) + 1 ) * 4
81
 
82
 
83
.macro portSAVE_STACK_POINTER_AND_LR
84
 
85
        /* Get the address of the TCB. */
86
        xor             R0, R0, R0
87
        addis   R2, R0, pxCurrentTCB@ha
88
        lwz             R2,     pxCurrentTCB@l( R2 )
89
 
90
        /* Store the stack pointer into the TCB */
91
        stw             SP,     0( R2 )
92
 
93
        /* Save the link register */
94
        stwu    R1, -24( R1 )
95
        mflr    R0
96
        stw             R31, 20( R1 )
97
        stw             R0, 28( R1 )
98
        mr              R31, r1
99
 
100
.endm
101
 
102
.macro portRESTORE_STACK_POINTER_AND_LR
103
 
104
        /* Restore the link register */
105
        lwz             R11, 0( R1 )
106
        lwz             R0, 4( R11 )
107
        mtlr    R0
108
        lwz             R31, -4( R11 )
109
        mr              R1, R11
110
 
111
        /* Get the address of the TCB. */
112
        xor             R0, R0, R0
113
        addis   SP, R0, pxCurrentTCB@ha
114
        lwz             SP,     pxCurrentTCB@l( R1 )
115
 
116
        /* Get the task stack pointer from the TCB. */
117
        lwz             SP, 0( SP )
118
 
119
.endm
120
 
121
 
122
vPortStartFirstTask:
123
 
124
        /* Get the address of the TCB. */
125
        xor             R0, R0, R0
126
    addis   SP, R0, pxCurrentTCB@ha
127
    lwz         SP,     pxCurrentTCB@l( SP )
128
 
129
        /* Get the task stack pointer from the TCB. */
130
        lwz             SP, 0( SP )
131
 
132
        /* Restore MSR register to SRR1. */
133
        lwz             R0, MSRField(R1)
134
        mtsrr1  R0
135
 
136
        /* Restore current PC location to SRR0. */
137
        lwz             R0, PCField(R1)
138
        mtsrr0  R0
139
 
140
        /* Save  USPRG0 register */
141
        lwz             R0, USPRG0Field(R1)
142
        mtspr   0x100,R0
143
 
144
        /* Restore Condition register */
145
        lwz             R0, CRField(R1)
146
        mtcr    R0
147
 
148
        /* Restore Fixed Point Exception register */
149
        lwz             R0, XERField(R1)
150
        mtxer   R0
151
 
152
        /* Restore Counter register */
153
        lwz             R0, CTRField(R1)
154
        mtctr   R0
155
 
156
        /* Restore Link register */
157
        lwz             R0, LRField(R1)
158
        mtlr    R0
159
 
160
        /* Restore remaining GPR registers. */
161
        lmw     R3,r3r31Field(R1)
162
 
163
        /* Restore r0 and r2. */
164
        lwz             R0, r0Field(R1)
165
        lwz             R2, r2Field(R1)
166
 
167
        /* Remove frame from stack */
168
        addi    R1,R1,IFrameSize
169
 
170
        /* Return into the first task */
171
        rfi
172
 
173
 
174
 
175
vPortYield:
176
 
177
        portSAVE_STACK_POINTER_AND_LR
178
        bl vTaskSwitchContext
179
        portRESTORE_STACK_POINTER_AND_LR
180
        blr
181
 
182
vPortTickISR:
183
 
184
        portSAVE_STACK_POINTER_AND_LR
185
        bl vTaskIncrementTick
186
 
187
        #if configUSE_PREEMPTION == 1
188
                bl vTaskSwitchContext
189
        #endif
190
 
191
        /* Clear the interrupt */
192
        lis             R0, 2048
193
        mttsr   R0
194
 
195
        portRESTORE_STACK_POINTER_AND_LR
196
        blr
197
 
198
vPortISRWrapper:
199
 
200
        portSAVE_STACK_POINTER_AND_LR
201
        bl vPortISRHandler
202
        portRESTORE_STACK_POINTER_AND_LR
203
        blr
204
 
205
#if configUSE_FPU == 1
206
 
207
vPortSaveFPURegisters:
208
 
209
        /* Enable APU and mark FPU as present. */
210
        mfmsr   r0
211
        xor             r30, r30, r30
212
        oris    r30, r30, 512
213
        ori             r30, r30, 8192
214
        or              r0, r0, r30
215
        mtmsr   r0
216
 
217
#ifdef USE_DP_FPU
218
 
219
        /* Buffer address is in r3.  Save each flop register into an offset from
220
        this buffer address. */
221
        stfd    f0, 0(r3)
222
        stfd    f1, 8(r3)
223
        stfd    f2, 16(r3)
224
        stfd    f3, 24(r3)
225
        stfd    f4, 32(r3)
226
        stfd    f5, 40(r3)
227
        stfd    f6, 48(r3)
228
        stfd    f7, 56(r3)
229
        stfd    f8, 64(r3)
230
        stfd    f9, 72(r3)
231
        stfd    f10, 80(r3)
232
        stfd    f11, 88(r3)
233
        stfd    f12, 96(r3)
234
        stfd    f13, 104(r3)
235
        stfd    f14, 112(r3)
236
        stfd    f15, 120(r3)
237
        stfd    f16, 128(r3)
238
        stfd    f17, 136(r3)
239
        stfd    f18, 144(r3)
240
        stfd    f19, 152(r3)
241
        stfd    f20, 160(r3)
242
        stfd    f21, 168(r3)
243
        stfd    f22, 176(r3)
244
        stfd    f23, 184(r3)
245
        stfd    f24, 192(r3)
246
        stfd    f25, 200(r3)
247
        stfd    f26, 208(r3)
248
        stfd    f27, 216(r3)
249
        stfd    f28, 224(r3)
250
        stfd    f29, 232(r3)
251
        stfd    f30, 240(r3)
252
        stfd    f31, 248(r3)
253
 
254
        /* Also save the FPSCR. */
255
        mffs    f31
256
        stfs    f31, 256(r3)
257
 
258
#else
259
 
260
        /* Buffer address is in r3.  Save each flop register into an offset from
261
        this buffer address. */
262
        stfs    f0, 0(r3)
263
        stfs    f1, 4(r3)
264
        stfs    f2, 8(r3)
265
        stfs    f3, 12(r3)
266
        stfs    f4, 16(r3)
267
        stfs    f5, 20(r3)
268
        stfs    f6, 24(r3)
269
        stfs    f7, 28(r3)
270
        stfs    f8, 32(r3)
271
        stfs    f9, 36(r3)
272
        stfs    f10, 40(r3)
273
        stfs    f11, 44(r3)
274
        stfs    f12, 48(r3)
275
        stfs    f13, 52(r3)
276
        stfs    f14, 56(r3)
277
        stfs    f15, 60(r3)
278
        stfs    f16, 64(r3)
279
        stfs    f17, 68(r3)
280
        stfs    f18, 72(r3)
281
        stfs    f19, 76(r3)
282
        stfs    f20, 80(r3)
283
        stfs    f21, 84(r3)
284
        stfs    f22, 88(r3)
285
        stfs    f23, 92(r3)
286
        stfs    f24, 96(r3)
287
        stfs    f25, 100(r3)
288
        stfs    f26, 104(r3)
289
        stfs    f27, 108(r3)
290
        stfs    f28, 112(r3)
291
        stfs    f29, 116(r3)
292
        stfs    f30, 120(r3)
293
        stfs    f31, 124(r3)
294
 
295
        /* Also save the FPSCR. */
296
        mffs    f31
297
        stfs    f31, 128(r3)
298
 
299
#endif
300
 
301
        blr
302
 
303
#endif /* configUSE_FPU. */
304
 
305
 
306
#if configUSE_FPU == 1
307
 
308
vPortRestoreFPURegisters:
309
 
310
        /* Enable APU and mark FPU as present. */
311
        mfmsr   r0
312
        xor             r30, r30, r30
313
        oris    r30, r30, 512
314
        ori             r30, r30, 8192
315
        or              r0, r0, r30
316
        mtmsr   r0
317
 
318
#ifdef USE_DP_FPU
319
 
320
        /* Buffer address is in r3.  Restore each flop register from an offset
321
        into this buffer.
322
 
323
        First the FPSCR. */
324
        lfs             f31, 256(r3)
325
        mtfsf   f31, 7
326
 
327
        lfd             f0, 0(r3)
328
        lfd         f1, 8(r3)
329
        lfd             f2, 16(r3)
330
        lfd             f3, 24(r3)
331
        lfd             f4, 32(r3)
332
        lfd             f5, 40(r3)
333
        lfd             f6, 48(r3)
334
        lfd             f7, 56(r3)
335
        lfd             f8, 64(r3)
336
        lfd             f9, 72(r3)
337
        lfd             f10, 80(r3)
338
        lfd             f11, 88(r3)
339
        lfd             f12, 96(r3)
340
        lfd             f13, 104(r3)
341
        lfd             f14, 112(r3)
342
        lfd             f15, 120(r3)
343
        lfd             f16, 128(r3)
344
        lfd             f17, 136(r3)
345
        lfd             f18, 144(r3)
346
        lfd             f19, 152(r3)
347
        lfd             f20, 160(r3)
348
        lfd             f21, 168(r3)
349
        lfd             f22, 176(r3)
350
        lfd             f23, 184(r3)
351
        lfd             f24, 192(r3)
352
        lfd             f25, 200(r3)
353
        lfd             f26, 208(r3)
354
        lfd             f27, 216(r3)
355
        lfd             f28, 224(r3)
356
        lfd             f29, 232(r3)
357
        lfd             f30, 240(r3)
358
        lfd             f31, 248(r3)
359
 
360
#else
361
 
362
        /* Buffer address is in r3.  Restore each flop register from an offset
363
        into this buffer.
364
 
365
        First the FPSCR. */
366
        lfs             f31, 128(r3)
367
        mtfsf   f31, 7
368
 
369
        lfs             f0, 0(r3)
370
        lfs             f1, 4(r3)
371
        lfs             f2, 8(r3)
372
        lfs             f3, 12(r3)
373
        lfs             f4, 16(r3)
374
        lfs             f5, 20(r3)
375
        lfs             f6, 24(r3)
376
        lfs             f7, 28(r3)
377
        lfs             f8, 32(r3)
378
        lfs             f9, 36(r3)
379
        lfs             f10, 40(r3)
380
        lfs             f11, 44(r3)
381
        lfs             f12, 48(r3)
382
        lfs             f13, 52(r3)
383
        lfs             f14, 56(r3)
384
        lfs             f15, 60(r3)
385
        lfs             f16, 64(r3)
386
        lfs             f17, 68(r3)
387
        lfs             f18, 72(r3)
388
        lfs             f19, 76(r3)
389
        lfs             f20, 80(r3)
390
        lfs             f21, 84(r3)
391
        lfs             f22, 88(r3)
392
        lfs             f23, 92(r3)
393
        lfs             f24, 96(r3)
394
        lfs             f25, 100(r3)
395
        lfs             f26, 104(r3)
396
        lfs             f27, 108(r3)
397
        lfs             f28, 112(r3)
398
        lfs             f29, 116(r3)
399
        lfs             f30, 120(r3)
400
        lfs             f31, 124(r3)
401
 
402
#endif
403
 
404
        blr
405
 
406
#endif /* configUSE_FPU. */
407
 
408
 

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