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// ----------------------------------------------------------------------------

//          ATMEL Microcontroller Software Support  -  ROUSSET  -

// ----------------------------------------------------------------------------

//  The software is delivered "AS IS" without warranty or condition of any

//  kind, either express, implied or statutory. This includes without

//  limitation any warranty or condition with respect to merchantability or

//  fitness for any particular purpose, or against the infringements of

//  intellectual property rights of others.

// ----------------------------------------------------------------------------

// File Name           : AT91SAM7S64.h

// Object              : AT91SAM7S64 definitions

// Generated           : AT91 SW Application Group  07/16/2004 (07:43:09)

// 

// CVS Reference       : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004//

// CVS Reference       : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004//

// CVS Reference       : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004//

// CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug  2 14:45:38 2002//

// CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//

// CVS Reference       : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//

// CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//

// CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//

// CVS Reference       : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004//

// CVS Reference       : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//

// CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov  8 13:26:40 2002//

// CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//

// CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb  7 10:30:08 2003//

// CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//

// CVS Reference       : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//

// CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//

// ----------------------------------------------------------------------------

// Hardware register definition

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR System Peripherals

// *****************************************************************************

// *** Register offset in AT91S_SYSC structure ***

#define SYSC_AIC_SMR    ( 0) // Source Mode Register

#define SYSC_AIC_SVR    (128) // Source Vector Register

#define SYSC_AIC_IVR    (256) // IRQ Vector Register

#define SYSC_AIC_FVR    (260) // FIQ Vector Register

#define SYSC_AIC_ISR    (264) // Interrupt Status Register

#define SYSC_AIC_IPR    (268) // Interrupt Pending Register

#define SYSC_AIC_IMR    (272) // Interrupt Mask Register

#define SYSC_AIC_CISR   (276) // Core Interrupt Status Register

#define SYSC_AIC_IECR   (288) // Interrupt Enable Command Register

#define SYSC_AIC_IDCR   (292) // Interrupt Disable Command Register

#define SYSC_AIC_ICCR   (296) // Interrupt Clear Command Register

#define SYSC_AIC_ISCR   (300) // Interrupt Set Command Register

#define SYSC_AIC_EOICR  (304) // End of Interrupt Command Register

#define SYSC_AIC_SPU    (308) // Spurious Vector Register

#define SYSC_AIC_DCR    (312) // Debug Control Register (Protect)

#define SYSC_AIC_FFER   (320) // Fast Forcing Enable Register

#define SYSC_AIC_FFDR   (324) // Fast Forcing Disable Register

#define SYSC_AIC_FFSR   (328) // Fast Forcing Status Register

#define SYSC_DBGU_CR    (512) // Control Register

#define SYSC_DBGU_MR    (516) // Mode Register

#define SYSC_DBGU_IER   (520) // Interrupt Enable Register

#define SYSC_DBGU_IDR   (524) // Interrupt Disable Register

#define SYSC_DBGU_IMR   (528) // Interrupt Mask Register

#define SYSC_DBGU_CSR   (532) // Channel Status Register

#define SYSC_DBGU_RHR   (536) // Receiver Holding Register

#define SYSC_DBGU_THR   (540) // Transmitter Holding Register

#define SYSC_DBGU_BRGR  (544) // Baud Rate Generator Register

#define SYSC_DBGU_C1R   (576) // Chip ID1 Register

#define SYSC_DBGU_C2R   (580) // Chip ID2 Register

#define SYSC_DBGU_FNTR  (584) // Force NTRST Register

#define SYSC_DBGU_RPR   (768) // Receive Pointer Register

#define SYSC_DBGU_RCR   (772) // Receive Counter Register

#define SYSC_DBGU_TPR   (776) // Transmit Pointer Register

#define SYSC_DBGU_TCR   (780) // Transmit Counter Register

#define SYSC_DBGU_RNPR  (784) // Receive Next Pointer Register

#define SYSC_DBGU_RNCR  (788) // Receive Next Counter Register

#define SYSC_DBGU_TNPR  (792) // Transmit Next Pointer Register

#define SYSC_DBGU_TNCR  (796) // Transmit Next Counter Register

#define SYSC_DBGU_PTCR  (800) // PDC Transfer Control Register

#define SYSC_DBGU_PTSR  (804) // PDC Transfer Status Register

#define SYSC_PIOA_PER   (1024) // PIO Enable Register

#define SYSC_PIOA_PDR   (1028) // PIO Disable Register

#define SYSC_PIOA_PSR   (1032) // PIO Status Register

#define SYSC_PIOA_OER   (1040) // Output Enable Register

#define SYSC_PIOA_ODR   (1044) // Output Disable Registerr

#define SYSC_PIOA_OSR   (1048) // Output Status Register

#define SYSC_PIOA_IFER  (1056) // Input Filter Enable Register

#define SYSC_PIOA_IFDR  (1060) // Input Filter Disable Register

#define SYSC_PIOA_IFSR  (1064) // Input Filter Status Register

#define SYSC_PIOA_SODR  (1072) // Set Output Data Register

#define SYSC_PIOA_CODR  (1076) // Clear Output Data Register

#define SYSC_PIOA_ODSR  (1080) // Output Data Status Register

#define SYSC_PIOA_PDSR  (1084) // Pin Data Status Register

#define SYSC_PIOA_IER   (1088) // Interrupt Enable Register

#define SYSC_PIOA_IDR   (1092) // Interrupt Disable Register

#define SYSC_PIOA_IMR   (1096) // Interrupt Mask Register

#define SYSC_PIOA_ISR   (1100) // Interrupt Status Register

#define SYSC_PIOA_MDER  (1104) // Multi-driver Enable Register

#define SYSC_PIOA_MDDR  (1108) // Multi-driver Disable Register

#define SYSC_PIOA_MDSR  (1112) // Multi-driver Status Register

#define SYSC_PIOA_PPUDR (1120) // Pull-up Disable Register

#define SYSC_PIOA_PPUER (1124) // Pull-up Enable Register

#define SYSC_PIOA_PPUSR (1128) // Pad Pull-up Status Register

#define SYSC_PIOA_ASR   (1136) // Select A Register

#define SYSC_PIOA_BSR   (1140) // Select B Register

#define SYSC_PIOA_ABSR  (1144) // AB Select Status Register

#define SYSC_PIOA_OWER  (1184) // Output Write Enable Register

#define SYSC_PIOA_OWDR  (1188) // Output Write Disable Register

#define SYSC_PIOA_OWSR  (1192) // Output Write Status Register

#define SYSC_PMC_SCER   (3072) // System Clock Enable Register

#define SYSC_PMC_SCDR   (3076) // System Clock Disable Register

#define SYSC_PMC_SCSR   (3080) // System Clock Status Register

#define SYSC_PMC_PCER   (3088) // Peripheral Clock Enable Register

#define SYSC_PMC_PCDR   (3092) // Peripheral Clock Disable Register

#define SYSC_PMC_PCSR   (3096) // Peripheral Clock Status Register

#define SYSC_PMC_MOR    (3104) // Main Oscillator Register

#define SYSC_PMC_MCFR   (3108) // Main Clock  Frequency Register

#define SYSC_PMC_PLLR   (3116) // PLL Register

#define SYSC_PMC_MCKR   (3120) // Master Clock Register

#define SYSC_PMC_PCKR   (3136) // Programmable Clock Register

#define SYSC_PMC_IER    (3168) // Interrupt Enable Register

#define SYSC_PMC_IDR    (3172) // Interrupt Disable Register

#define SYSC_PMC_SR     (3176) // Status Register

#define SYSC_PMC_IMR    (3180) // Interrupt Mask Register

#define SYSC_RSTC_RCR   (3328) // Reset Control Register

#define SYSC_RSTC_RSR   (3332) // Reset Status Register

#define SYSC_RSTC_RMR   (3336) // Reset Mode Register

#define SYSC_RTTC_RTMR  (3360) // Real-time Mode Register

#define SYSC_RTTC_RTAR  (3364) // Real-time Alarm Register

#define SYSC_RTTC_RTVR  (3368) // Real-time Value Register

#define SYSC_RTTC_RTSR  (3372) // Real-time Status Register

#define SYSC_PITC_PIMR  (3376) // Period Interval Mode Register

#define SYSC_PITC_PISR  (3380) // Period Interval Status Register

#define SYSC_PITC_PIVR  (3384) // Period Interval Value Register

#define SYSC_PITC_PIIR  (3388) // Period Interval Image Register

#define SYSC_WDTC_WDCR  (3392) // Watchdog Control Register

#define SYSC_WDTC_WDMR  (3396) // Watchdog Mode Register

#define SYSC_WDTC_WDSR  (3400) // Watchdog Status Register

#define SYSC_SYSC_VRPM  (3424) // Voltage Regulator Power Mode Register

// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- 

#define AT91C_SYSC_PSTDBY         (0x1 <<  0) // (SYSC) Voltage Regulator Power Mode

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller

// *****************************************************************************

// *** Register offset in AT91S_AIC structure ***

#define AIC_SMR         ( 0) // Source Mode Register

#define AIC_SVR         (128) // Source Vector Register

#define AIC_IVR         (256) // IRQ Vector Register

#define AIC_FVR         (260) // FIQ Vector Register

#define AIC_ISR         (264) // Interrupt Status Register

#define AIC_IPR         (268) // Interrupt Pending Register

#define AIC_IMR         (272) // Interrupt Mask Register

#define AIC_CISR        (276) // Core Interrupt Status Register

#define AIC_IECR        (288) // Interrupt Enable Command Register

#define AIC_IDCR        (292) // Interrupt Disable Command Register

#define AIC_ICCR        (296) // Interrupt Clear Command Register

#define AIC_ISCR        (300) // Interrupt Set Command Register

#define AIC_EOICR       (304) // End of Interrupt Command Register

#define AIC_SPU         (308) // Spurious Vector Register

#define AIC_DCR         (312) // Debug Control Register (Protect)

#define AIC_FFER        (320) // Fast Forcing Enable Register

#define AIC_FFDR        (324) // Fast Forcing Disable Register

#define AIC_FFSR        (328) // Fast Forcing Status Register

// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 

#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level

#define         AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level

#define         AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level

#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type

#define         AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive

#define         AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered

#define         AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive

#define         AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered

// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 

#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status

#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status

// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 

#define AT91C_AIC_DCR_PROT        (0x1 <<  0) // (AIC) Protection Mode

#define AT91C_AIC_DCR_GMSK        (0x1 <<  1) // (AIC) General Mask

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Debug Unit

// *****************************************************************************

// *** Register offset in AT91S_DBGU structure ***

#define DBGU_CR         ( 0) // Control Register

#define DBGU_MR         ( 4) // Mode Register

#define DBGU_IER        ( 8) // Interrupt Enable Register

#define DBGU_IDR        (12) // Interrupt Disable Register

#define DBGU_IMR        (16) // Interrupt Mask Register

#define DBGU_CSR        (20) // Channel Status Register

#define DBGU_RHR        (24) // Receiver Holding Register

#define DBGU_THR        (28) // Transmitter Holding Register

#define DBGU_BRGR       (32) // Baud Rate Generator Register

#define DBGU_C1R        (64) // Chip ID1 Register

#define DBGU_C2R        (68) // Chip ID2 Register

#define DBGU_FNTR       (72) // Force NTRST Register

#define DBGU_RPR        (256) // Receive Pointer Register

#define DBGU_RCR        (260) // Receive Counter Register

#define DBGU_TPR        (264) // Transmit Pointer Register

#define DBGU_TCR        (268) // Transmit Counter Register

#define DBGU_RNPR       (272) // Receive Next Pointer Register

#define DBGU_RNCR       (276) // Receive Next Counter Register

#define DBGU_TNPR       (280) // Transmit Next Pointer Register

#define DBGU_TNCR       (284) // Transmit Next Counter Register

#define DBGU_PTCR       (288) // PDC Transfer Control Register

#define DBGU_PTSR       (292) // PDC Transfer Status Register

// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 

#define AT91C_US_RSTRX            (0x1 <<  2) // (DBGU) Reset Receiver

#define AT91C_US_RSTTX            (0x1 <<  3) // (DBGU) Reset Transmitter

#define AT91C_US_RXEN             (0x1 <<  4) // (DBGU) Receiver Enable

#define AT91C_US_RXDIS            (0x1 <<  5) // (DBGU) Receiver Disable

#define AT91C_US_TXEN             (0x1 <<  6) // (DBGU) Transmitter Enable

#define AT91C_US_TXDIS            (0x1 <<  7) // (DBGU) Transmitter Disable

// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 

#define AT91C_US_PAR              (0x7 <<  9) // (DBGU) Parity type

#define         AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity

#define         AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity

#define         AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)

#define         AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)

#define         AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity

#define         AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode

#define AT91C_US_CHMODE           (0x3 << 14) // (DBGU) Channel Mode

#define         AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.

#define         AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.

#define         AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.

#define         AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.

// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 

#define AT91C_US_RXRDY            (0x1 <<  0) // (DBGU) RXRDY Interrupt

#define AT91C_US_TXRDY            (0x1 <<  1) // (DBGU) TXRDY Interrupt

#define AT91C_US_ENDRX            (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt

#define AT91C_US_ENDTX            (0x1 <<  4) // (DBGU) End of Transmit Interrupt

#define AT91C_US_OVRE             (0x1 <<  5) // (DBGU) Overrun Interrupt

#define AT91C_US_FRAME            (0x1 <<  6) // (DBGU) Framing Error Interrupt

#define AT91C_US_PARE             (0x1 <<  7) // (DBGU) Parity Error Interrupt

#define AT91C_US_TXEMPTY          (0x1 <<  9) // (DBGU) TXEMPTY Interrupt

#define AT91C_US_TXBUFE           (0x1 << 11) // (DBGU) TXBUFE Interrupt

#define AT91C_US_RXBUFF           (0x1 << 12) // (DBGU) RXBUFF Interrupt

#define AT91C_US_COMM_TX          (0x1 << 30) // (DBGU) COMM_TX Interrupt

#define AT91C_US_COMM_RX          (0x1 << 31) // (DBGU) COMM_RX Interrupt

// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 

// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 

// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 

// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 

#define AT91C_US_FORCE_NTRST      (0x1 <<  0) // (DBGU) Force NTRST in JTAG

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Peripheral Data Controller

// *****************************************************************************

// *** Register offset in AT91S_PDC structure ***

#define PDC_RPR         ( 0) // Receive Pointer Register

#define PDC_RCR         ( 4) // Receive Counter Register

#define PDC_TPR         ( 8) // Transmit Pointer Register

#define PDC_TCR         (12) // Transmit Counter Register

#define PDC_RNPR        (16) // Receive Next Pointer Register

#define PDC_RNCR        (20) // Receive Next Counter Register

#define PDC_TNPR        (24) // Transmit Next Pointer Register

#define PDC_TNCR        (28) // Transmit Next Counter Register

#define PDC_PTCR        (32) // PDC Transfer Control Register

#define PDC_PTSR        (36) // PDC Transfer Status Register

// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 

#define AT91C_PDC_RXTEN           (0x1 <<  0) // (PDC) Receiver Transfer Enable

#define AT91C_PDC_RXTDIS          (0x1 <<  1) // (PDC) Receiver Transfer Disable

#define AT91C_PDC_TXTEN           (0x1 <<  8) // (PDC) Transmitter Transfer Enable

#define AT91C_PDC_TXTDIS          (0x1 <<  9) // (PDC) Transmitter Transfer Disable

// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler

// *****************************************************************************

// *** Register offset in AT91S_PIO structure ***

#define PIO_PER         ( 0) // PIO Enable Register

#define PIO_PDR         ( 4) // PIO Disable Register

#define PIO_PSR         ( 8) // PIO Status Register

#define PIO_OER         (16) // Output Enable Register

#define PIO_ODR         (20) // Output Disable Registerr

#define PIO_OSR         (24) // Output Status Register

#define PIO_IFER        (32) // Input Filter Enable Register

#define PIO_IFDR        (36) // Input Filter Disable Register

#define PIO_IFSR        (40) // Input Filter Status Register

#define PIO_SODR        (48) // Set Output Data Register

#define PIO_CODR        (52) // Clear Output Data Register

#define PIO_ODSR        (56) // Output Data Status Register

#define PIO_PDSR        (60) // Pin Data Status Register

#define PIO_IER         (64) // Interrupt Enable Register

#define PIO_IDR         (68) // Interrupt Disable Register

#define PIO_IMR         (72) // Interrupt Mask Register

#define PIO_ISR         (76) // Interrupt Status Register

#define PIO_MDER        (80) // Multi-driver Enable Register

#define PIO_MDDR        (84) // Multi-driver Disable Register

#define PIO_MDSR        (88) // Multi-driver Status Register

#define PIO_PPUDR       (96) // Pull-up Disable Register

#define PIO_PPUER       (100) // Pull-up Enable Register

#define PIO_PPUSR       (104) // Pad Pull-up Status Register

#define PIO_ASR         (112) // Select A Register

#define PIO_BSR         (116) // Select B Register

#define PIO_ABSR        (120) // AB Select Status Register

#define PIO_OWER        (160) // Output Write Enable Register

#define PIO_OWDR        (164) // Output Write Disable Register

#define PIO_OWSR        (168) // Output Write Status Register

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Clock Generator Controler

// *****************************************************************************

// *** Register offset in AT91S_CKGR structure ***

#define CKGR_MOR        ( 0) // Main Oscillator Register

#define CKGR_MCFR       ( 4) // Main Clock  Frequency Register

#define CKGR_PLLR       (12) // PLL Register

// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 

#define AT91C_CKGR_MOSCEN         (0x1 <<  0) // (CKGR) Main Oscillator Enable

#define AT91C_CKGR_OSCBYPASS      (0x1 <<  1) // (CKGR) Main Oscillator Bypass

#define AT91C_CKGR_OSCOUNT        (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time

// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 

#define AT91C_CKGR_MAINF          (0xFFFF <<  0) // (CKGR) Main Clock Frequency

#define AT91C_CKGR_MAINRDY        (0x1 << 16) // (CKGR) Main Clock Ready

// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 

#define AT91C_CKGR_DIV            (0xFF <<  0) // (CKGR) Divider Selected

#define         AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0

#define         AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed

#define AT91C_CKGR_PLLCOUNT       (0x3F <<  8) // (CKGR) PLL Counter

#define AT91C_CKGR_OUT            (0x3 << 14) // (CKGR) PLL Output Frequency Range

#define         AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet

#define         AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet

#define         AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet

#define         AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet

#define AT91C_CKGR_MUL            (0x7FF << 16) // (CKGR) PLL Multiplier

#define AT91C_CKGR_USBDIV         (0x3 << 28) // (CKGR) Divider for USB Clocks

#define         AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output

#define         AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2

#define         AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Power Management Controler

// *****************************************************************************

// *** Register offset in AT91S_PMC structure ***

#define PMC_SCER        ( 0) // System Clock Enable Register

#define PMC_SCDR        ( 4) // System Clock Disable Register

#define PMC_SCSR        ( 8) // System Clock Status Register

#define PMC_PCER        (16) // Peripheral Clock Enable Register

#define PMC_PCDR        (20) // Peripheral Clock Disable Register

#define PMC_PCSR        (24) // Peripheral Clock Status Register

#define PMC_MOR         (32) // Main Oscillator Register

#define PMC_MCFR        (36) // Main Clock  Frequency Register

#define PMC_PLLR        (44) // PLL Register

#define PMC_MCKR        (48) // Master Clock Register

#define PMC_PCKR        (64) // Programmable Clock Register

#define PMC_IER         (96) // Interrupt Enable Register

#define PMC_IDR         (100) // Interrupt Disable Register

#define PMC_SR          (104) // Status Register

#define PMC_IMR         (108) // Interrupt Mask Register

// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 

#define AT91C_PMC_PCK             (0x1 <<  0) // (PMC) Processor Clock

#define AT91C_PMC_UDP             (0x1 <<  7) // (PMC) USB Device Port Clock

#define AT91C_PMC_PCK0            (0x1 <<  8) // (PMC) Programmable Clock Output

#define AT91C_PMC_PCK1            (0x1 <<  9) // (PMC) Programmable Clock Output

#define AT91C_PMC_PCK2            (0x1 << 10) // (PMC) Programmable Clock Output

#define AT91C_PMC_PCK3            (0x1 << 11) // (PMC) Programmable Clock Output

// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 

// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 

// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 

// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 

// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 

// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 

#define AT91C_PMC_CSS             (0x3 <<  0) // (PMC) Programmable Clock Selection

#define         AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected

#define         AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected

#define         AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected

#define AT91C_PMC_PRES            (0x7 <<  2) // (PMC) Programmable Clock Prescaler

#define         AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock

#define         AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2

#define         AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4

#define         AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8

#define         AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16

#define         AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32

#define         AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64

// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 

// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 

#define AT91C_PMC_MOSCS           (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask

#define AT91C_PMC_LOCK            (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask

#define AT91C_PMC_MCKRDY          (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK0RDY         (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK1RDY         (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK2RDY         (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask

#define AT91C_PMC_PCK3RDY         (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask

// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 

// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 

// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Reset Controller Interface

// *****************************************************************************

// *** Register offset in AT91S_RSTC structure ***

#define RSTC_RCR        ( 0) // Reset Control Register

#define RSTC_RSR        ( 4) // Reset Status Register

#define RSTC_RMR        ( 8) // Reset Mode Register

// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 

#define AT91C_SYSC_PROCRST        (0x1 <<  0) // (RSTC) Processor Reset

#define AT91C_SYSC_ICERST         (0x1 <<  1) // (RSTC) ICE Interface Reset

#define AT91C_SYSC_PERRST         (0x1 <<  2) // (RSTC) Peripheral Reset

#define AT91C_SYSC_EXTRST         (0x1 <<  3) // (RSTC) External Reset

#define AT91C_SYSC_KEY            (0xFF << 24) // (RSTC) Password

// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 

#define AT91C_SYSC_URSTS          (0x1 <<  0) // (RSTC) User Reset Status

#define AT91C_SYSC_BODSTS         (0x1 <<  1) // (RSTC) Brown-out Detection Status

#define AT91C_SYSC_RSTTYP         (0x7 <<  8) // (RSTC) Reset Type

#define         AT91C_SYSC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.

#define         AT91C_SYSC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.

#define         AT91C_SYSC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.

#define         AT91C_SYSC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.

#define         AT91C_SYSC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brown-out Reset.

#define AT91C_SYSC_NRSTL          (0x1 << 16) // (RSTC) NRST pin level

#define AT91C_SYSC_SRCMP          (0x1 << 17) // (RSTC) Software Reset Command in Progress.

// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 

#define AT91C_SYSC_URSTEN         (0x1 <<  0) // (RSTC) User Reset Enable

#define AT91C_SYSC_URSTIEN        (0x1 <<  4) // (RSTC) User Reset Interrupt Enable

#define AT91C_SYSC_ERSTL          (0xF <<  8) // (RSTC) User Reset Enable

#define AT91C_SYSC_BODIEN         (0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface

// *****************************************************************************

// *** Register offset in AT91S_RTTC structure ***

#define RTTC_RTMR       ( 0) // Real-time Mode Register

#define RTTC_RTAR       ( 4) // Real-time Alarm Register

#define RTTC_RTVR       ( 8) // Real-time Value Register

#define RTTC_RTSR       (12) // Real-time Status Register

// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 

#define AT91C_SYSC_RTPRES         (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value

#define AT91C_SYSC_ALMIEN         (0x1 << 16) // (RTTC) Alarm Interrupt Enable

#define AT91C_SYSC_RTTINCIEN      (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable

#define AT91C_SYSC_RTTRST         (0x1 << 18) // (RTTC) Real Time Timer Restart

// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 

#define AT91C_SYSC_ALMV           (0x0 <<  0) // (RTTC) Alarm Value

// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 

#define AT91C_SYSC_CRTV           (0x0 <<  0) // (RTTC) Current Real-time Value

// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 

#define AT91C_SYSC_ALMS           (0x1 <<  0) // (RTTC) Real-time Alarm Status

#define AT91C_SYSC_RTTINC         (0x1 <<  1) // (RTTC) Real-time Timer Increment

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface

// *****************************************************************************

// *** Register offset in AT91S_PITC structure ***

#define PITC_PIMR       ( 0) // Period Interval Mode Register

#define PITC_PISR       ( 4) // Period Interval Status Register

#define PITC_PIVR       ( 8) // Period Interval Value Register

#define PITC_PIIR       (12) // Period Interval Image Register

// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 

#define AT91C_SYSC_PIV            (0xFFFFF <<  0) // (PITC) Periodic Interval Value

#define AT91C_SYSC_PITEN          (0x1 << 24) // (PITC) Periodic Interval Timer Enabled

#define AT91C_SYSC_PITIEN         (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable

// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 

#define AT91C_SYSC_PITS           (0x1 <<  0) // (PITC) Periodic Interval Timer Status

// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 

#define AT91C_SYSC_CPIV           (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value

#define AT91C_SYSC_PICNT          (0xFFF << 20) // (PITC) Periodic Interval Counter

// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface

// *****************************************************************************

// *** Register offset in AT91S_WDTC structure ***

#define WDTC_WDCR       ( 0) // Watchdog Control Register

#define WDTC_WDMR       ( 4) // Watchdog Mode Register

#define WDTC_WDSR       ( 8) // Watchdog Status Register

// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 

#define AT91C_SYSC_WDRSTT         (0x1 <<  0) // (WDTC) Watchdog Restart

// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 

#define AT91C_SYSC_WDV            (0xFFF <<  0) // (WDTC) Watchdog Timer Restart

#define AT91C_SYSC_WDFIEN         (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable

#define AT91C_SYSC_WDRSTEN        (0x1 << 13) // (WDTC) Watchdog Reset Enable

#define AT91C_SYSC_WDRPROC        (0x1 << 14) // (WDTC) Watchdog Timer Restart

#define AT91C_SYSC_WDDIS          (0x1 << 15) // (WDTC) Watchdog Disable

#define AT91C_SYSC_WDD            (0xFFF << 16) // (WDTC) Watchdog Delta Value

#define AT91C_SYSC_WDDBGHLT       (0x1 << 28) // (WDTC) Watchdog Debug Halt

#define AT91C_SYSC_WDIDLEHLT      (0x1 << 29) // (WDTC) Watchdog Idle Halt

// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 

#define AT91C_SYSC_WDUNF          (0x1 <<  0) // (WDTC) Watchdog Underflow

#define AT91C_SYSC_WDERR          (0x1 <<  1) // (WDTC) Watchdog Error

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Memory Controller Interface

// *****************************************************************************

// *** Register offset in AT91S_MC structure ***

#define MC_RCR          ( 0) // MC Remap Control Register

#define MC_ASR          ( 4) // MC Abort Status Register

#define MC_AASR         ( 8) // MC Abort Address Status Register

#define MC_FMR          (96) // MC Flash Mode Register

#define MC_FCR          (100) // MC Flash Command Register

#define MC_FSR          (104) // MC Flash Status Register

// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 

#define AT91C_MC_RCB              (0x1 <<  0) // (MC) Remap Command Bit

// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 

#define AT91C_MC_UNDADD           (0x1 <<  0) // (MC) Undefined Addess Abort Status

#define AT91C_MC_MISADD           (0x1 <<  1) // (MC) Misaligned Addess Abort Status

#define AT91C_MC_ABTSZ            (0x3 <<  8) // (MC) Abort Size Status

#define         AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte

#define         AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word

#define         AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word

#define AT91C_MC_ABTTYP           (0x3 << 10) // (MC) Abort Type Status

#define         AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read

#define         AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write

#define         AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch

#define AT91C_MC_MST0             (0x1 << 16) // (MC) Master 0 Abort Source

#define AT91C_MC_MST1             (0x1 << 17) // (MC) Master 1 Abort Source

#define AT91C_MC_SVMST0           (0x1 << 24) // (MC) Saved Master 0 Abort Source

#define AT91C_MC_SVMST1           (0x1 << 25) // (MC) Saved Master 1 Abort Source

// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 

#define AT91C_MC_FRDY             (0x1 <<  0) // (MC) Flash Ready

#define AT91C_MC_LOCKE            (0x1 <<  2) // (MC) Lock Error

#define AT91C_MC_PROGE            (0x1 <<  3) // (MC) Programming Error

#define AT91C_MC_NEBP             (0x1 <<  7) // (MC) No Erase Before Programming

#define AT91C_MC_FWS              (0x3 <<  8) // (MC) Flash Wait State

#define         AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations

#define         AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations

#define         AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations

#define         AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations

#define AT91C_MC_FMCN             (0xFF << 16) // (MC) Flash Microsecond Cycle Number

// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 

#define AT91C_MC_FCMD             (0xF <<  0) // (MC) Flash Command

#define         AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.

#define         AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.

#define         AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.

#define         AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.

#define         AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.

#define         AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.

#define         AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.

#define         AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.

#define AT91C_MC_PAGEN            (0x3FF <<  8) // (MC) Page Number

#define AT91C_MC_KEY              (0xFF << 24) // (MC) Writing Protect Key

// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 

#define AT91C_MC_SECURITY         (0x1 <<  4) // (MC) Security Bit Status

#define AT91C_MC_GPNVM0           (0x1 <<  8) // (MC) Sector 0 Lock Status

#define AT91C_MC_GPNVM1           (0x1 <<  9) // (MC) Sector 1 Lock Status

#define AT91C_MC_GPNVM2           (0x1 << 10) // (MC) Sector 2 Lock Status

#define AT91C_MC_GPNVM3           (0x1 << 11) // (MC) Sector 3 Lock Status

#define AT91C_MC_GPNVM4           (0x1 << 12) // (MC) Sector 4 Lock Status

#define AT91C_MC_GPNVM5           (0x1 << 13) // (MC) Sector 5 Lock Status

#define AT91C_MC_GPNVM6           (0x1 << 14) // (MC) Sector 6 Lock Status

#define AT91C_MC_GPNVM7           (0x1 << 15) // (MC) Sector 7 Lock Status

#define AT91C_MC_LOCKS0           (0x1 << 16) // (MC) Sector 0 Lock Status

#define AT91C_MC_LOCKS1           (0x1 << 17) // (MC) Sector 1 Lock Status

#define AT91C_MC_LOCKS2           (0x1 << 18) // (MC) Sector 2 Lock Status

#define AT91C_MC_LOCKS3           (0x1 << 19) // (MC) Sector 3 Lock Status

#define AT91C_MC_LOCKS4           (0x1 << 20) // (MC) Sector 4 Lock Status

#define AT91C_MC_LOCKS5           (0x1 << 21) // (MC) Sector 5 Lock Status

#define AT91C_MC_LOCKS6           (0x1 << 22) // (MC) Sector 6 Lock Status

#define AT91C_MC_LOCKS7           (0x1 << 23) // (MC) Sector 7 Lock Status

#define AT91C_MC_LOCKS8           (0x1 << 24) // (MC) Sector 8 Lock Status

#define AT91C_MC_LOCKS9           (0x1 << 25) // (MC) Sector 9 Lock Status

#define AT91C_MC_LOCKS10          (0x1 << 26) // (MC) Sector 10 Lock Status

#define AT91C_MC_LOCKS11          (0x1 << 27) // (MC) Sector 11 Lock Status

#define AT91C_MC_LOCKS12          (0x1 << 28) // (MC) Sector 12 Lock Status

#define AT91C_MC_LOCKS13          (0x1 << 29) // (MC) Sector 13 Lock Status

#define AT91C_MC_LOCKS14          (0x1 << 30) // (MC) Sector 14 Lock Status

#define AT91C_MC_LOCKS15          (0x1 << 31) // (MC) Sector 15 Lock Status

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface

// *****************************************************************************

// *** Register offset in AT91S_SPI structure ***

#define SPI_CR          ( 0) // Control Register

#define SPI_MR          ( 4) // Mode Register

#define SPI_RDR         ( 8) // Receive Data Register

#define SPI_TDR         (12) // Transmit Data Register

#define SPI_SR          (16) // Status Register

#define SPI_IER         (20) // Interrupt Enable Register

#define SPI_IDR         (24) // Interrupt Disable Register

#define SPI_IMR         (28) // Interrupt Mask Register

#define SPI_CSR         (48) // Chip Select Register

#define SPI_RPR         (256) // Receive Pointer Register

#define SPI_RCR         (260) // Receive Counter Register

#define SPI_TPR         (264) // Transmit Pointer Register

#define SPI_TCR         (268) // Transmit Counter Register

#define SPI_RNPR        (272) // Receive Next Pointer Register

#define SPI_RNCR        (276) // Receive Next Counter Register

#define SPI_TNPR        (280) // Transmit Next Pointer Register

#define SPI_TNCR        (284) // Transmit Next Counter Register

#define SPI_PTCR        (288) // PDC Transfer Control Register

#define SPI_PTSR        (292) // PDC Transfer Status Register

// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 

#define AT91C_SPI_SPIEN           (0x1 <<  0) // (SPI) SPI Enable

#define AT91C_SPI_SPIDIS          (0x1 <<  1) // (SPI) SPI Disable

#define AT91C_SPI_SWRST           (0x1 <<  7) // (SPI) SPI Software reset

#define AT91C_SPI_LASTXFER        (0x1 << 24) // (SPI) SPI Last Transfer

// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 

#define AT91C_SPI_MSTR            (0x1 <<  0) // (SPI) Master/Slave Mode

#define AT91C_SPI_PS              (0x1 <<  1) // (SPI) Peripheral Select

#define         AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select

#define         AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select

#define AT91C_SPI_PCSDEC          (0x1 <<  2) // (SPI) Chip Select Decode

#define AT91C_SPI_FDIV            (0x1 <<  3) // (SPI) Clock Selection

#define AT91C_SPI_MODFDIS         (0x1 <<  4) // (SPI) Mode Fault Detection

#define AT91C_SPI_LLB             (0x1 <<  7) // (SPI) Clock Selection

#define AT91C_SPI_PCS             (0xF << 16) // (SPI) Peripheral Chip Select

#define AT91C_SPI_DLYBCS          (0xFF << 24) // (SPI) Delay Between Chip Selects

// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 

#define AT91C_SPI_RD              (0xFFFF <<  0) // (SPI) Receive Data

#define AT91C_SPI_RPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status

// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 

#define AT91C_SPI_TD              (0xFFFF <<  0) // (SPI) Transmit Data

#define AT91C_SPI_TPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status

// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 

#define AT91C_SPI_RDRF            (0x1 <<  0) // (SPI) Receive Data Register Full

#define AT91C_SPI_TDRE            (0x1 <<  1) // (SPI) Transmit Data Register Empty

#define AT91C_SPI_MODF            (0x1 <<  2) // (SPI) Mode Fault Error

#define AT91C_SPI_OVRES           (0x1 <<  3) // (SPI) Overrun Error Status

#define AT91C_SPI_ENDRX           (0x1 <<  4) // (SPI) End of Receiver Transfer

#define AT91C_SPI_ENDTX           (0x1 <<  5) // (SPI) End of Receiver Transfer

#define AT91C_SPI_RXBUFF          (0x1 <<  6) // (SPI) RXBUFF Interrupt

#define AT91C_SPI_TXBUFE          (0x1 <<  7) // (SPI) TXBUFE Interrupt

#define AT91C_SPI_NSSR            (0x1 <<  8) // (SPI) NSSR Interrupt

#define AT91C_SPI_TXEMPTY         (0x1 <<  9) // (SPI) TXEMPTY Interrupt

#define AT91C_SPI_SPIENS          (0x1 << 16) // (SPI) Enable Status

// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 

// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 

// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 

// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 

#define AT91C_SPI_CPOL            (0x1 <<  0) // (SPI) Clock Polarity

#define AT91C_SPI_NCPHA           (0x1 <<  1) // (SPI) Clock Phase

#define AT91C_SPI_CSAAT           (0x1 <<  2) // (SPI) Chip Select Active After Transfer

#define AT91C_SPI_BITS            (0xF <<  4) // (SPI) Bits Per Transfer

#define         AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer

#define         AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer

#define         AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer

#define         AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer

#define         AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer

#define         AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer

#define         AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer

#define         AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer

#define         AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer

#define AT91C_SPI_SCBR            (0xFF <<  8) // (SPI) Serial Clock Baud Rate

#define AT91C_SPI_DLYBS           (0xFF << 16) // (SPI) Serial Clock Baud Rate

#define AT91C_SPI_DLYBCT          (0xFF << 24) // (SPI) Delay Between Consecutive Transfers

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor

// *****************************************************************************

// *** Register offset in AT91S_ADC structure ***

#define ADC_CR          ( 0) // ADC Control Register

#define ADC_MR          ( 4) // ADC Mode Register

#define ADC_CHER        (16) // ADC Channel Enable Register

#define ADC_CHDR        (20) // ADC Channel Disable Register

#define ADC_CHSR        (24) // ADC Channel Status Register

#define ADC_SR          (28) // ADC Status Register

#define ADC_LCDR        (32) // ADC Last Converted Data Register

#define ADC_IER         (36) // ADC Interrupt Enable Register

#define ADC_IDR         (40) // ADC Interrupt Disable Register

#define ADC_IMR         (44) // ADC Interrupt Mask Register

#define ADC_CDR0        (48) // ADC Channel Data Register 0

#define ADC_CDR1        (52) // ADC Channel Data Register 1

#define ADC_CDR2        (56) // ADC Channel Data Register 2

#define ADC_CDR3        (60) // ADC Channel Data Register 3

#define ADC_CDR4        (64) // ADC Channel Data Register 4

#define ADC_CDR5        (68) // ADC Channel Data Register 5

#define ADC_CDR6        (72) // ADC Channel Data Register 6

#define ADC_CDR7        (76) // ADC Channel Data Register 7

#define ADC_RPR         (256) // Receive Pointer Register

#define ADC_RCR         (260) // Receive Counter Register

#define ADC_TPR         (264) // Transmit Pointer Register

#define ADC_TCR         (268) // Transmit Counter Register

#define ADC_RNPR        (272) // Receive Next Pointer Register

#define ADC_RNCR        (276) // Receive Next Counter Register

#define ADC_TNPR        (280) // Transmit Next Pointer Register

#define ADC_TNCR        (284) // Transmit Next Counter Register

#define ADC_PTCR        (288) // PDC Transfer Control Register

#define ADC_PTSR        (292) // PDC Transfer Status Register

// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 

#define AT91C_ADC_SWRST           (0x1 <<  0) // (ADC) Software Reset

#define AT91C_ADC_START           (0x1 <<  1) // (ADC) Start Conversion

// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 

#define AT91C_ADC_TRGEN           (0x1 <<  0) // (ADC) Trigger Enable

#define         AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software

#define         AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.

#define AT91C_ADC_TRGSEL          (0x7 <<  1) // (ADC) Trigger Selection

#define         AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0

#define         AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1

#define         AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2

#define         AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3

#define         AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4

#define         AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5

#define         AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger

#define AT91C_ADC_LOWRES          (0x1 <<  4) // (ADC) Resolution.

#define         AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution

#define         AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution

#define AT91C_ADC_SLEEP           (0x1 <<  5) // (ADC) Sleep Mode

#define         AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode

#define         AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode

#define AT91C_ADC_PRESCAL         (0x3F <<  8) // (ADC) Prescaler rate selection

#define AT91C_ADC_STARTUP         (0x1F << 16) // (ADC) Startup Time

#define AT91C_ADC_SHTIM           (0xF << 24) // (ADC) Sample & Hold Time

// --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 

#define AT91C_ADC_CH0             (0x1 <<  0) // (ADC) Channel 0

#define AT91C_ADC_CH1             (0x1 <<  1) // (ADC) Channel 1

#define AT91C_ADC_CH2             (0x1 <<  2) // (ADC) Channel 2

#define AT91C_ADC_CH3             (0x1 <<  3) // (ADC) Channel 3

#define AT91C_ADC_CH4             (0x1 <<  4) // (ADC) Channel 4

#define AT91C_ADC_CH5             (0x1 <<  5) // (ADC) Channel 5

#define AT91C_ADC_CH6             (0x1 <<  6) // (ADC) Channel 6

#define AT91C_ADC_CH7             (0x1 <<  7) // (ADC) Channel 7

// --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 

// --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 

// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 

#define AT91C_ADC_EOC0            (0x1 <<  0) // (ADC) End of Conversion

#define AT91C_ADC_EOC1            (0x1 <<  1) // (ADC) End of Conversion

#define AT91C_ADC_EOC2            (0x1 <<  2) // (ADC) End of Conversion

#define AT91C_ADC_EOC3            (0x1 <<  3) // (ADC) End of Conversion

#define AT91C_ADC_EOC4            (0x1 <<  4) // (ADC) End of Conversion

#define AT91C_ADC_EOC5            (0x1 <<  5) // (ADC) End of Conversion

#define AT91C_ADC_EOC6            (0x1 <<  6) // (ADC) End of Conversion

#define AT91C_ADC_EOC7            (0x1 <<  7) // (ADC) End of Conversion

#define AT91C_ADC_OVRE0           (0x1 <<  8) // (ADC) Overrun Error

#define AT91C_ADC_OVRE1           (0x1 <<  9) // (ADC) Overrun Error

#define AT91C_ADC_OVRE2           (0x1 << 10) // (ADC) Overrun Error

#define AT91C_ADC_OVRE3           (0x1 << 11) // (ADC) Overrun Error

#define AT91C_ADC_OVRE4           (0x1 << 12) // (ADC) Overrun Error

#define AT91C_ADC_OVRE5           (0x1 << 13) // (ADC) Overrun Error

#define AT91C_ADC_OVRE6           (0x1 << 14) // (ADC) Overrun Error

#define AT91C_ADC_OVRE7           (0x1 << 15) // (ADC) Overrun Error

#define AT91C_ADC_DRDY            (0x1 << 16) // (ADC) Data Ready

#define AT91C_ADC_GOVRE           (0x1 << 17) // (ADC) General Overrun

#define AT91C_ADC_ENDRX           (0x1 << 18) // (ADC) End of Receiver Transfer

#define AT91C_ADC_RXBUFF          (0x1 << 19) // (ADC) RXBUFF Interrupt

// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 

#define AT91C_ADC_LDATA           (0x3FF <<  0) // (ADC) Last Data Converted

// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 

// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 

// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 

// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 

#define AT91C_ADC_DATA            (0x3FF <<  0) // (ADC) Converted Data

// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 

// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 

// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 

// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 

// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 

// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 

// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 

// *****************************************************************************

//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface

// *****************************************************************************

// *** Register offset in AT91S_SSC structure ***

#define SSC_CR          ( 0) // Control Register

#define SSC_CMR         ( 4) // Clock Mode Register

#define SSC_RCMR        (16) // Receive Clock ModeRegister

#define SSC_RFMR        (20) // Receive Frame Mode Register

#define SSC_TCMR        (24) // Transmit Clock Mode Register

#define SSC_TFMR        (28) // Transmit Frame Mode Register

#define SSC_RHR         (32) // Receive Holding Register

#define SSC_THR         (36) // Transmit Holding Register

#define SSC_RSHR        (48) // Receive Sync Holding Register

#define SSC_TSHR        (52) // Transmit Sync Holding Register

#define SSC_RC0R        (56) // Receive Compare 0 Register

#define SSC_RC1R        (60) // Receive Compare 1 Register

#define SSC_SR          (64) // Status Register

#define SSC_IER         (68) // Interrupt Enable Register

#define SSC_IDR         (72) // Interrupt Disable Register

#define SSC_IMR         (76) // Interrupt Mask Register

#define SSC_RPR         (256) // Receive Pointer Register

#define SSC_RCR         (260) // Receive Counter Register

#define SSC_TPR         (264) // Transmit Pointer Register

#define SSC_TCR         (268) // Transmit Counter Register

#define SSC_RNPR        (272) // Receive Next Pointer Register

#define SSC_RNCR        (276) // Receive Next Counter Register

#define SSC_TNPR        (280) // Transmit Next Pointer Register

#define SSC_TNCR        (284) // Transmit Next Counter Register

#define SSC_PTCR        (288) // PDC Transfer Control Register

#define SSC_PTSR        (292) // PDC Transfer Status Register

// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 

#define AT91C_SSC_RXEN            (0x1 <<  0) // (SSC) Receive Enable

#define AT91C_SSC_RXDIS           (0x1 <<  1) // (SSC) Receive Disable

#define AT91C_SSC_TXEN            (0x1 <<  8) // (SSC) Transmit Enable

#define AT91C_SSC_TXDIS           (0x1 <<  9) // (SSC) Transmit Disable

#define AT91C_SSC_SWRST           (0x1 << 15) // (SSC) Software Reset

// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 

#define AT91C_SSC_CKS             (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection

#define         AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock

#define         AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal

#define         AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin

#define AT91C_SSC_CKO             (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection

#define         AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only

#define         AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output

#define         AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output

#define AT91C_SSC_CKI             (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion

#define AT91C_SSC_CKG             (0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection

#define         AT91C_SSC_CKG_NONE                 (0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock

#define         AT91C_SSC_CKG_LOW                  (0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low

#define         AT91C_SSC_CKG_HIGH                 (0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High

#define AT91C_SSC_START           (0xF <<  8) // (SSC) Receive/Transmit Start Selection

#define         AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.

#define         AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start

#define         AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input

#define         AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input

#define         AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input

#define         AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input

#define         AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input

#define         AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input

#define         AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0

#define AT91C_SSC_STOP            (0x1 << 12) // (SSC) Receive Stop Selection

#define AT91C_SSC_STTOUT          (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection

#define AT91C_SSC_STTDLY          (0xFF << 16) // (SSC) Receive/Transmit Start Delay

#define AT91C_SSC_PERIOD          (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection

// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 

#define AT91C_SSC_DATLEN          (0x1F <<  0) // (SSC) Data Length

#define AT91C_SSC_LOOP            (0x1 <<  5) // (SSC) Loop Mode

#define AT91C_SSC_MSBF            (0x1 <<  7) // (SSC) Most Significant Bit First

#define AT91C_SSC_DATNB           (0xF <<  8) // (SSC) Data Number per Frame

#define AT91C_SSC_FSLEN           (0xF << 16) // (SSC) Receive/Transmit Frame Sync length

#define AT91C_SSC_FSOS            (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection

#define         AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only

#define         AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse

#define         AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse

#define         AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer

#define         AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer

#define         AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer

#define AT91C_SSC_FSEDGE          (0x1 << 24) // (SSC) Frame Sync Edge Detection

// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 

// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 

#define AT91C_SSC_DATDEF          (0x1 <<  5) // (SSC) Data Default Value

#define AT91C_SSC_FSDEN           (0x1 << 23) // (SSC) Frame Sync Data Enable

// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 

#define AT91C_SSC_TXRDY           (0x1 <<  0) // (SSC) Transmit Ready

#define AT91C_SSC_TXEMPTY         (0x1 <<  1) // (SSC) Transmit Empty

#define AT91C_SSC_ENDTX           (0x1 <<  2) // (SSC) End Of Transmission

#define AT91C_SSC_TXBUFE          (0x1 <<  3) // (SSC) Transmit Buffer Empty

#define AT91C_SSC_RXRDY           (0x1 <<  4) // (SSC) Receive Ready

#define AT91C_SSC_OVRUN           (0x1 <<  5) // (SSC) Receive Overrun

#define AT91C_SSC_ENDRX           (0x1 <<  6) // (SSC) End of Reception