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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Source/] [portable/] [IAR/] [AtmelSAM7S64/] [AT91SAM7X256_inc.h] - Blame information for rev 820

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1 572 jeremybenn
//  ----------------------------------------------------------------------------
2
//          ATMEL Microcontroller Software Support  -  ROUSSET  -
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//  ----------------------------------------------------------------------------
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//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
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//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
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//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//  ----------------------------------------------------------------------------
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// File Name           : AT91SAM7X256.h
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// Object              : AT91SAM7X256 definitions
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// Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
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// 
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// CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
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// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
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// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
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// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
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// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
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// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
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// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
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// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
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// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
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// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
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// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
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// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
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// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
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// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
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// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
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// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
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// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
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// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
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// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
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// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
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// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
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// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
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// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
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// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
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// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
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//  ----------------------------------------------------------------------------
45
 
46
// Hardware register definition
47
 
48
// *****************************************************************************
49
//              SOFTWARE API DEFINITION  FOR System Peripherals
50
// *****************************************************************************
51
 
52
// *****************************************************************************
53
//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
54
// *****************************************************************************
55
// *** Register offset in AT91S_AIC structure ***
56
#define AIC_SMR         ( 0) // Source Mode Register
57
#define AIC_SVR         (128) // Source Vector Register
58
#define AIC_IVR         (256) // IRQ Vector Register
59
#define AIC_FVR         (260) // FIQ Vector Register
60
#define AIC_ISR         (264) // Interrupt Status Register
61
#define AIC_IPR         (268) // Interrupt Pending Register
62
#define AIC_IMR         (272) // Interrupt Mask Register
63
#define AIC_CISR        (276) // Core Interrupt Status Register
64
#define AIC_IECR        (288) // Interrupt Enable Command Register
65
#define AIC_IDCR        (292) // Interrupt Disable Command Register
66
#define AIC_ICCR        (296) // Interrupt Clear Command Register
67
#define AIC_ISCR        (300) // Interrupt Set Command Register
68
#define AIC_EOICR       (304) // End of Interrupt Command Register
69
#define AIC_SPU         (308) // Spurious Vector Register
70
#define AIC_DCR         (312) // Debug Control Register (Protect)
71
#define AIC_FFER        (320) // Fast Forcing Enable Register
72
#define AIC_FFDR        (324) // Fast Forcing Disable Register
73
#define AIC_FFSR        (328) // Fast Forcing Status Register
74
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
75
#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level
76
#define         AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
77
#define         AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
78
#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type
79
#define         AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
80
#define         AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
81
#define         AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
82
#define         AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
83
#define         AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
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#define         AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
85
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
86
#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status
87
#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status
88
// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
89
#define AT91C_AIC_DCR_PROT        (0x1 <<  0) // (AIC) Protection Mode
90
#define AT91C_AIC_DCR_GMSK        (0x1 <<  1) // (AIC) General Mask
91
 
92
// *****************************************************************************
93
//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
94
// *****************************************************************************
95
// *** Register offset in AT91S_PDC structure ***
96
#define PDC_RPR         ( 0) // Receive Pointer Register
97
#define PDC_RCR         ( 4) // Receive Counter Register
98
#define PDC_TPR         ( 8) // Transmit Pointer Register
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#define PDC_TCR         (12) // Transmit Counter Register
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#define PDC_RNPR        (16) // Receive Next Pointer Register
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#define PDC_RNCR        (20) // Receive Next Counter Register
102
#define PDC_TNPR        (24) // Transmit Next Pointer Register
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#define PDC_TNCR        (28) // Transmit Next Counter Register
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#define PDC_PTCR        (32) // PDC Transfer Control Register
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#define PDC_PTSR        (36) // PDC Transfer Status Register
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// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
107
#define AT91C_PDC_RXTEN           (0x1 <<  0) // (PDC) Receiver Transfer Enable
108
#define AT91C_PDC_RXTDIS          (0x1 <<  1) // (PDC) Receiver Transfer Disable
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#define AT91C_PDC_TXTEN           (0x1 <<  8) // (PDC) Transmitter Transfer Enable
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#define AT91C_PDC_TXTDIS          (0x1 <<  9) // (PDC) Transmitter Transfer Disable
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// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
112
 
113
// *****************************************************************************
114
//              SOFTWARE API DEFINITION  FOR Debug Unit
115
// *****************************************************************************
116
// *** Register offset in AT91S_DBGU structure ***
117
#define DBGU_CR         ( 0) // Control Register
118
#define DBGU_MR         ( 4) // Mode Register
119
#define DBGU_IER        ( 8) // Interrupt Enable Register
120
#define DBGU_IDR        (12) // Interrupt Disable Register
121
#define DBGU_IMR        (16) // Interrupt Mask Register
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#define DBGU_CSR        (20) // Channel Status Register
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#define DBGU_RHR        (24) // Receiver Holding Register
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#define DBGU_THR        (28) // Transmitter Holding Register
125
#define DBGU_BRGR       (32) // Baud Rate Generator Register
126
#define DBGU_CIDR       (64) // Chip ID Register
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#define DBGU_EXID       (68) // Chip ID Extension Register
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#define DBGU_FNTR       (72) // Force NTRST Register
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#define DBGU_RPR        (256) // Receive Pointer Register
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#define DBGU_RCR        (260) // Receive Counter Register
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#define DBGU_TPR        (264) // Transmit Pointer Register
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#define DBGU_TCR        (268) // Transmit Counter Register
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#define DBGU_RNPR       (272) // Receive Next Pointer Register
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#define DBGU_RNCR       (276) // Receive Next Counter Register
135
#define DBGU_TNPR       (280) // Transmit Next Pointer Register
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#define DBGU_TNCR       (284) // Transmit Next Counter Register
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#define DBGU_PTCR       (288) // PDC Transfer Control Register
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#define DBGU_PTSR       (292) // PDC Transfer Status Register
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// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
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#define AT91C_US_RSTRX            (0x1 <<  2) // (DBGU) Reset Receiver
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#define AT91C_US_RSTTX            (0x1 <<  3) // (DBGU) Reset Transmitter
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#define AT91C_US_RXEN             (0x1 <<  4) // (DBGU) Receiver Enable
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#define AT91C_US_RXDIS            (0x1 <<  5) // (DBGU) Receiver Disable
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#define AT91C_US_TXEN             (0x1 <<  6) // (DBGU) Transmitter Enable
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#define AT91C_US_TXDIS            (0x1 <<  7) // (DBGU) Transmitter Disable
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#define AT91C_US_RSTSTA           (0x1 <<  8) // (DBGU) Reset Status Bits
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// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
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#define AT91C_US_PAR              (0x7 <<  9) // (DBGU) Parity type
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#define         AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
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#define         AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
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#define         AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
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#define         AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
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#define         AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
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#define         AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
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#define AT91C_US_CHMODE           (0x3 << 14) // (DBGU) Channel Mode
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#define         AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
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#define         AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
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#define         AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
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#define         AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
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// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
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#define AT91C_US_RXRDY            (0x1 <<  0) // (DBGU) RXRDY Interrupt
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#define AT91C_US_TXRDY            (0x1 <<  1) // (DBGU) TXRDY Interrupt
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#define AT91C_US_ENDRX            (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
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#define AT91C_US_ENDTX            (0x1 <<  4) // (DBGU) End of Transmit Interrupt
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#define AT91C_US_OVRE             (0x1 <<  5) // (DBGU) Overrun Interrupt
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#define AT91C_US_FRAME            (0x1 <<  6) // (DBGU) Framing Error Interrupt
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#define AT91C_US_PARE             (0x1 <<  7) // (DBGU) Parity Error Interrupt
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#define AT91C_US_TXEMPTY          (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
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#define AT91C_US_TXBUFE           (0x1 << 11) // (DBGU) TXBUFE Interrupt
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#define AT91C_US_RXBUFF           (0x1 << 12) // (DBGU) RXBUFF Interrupt
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#define AT91C_US_COMM_TX          (0x1 << 30) // (DBGU) COMM_TX Interrupt
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#define AT91C_US_COMM_RX          (0x1 << 31) // (DBGU) COMM_RX Interrupt
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// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
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// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
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// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
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// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
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#define AT91C_US_FORCE_NTRST      (0x1 <<  0) // (DBGU) Force NTRST in JTAG
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179
// *****************************************************************************
180
//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
181
// *****************************************************************************
182
// *** Register offset in AT91S_PIO structure ***
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#define PIO_PER         ( 0) // PIO Enable Register
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#define PIO_PDR         ( 4) // PIO Disable Register
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#define PIO_PSR         ( 8) // PIO Status Register
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#define PIO_OER         (16) // Output Enable Register
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#define PIO_ODR         (20) // Output Disable Registerr
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#define PIO_OSR         (24) // Output Status Register
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#define PIO_IFER        (32) // Input Filter Enable Register
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#define PIO_IFDR        (36) // Input Filter Disable Register
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#define PIO_IFSR        (40) // Input Filter Status Register
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#define PIO_SODR        (48) // Set Output Data Register
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#define PIO_CODR        (52) // Clear Output Data Register
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#define PIO_ODSR        (56) // Output Data Status Register
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#define PIO_PDSR        (60) // Pin Data Status Register
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#define PIO_IER         (64) // Interrupt Enable Register
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#define PIO_IDR         (68) // Interrupt Disable Register
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#define PIO_IMR         (72) // Interrupt Mask Register
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#define PIO_ISR         (76) // Interrupt Status Register
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#define PIO_MDER        (80) // Multi-driver Enable Register
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#define PIO_MDDR        (84) // Multi-driver Disable Register
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#define PIO_MDSR        (88) // Multi-driver Status Register
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#define PIO_PPUDR       (96) // Pull-up Disable Register
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#define PIO_PPUER       (100) // Pull-up Enable Register
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#define PIO_PPUSR       (104) // Pull-up Status Register
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#define PIO_ASR         (112) // Select A Register
207
#define PIO_BSR         (116) // Select B Register
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#define PIO_ABSR        (120) // AB Select Status Register
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#define PIO_OWER        (160) // Output Write Enable Register
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#define PIO_OWDR        (164) // Output Write Disable Register
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#define PIO_OWSR        (168) // Output Write Status Register
212
 
213
// *****************************************************************************
214
//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
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// *****************************************************************************
216
// *** Register offset in AT91S_CKGR structure ***
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#define CKGR_MOR        ( 0) // Main Oscillator Register
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#define CKGR_MCFR       ( 4) // Main Clock  Frequency Register
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#define CKGR_PLLR       (12) // PLL Register
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// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
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#define AT91C_CKGR_MOSCEN         (0x1 <<  0) // (CKGR) Main Oscillator Enable
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#define AT91C_CKGR_OSCBYPASS      (0x1 <<  1) // (CKGR) Main Oscillator Bypass
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#define AT91C_CKGR_OSCOUNT        (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
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// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
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#define AT91C_CKGR_MAINF          (0xFFFF <<  0) // (CKGR) Main Clock Frequency
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#define AT91C_CKGR_MAINRDY        (0x1 << 16) // (CKGR) Main Clock Ready
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// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
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#define AT91C_CKGR_DIV            (0xFF <<  0) // (CKGR) Divider Selected
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#define         AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
230
#define         AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
231
#define AT91C_CKGR_PLLCOUNT       (0x3F <<  8) // (CKGR) PLL Counter
232
#define AT91C_CKGR_OUT            (0x3 << 14) // (CKGR) PLL Output Frequency Range
233
#define         AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
234
#define         AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
235
#define         AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
236
#define         AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
237
#define AT91C_CKGR_MUL            (0x7FF << 16) // (CKGR) PLL Multiplier
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#define AT91C_CKGR_USBDIV         (0x3 << 28) // (CKGR) Divider for USB Clocks
239
#define         AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
240
#define         AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
241
#define         AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
242
 
243
// *****************************************************************************
244
//              SOFTWARE API DEFINITION  FOR Power Management Controler
245
// *****************************************************************************
246
// *** Register offset in AT91S_PMC structure ***
247
#define PMC_SCER        ( 0) // System Clock Enable Register
248
#define PMC_SCDR        ( 4) // System Clock Disable Register
249
#define PMC_SCSR        ( 8) // System Clock Status Register
250
#define PMC_PCER        (16) // Peripheral Clock Enable Register
251
#define PMC_PCDR        (20) // Peripheral Clock Disable Register
252
#define PMC_PCSR        (24) // Peripheral Clock Status Register
253
#define PMC_MOR         (32) // Main Oscillator Register
254
#define PMC_MCFR        (36) // Main Clock  Frequency Register
255
#define PMC_PLLR        (44) // PLL Register
256
#define PMC_MCKR        (48) // Master Clock Register
257
#define PMC_PCKR        (64) // Programmable Clock Register
258
#define PMC_IER         (96) // Interrupt Enable Register
259
#define PMC_IDR         (100) // Interrupt Disable Register
260
#define PMC_SR          (104) // Status Register
261
#define PMC_IMR         (108) // Interrupt Mask Register
262
// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
263
#define AT91C_PMC_PCK             (0x1 <<  0) // (PMC) Processor Clock
264
#define AT91C_PMC_UDP             (0x1 <<  7) // (PMC) USB Device Port Clock
265
#define AT91C_PMC_PCK0            (0x1 <<  8) // (PMC) Programmable Clock Output
266
#define AT91C_PMC_PCK1            (0x1 <<  9) // (PMC) Programmable Clock Output
267
#define AT91C_PMC_PCK2            (0x1 << 10) // (PMC) Programmable Clock Output
268
#define AT91C_PMC_PCK3            (0x1 << 11) // (PMC) Programmable Clock Output
269
// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
270
// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
271
// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
272
// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
273
// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
274
// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
275
#define AT91C_PMC_CSS             (0x3 <<  0) // (PMC) Programmable Clock Selection
276
#define         AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
277
#define         AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
278
#define         AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
279
#define AT91C_PMC_PRES            (0x7 <<  2) // (PMC) Programmable Clock Prescaler
280
#define         AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
281
#define         AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
282
#define         AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
283
#define         AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
284
#define         AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
285
#define         AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
286
#define         AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
287
// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
288
// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
289
#define AT91C_PMC_MOSCS           (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
290
#define AT91C_PMC_LOCK            (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
291
#define AT91C_PMC_MCKRDY          (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
292
#define AT91C_PMC_PCK0RDY         (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
293
#define AT91C_PMC_PCK1RDY         (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
294
#define AT91C_PMC_PCK2RDY         (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
295
#define AT91C_PMC_PCK3RDY         (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
296
// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
297
// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
298
// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
299
 
300
// *****************************************************************************
301
//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
302
// *****************************************************************************
303
// *** Register offset in AT91S_RSTC structure ***
304
#define RSTC_RCR        ( 0) // Reset Control Register
305
#define RSTC_RSR        ( 4) // Reset Status Register
306
#define RSTC_RMR        ( 8) // Reset Mode Register
307
// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
308
#define AT91C_RSTC_PROCRST        (0x1 <<  0) // (RSTC) Processor Reset
309
#define AT91C_RSTC_PERRST         (0x1 <<  2) // (RSTC) Peripheral Reset
310
#define AT91C_RSTC_EXTRST         (0x1 <<  3) // (RSTC) External Reset
311
#define AT91C_RSTC_KEY            (0xFF << 24) // (RSTC) Password
312
// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
313
#define AT91C_RSTC_URSTS          (0x1 <<  0) // (RSTC) User Reset Status
314
#define AT91C_RSTC_BODSTS         (0x1 <<  1) // (RSTC) Brownout Detection Status
315
#define AT91C_RSTC_RSTTYP         (0x7 <<  8) // (RSTC) Reset Type
316
#define         AT91C_RSTC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
317
#define         AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
318
#define         AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
319
#define         AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
320
#define         AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
321
#define         AT91C_RSTC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brownout Reset occured.
322
#define AT91C_RSTC_NRSTL          (0x1 << 16) // (RSTC) NRST pin level
323
#define AT91C_RSTC_SRCMP          (0x1 << 17) // (RSTC) Software Reset Command in Progress.
324
// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
325
#define AT91C_RSTC_URSTEN         (0x1 <<  0) // (RSTC) User Reset Enable
326
#define AT91C_RSTC_URSTIEN        (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
327
#define AT91C_RSTC_ERSTL          (0xF <<  8) // (RSTC) User Reset Enable
328
#define AT91C_RSTC_BODIEN         (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
329
 
330
// *****************************************************************************
331
//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
332
// *****************************************************************************
333
// *** Register offset in AT91S_RTTC structure ***
334
#define RTTC_RTMR       ( 0) // Real-time Mode Register
335
#define RTTC_RTAR       ( 4) // Real-time Alarm Register
336
#define RTTC_RTVR       ( 8) // Real-time Value Register
337
#define RTTC_RTSR       (12) // Real-time Status Register
338
// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
339
#define AT91C_RTTC_RTPRES         (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
340
#define AT91C_RTTC_ALMIEN         (0x1 << 16) // (RTTC) Alarm Interrupt Enable
341
#define AT91C_RTTC_RTTINCIEN      (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
342
#define AT91C_RTTC_RTTRST         (0x1 << 18) // (RTTC) Real Time Timer Restart
343
// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
344
#define AT91C_RTTC_ALMV           (0x0 <<  0) // (RTTC) Alarm Value
345
// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
346
#define AT91C_RTTC_CRTV           (0x0 <<  0) // (RTTC) Current Real-time Value
347
// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
348
#define AT91C_RTTC_ALMS           (0x1 <<  0) // (RTTC) Real-time Alarm Status
349
#define AT91C_RTTC_RTTINC         (0x1 <<  1) // (RTTC) Real-time Timer Increment
350
 
351
// *****************************************************************************
352
//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
353
// *****************************************************************************
354
// *** Register offset in AT91S_PITC structure ***
355
#define PITC_PIMR       ( 0) // Period Interval Mode Register
356
#define PITC_PISR       ( 4) // Period Interval Status Register
357
#define PITC_PIVR       ( 8) // Period Interval Value Register
358
#define PITC_PIIR       (12) // Period Interval Image Register
359
// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
360
#define AT91C_PITC_PIV            (0xFFFFF <<  0) // (PITC) Periodic Interval Value
361
#define AT91C_PITC_PITEN          (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
362
#define AT91C_PITC_PITIEN         (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
363
// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
364
#define AT91C_PITC_PITS           (0x1 <<  0) // (PITC) Periodic Interval Timer Status
365
// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
366
#define AT91C_PITC_CPIV           (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
367
#define AT91C_PITC_PICNT          (0xFFF << 20) // (PITC) Periodic Interval Counter
368
// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
369
 
370
// *****************************************************************************
371
//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
372
// *****************************************************************************
373
// *** Register offset in AT91S_WDTC structure ***
374
#define WDTC_WDCR       ( 0) // Watchdog Control Register
375
#define WDTC_WDMR       ( 4) // Watchdog Mode Register
376
#define WDTC_WDSR       ( 8) // Watchdog Status Register
377
// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
378
#define AT91C_WDTC_WDRSTT         (0x1 <<  0) // (WDTC) Watchdog Restart
379
#define AT91C_WDTC_KEY            (0xFF << 24) // (WDTC) Watchdog KEY Password
380
// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
381
#define AT91C_WDTC_WDV            (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
382
#define AT91C_WDTC_WDFIEN         (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
383
#define AT91C_WDTC_WDRSTEN        (0x1 << 13) // (WDTC) Watchdog Reset Enable
384
#define AT91C_WDTC_WDRPROC        (0x1 << 14) // (WDTC) Watchdog Timer Restart
385
#define AT91C_WDTC_WDDIS          (0x1 << 15) // (WDTC) Watchdog Disable
386
#define AT91C_WDTC_WDD            (0xFFF << 16) // (WDTC) Watchdog Delta Value
387
#define AT91C_WDTC_WDDBGHLT       (0x1 << 28) // (WDTC) Watchdog Debug Halt
388
#define AT91C_WDTC_WDIDLEHLT      (0x1 << 29) // (WDTC) Watchdog Idle Halt
389
// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
390
#define AT91C_WDTC_WDUNF          (0x1 <<  0) // (WDTC) Watchdog Underflow
391
#define AT91C_WDTC_WDERR          (0x1 <<  1) // (WDTC) Watchdog Error
392
 
393
// *****************************************************************************
394
//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
395
// *****************************************************************************
396
// *** Register offset in AT91S_VREG structure ***
397
#define VREG_MR         ( 0) // Voltage Regulator Mode Register
398
// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
399
#define AT91C_VREG_PSTDBY         (0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
400
 
401
// *****************************************************************************
402
//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
403
// *****************************************************************************
404
// *** Register offset in AT91S_MC structure ***
405
#define MC_RCR          ( 0) // MC Remap Control Register
406
#define MC_ASR          ( 4) // MC Abort Status Register
407
#define MC_AASR         ( 8) // MC Abort Address Status Register
408
#define MC_FMR          (96) // MC Flash Mode Register
409
#define MC_FCR          (100) // MC Flash Command Register
410
#define MC_FSR          (104) // MC Flash Status Register
411
// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
412
#define AT91C_MC_RCB              (0x1 <<  0) // (MC) Remap Command Bit
413
// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
414
#define AT91C_MC_UNDADD           (0x1 <<  0) // (MC) Undefined Addess Abort Status
415
#define AT91C_MC_MISADD           (0x1 <<  1) // (MC) Misaligned Addess Abort Status
416
#define AT91C_MC_ABTSZ            (0x3 <<  8) // (MC) Abort Size Status
417
#define         AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
418
#define         AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
419
#define         AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
420
#define AT91C_MC_ABTTYP           (0x3 << 10) // (MC) Abort Type Status
421
#define         AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
422
#define         AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
423
#define         AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
424
#define AT91C_MC_MST0             (0x1 << 16) // (MC) Master 0 Abort Source
425
#define AT91C_MC_MST1             (0x1 << 17) // (MC) Master 1 Abort Source
426
#define AT91C_MC_SVMST0           (0x1 << 24) // (MC) Saved Master 0 Abort Source
427
#define AT91C_MC_SVMST1           (0x1 << 25) // (MC) Saved Master 1 Abort Source
428
// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
429
#define AT91C_MC_FRDY             (0x1 <<  0) // (MC) Flash Ready
430
#define AT91C_MC_LOCKE            (0x1 <<  2) // (MC) Lock Error
431
#define AT91C_MC_PROGE            (0x1 <<  3) // (MC) Programming Error
432
#define AT91C_MC_NEBP             (0x1 <<  7) // (MC) No Erase Before Programming
433
#define AT91C_MC_FWS              (0x3 <<  8) // (MC) Flash Wait State
434
#define         AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
435
#define         AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
436
#define         AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
437
#define         AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
438
#define AT91C_MC_FMCN             (0xFF << 16) // (MC) Flash Microsecond Cycle Number
439
// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
440
#define AT91C_MC_FCMD             (0xF <<  0) // (MC) Flash Command
441
#define         AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
442
#define         AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
443
#define         AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
444
#define         AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
445
#define         AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
446
#define         AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.
447
#define         AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.
448
#define         AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.
449
#define AT91C_MC_PAGEN            (0x3FF <<  8) // (MC) Page Number
450
#define AT91C_MC_KEY              (0xFF << 24) // (MC) Writing Protect Key
451
// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
452
#define AT91C_MC_SECURITY         (0x1 <<  4) // (MC) Security Bit Status
453
#define AT91C_MC_GPNVM0           (0x1 <<  8) // (MC) Sector 0 Lock Status
454
#define AT91C_MC_GPNVM1           (0x1 <<  9) // (MC) Sector 1 Lock Status
455
#define AT91C_MC_GPNVM2           (0x1 << 10) // (MC) Sector 2 Lock Status
456
#define AT91C_MC_GPNVM3           (0x1 << 11) // (MC) Sector 3 Lock Status
457
#define AT91C_MC_GPNVM4           (0x1 << 12) // (MC) Sector 4 Lock Status
458
#define AT91C_MC_GPNVM5           (0x1 << 13) // (MC) Sector 5 Lock Status
459
#define AT91C_MC_GPNVM6           (0x1 << 14) // (MC) Sector 6 Lock Status
460
#define AT91C_MC_GPNVM7           (0x1 << 15) // (MC) Sector 7 Lock Status
461
#define AT91C_MC_LOCKS0           (0x1 << 16) // (MC) Sector 0 Lock Status
462
#define AT91C_MC_LOCKS1           (0x1 << 17) // (MC) Sector 1 Lock Status
463
#define AT91C_MC_LOCKS2           (0x1 << 18) // (MC) Sector 2 Lock Status
464
#define AT91C_MC_LOCKS3           (0x1 << 19) // (MC) Sector 3 Lock Status
465
#define AT91C_MC_LOCKS4           (0x1 << 20) // (MC) Sector 4 Lock Status
466
#define AT91C_MC_LOCKS5           (0x1 << 21) // (MC) Sector 5 Lock Status
467
#define AT91C_MC_LOCKS6           (0x1 << 22) // (MC) Sector 6 Lock Status
468
#define AT91C_MC_LOCKS7           (0x1 << 23) // (MC) Sector 7 Lock Status
469
#define AT91C_MC_LOCKS8           (0x1 << 24) // (MC) Sector 8 Lock Status
470
#define AT91C_MC_LOCKS9           (0x1 << 25) // (MC) Sector 9 Lock Status
471
#define AT91C_MC_LOCKS10          (0x1 << 26) // (MC) Sector 10 Lock Status
472
#define AT91C_MC_LOCKS11          (0x1 << 27) // (MC) Sector 11 Lock Status
473
#define AT91C_MC_LOCKS12          (0x1 << 28) // (MC) Sector 12 Lock Status
474
#define AT91C_MC_LOCKS13          (0x1 << 29) // (MC) Sector 13 Lock Status
475
#define AT91C_MC_LOCKS14          (0x1 << 30) // (MC) Sector 14 Lock Status
476
#define AT91C_MC_LOCKS15          (0x1 << 31) // (MC) Sector 15 Lock Status
477
 
478
// *****************************************************************************
479
//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
480
// *****************************************************************************
481
// *** Register offset in AT91S_SPI structure ***
482
#define SPI_CR          ( 0) // Control Register
483
#define SPI_MR          ( 4) // Mode Register
484
#define SPI_RDR         ( 8) // Receive Data Register
485
#define SPI_TDR         (12) // Transmit Data Register
486
#define SPI_SR          (16) // Status Register
487
#define SPI_IER         (20) // Interrupt Enable Register
488
#define SPI_IDR         (24) // Interrupt Disable Register
489
#define SPI_IMR         (28) // Interrupt Mask Register
490
#define SPI_CSR         (48) // Chip Select Register
491
#define SPI_RPR         (256) // Receive Pointer Register
492
#define SPI_RCR         (260) // Receive Counter Register
493
#define SPI_TPR         (264) // Transmit Pointer Register
494
#define SPI_TCR         (268) // Transmit Counter Register
495
#define SPI_RNPR        (272) // Receive Next Pointer Register
496
#define SPI_RNCR        (276) // Receive Next Counter Register
497
#define SPI_TNPR        (280) // Transmit Next Pointer Register
498
#define SPI_TNCR        (284) // Transmit Next Counter Register
499
#define SPI_PTCR        (288) // PDC Transfer Control Register
500
#define SPI_PTSR        (292) // PDC Transfer Status Register
501
// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
502
#define AT91C_SPI_SPIEN           (0x1 <<  0) // (SPI) SPI Enable
503
#define AT91C_SPI_SPIDIS          (0x1 <<  1) // (SPI) SPI Disable
504
#define AT91C_SPI_SWRST           (0x1 <<  7) // (SPI) SPI Software reset
505
#define AT91C_SPI_LASTXFER        (0x1 << 24) // (SPI) SPI Last Transfer
506
// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
507
#define AT91C_SPI_MSTR            (0x1 <<  0) // (SPI) Master/Slave Mode
508
#define AT91C_SPI_PS              (0x1 <<  1) // (SPI) Peripheral Select
509
#define         AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
510
#define         AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
511
#define AT91C_SPI_PCSDEC          (0x1 <<  2) // (SPI) Chip Select Decode
512
#define AT91C_SPI_FDIV            (0x1 <<  3) // (SPI) Clock Selection
513
#define AT91C_SPI_MODFDIS         (0x1 <<  4) // (SPI) Mode Fault Detection
514
#define AT91C_SPI_LLB             (0x1 <<  7) // (SPI) Clock Selection
515
#define AT91C_SPI_PCS             (0xF << 16) // (SPI) Peripheral Chip Select
516
#define AT91C_SPI_DLYBCS          (0xFF << 24) // (SPI) Delay Between Chip Selects
517
// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
518
#define AT91C_SPI_RD              (0xFFFF <<  0) // (SPI) Receive Data
519
#define AT91C_SPI_RPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
520
// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
521
#define AT91C_SPI_TD              (0xFFFF <<  0) // (SPI) Transmit Data
522
#define AT91C_SPI_TPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
523
// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
524
#define AT91C_SPI_RDRF            (0x1 <<  0) // (SPI) Receive Data Register Full
525
#define AT91C_SPI_TDRE            (0x1 <<  1) // (SPI) Transmit Data Register Empty
526
#define AT91C_SPI_MODF            (0x1 <<  2) // (SPI) Mode Fault Error
527
#define AT91C_SPI_OVRES           (0x1 <<  3) // (SPI) Overrun Error Status
528
#define AT91C_SPI_ENDRX           (0x1 <<  4) // (SPI) End of Receiver Transfer
529
#define AT91C_SPI_ENDTX           (0x1 <<  5) // (SPI) End of Receiver Transfer
530
#define AT91C_SPI_RXBUFF          (0x1 <<  6) // (SPI) RXBUFF Interrupt
531
#define AT91C_SPI_TXBUFE          (0x1 <<  7) // (SPI) TXBUFE Interrupt
532
#define AT91C_SPI_NSSR            (0x1 <<  8) // (SPI) NSSR Interrupt
533
#define AT91C_SPI_TXEMPTY         (0x1 <<  9) // (SPI) TXEMPTY Interrupt
534
#define AT91C_SPI_SPIENS          (0x1 << 16) // (SPI) Enable Status
535
// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
536
// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
537
// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
538
// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
539
#define AT91C_SPI_CPOL            (0x1 <<  0) // (SPI) Clock Polarity
540
#define AT91C_SPI_NCPHA           (0x1 <<  1) // (SPI) Clock Phase
541
#define AT91C_SPI_CSAAT           (0x1 <<  3) // (SPI) Chip Select Active After Transfer
542
#define AT91C_SPI_BITS            (0xF <<  4) // (SPI) Bits Per Transfer
543
#define         AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
544
#define         AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
545
#define         AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
546
#define         AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
547
#define         AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
548
#define         AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
549
#define         AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
550
#define         AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
551
#define         AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
552
#define AT91C_SPI_SCBR            (0xFF <<  8) // (SPI) Serial Clock Baud Rate
553
#define AT91C_SPI_DLYBS           (0xFF << 16) // (SPI) Delay Before SPCK
554
#define AT91C_SPI_DLYBCT          (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
555
 
556
// *****************************************************************************
557
//              SOFTWARE API DEFINITION  FOR Usart
558
// *****************************************************************************
559
// *** Register offset in AT91S_USART structure ***
560
#define US_CR           ( 0) // Control Register
561
#define US_MR           ( 4) // Mode Register
562
#define US_IER          ( 8) // Interrupt Enable Register
563
#define US_IDR          (12) // Interrupt Disable Register
564
#define US_IMR          (16) // Interrupt Mask Register
565
#define US_CSR          (20) // Channel Status Register
566
#define US_RHR          (24) // Receiver Holding Register
567
#define US_THR          (28) // Transmitter Holding Register
568
#define US_BRGR         (32) // Baud Rate Generator Register
569
#define US_RTOR         (36) // Receiver Time-out Register
570
#define US_TTGR         (40) // Transmitter Time-guard Register
571
#define US_FIDI         (64) // FI_DI_Ratio Register
572
#define US_NER          (68) // Nb Errors Register
573
#define US_IF           (76) // IRDA_FILTER Register
574
#define US_RPR          (256) // Receive Pointer Register
575
#define US_RCR          (260) // Receive Counter Register
576
#define US_TPR          (264) // Transmit Pointer Register
577
#define US_TCR          (268) // Transmit Counter Register
578
#define US_RNPR         (272) // Receive Next Pointer Register
579
#define US_RNCR         (276) // Receive Next Counter Register
580
#define US_TNPR         (280) // Transmit Next Pointer Register
581
#define US_TNCR         (284) // Transmit Next Counter Register
582
#define US_PTCR         (288) // PDC Transfer Control Register
583
#define US_PTSR         (292) // PDC Transfer Status Register
584
// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
585
#define AT91C_US_STTBRK           (0x1 <<  9) // (USART) Start Break
586
#define AT91C_US_STPBRK           (0x1 << 10) // (USART) Stop Break
587
#define AT91C_US_STTTO            (0x1 << 11) // (USART) Start Time-out
588
#define AT91C_US_SENDA            (0x1 << 12) // (USART) Send Address
589
#define AT91C_US_RSTIT            (0x1 << 13) // (USART) Reset Iterations
590
#define AT91C_US_RSTNACK          (0x1 << 14) // (USART) Reset Non Acknowledge
591
#define AT91C_US_RETTO            (0x1 << 15) // (USART) Rearm Time-out
592
#define AT91C_US_DTREN            (0x1 << 16) // (USART) Data Terminal ready Enable
593
#define AT91C_US_DTRDIS           (0x1 << 17) // (USART) Data Terminal ready Disable
594
#define AT91C_US_RTSEN            (0x1 << 18) // (USART) Request to Send enable
595
#define AT91C_US_RTSDIS           (0x1 << 19) // (USART) Request to Send Disable
596
// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
597
#define AT91C_US_USMODE           (0xF <<  0) // (USART) Usart mode
598
#define         AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
599
#define         AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
600
#define         AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
601
#define         AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
602
#define         AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
603
#define         AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
604
#define         AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
605
#define         AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
606
#define AT91C_US_CLKS             (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
607
#define         AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
608
#define         AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
609
#define         AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
610
#define         AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
611
#define AT91C_US_CHRL             (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
612
#define         AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
613
#define         AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
614
#define         AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
615
#define         AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
616
#define AT91C_US_SYNC             (0x1 <<  8) // (USART) Synchronous Mode Select
617
#define AT91C_US_NBSTOP           (0x3 << 12) // (USART) Number of Stop bits
618
#define         AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
619
#define         AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
620
#define         AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
621
#define AT91C_US_MSBF             (0x1 << 16) // (USART) Bit Order
622
#define AT91C_US_MODE9            (0x1 << 17) // (USART) 9-bit Character length
623
#define AT91C_US_CKLO             (0x1 << 18) // (USART) Clock Output Select
624
#define AT91C_US_OVER             (0x1 << 19) // (USART) Over Sampling Mode
625
#define AT91C_US_INACK            (0x1 << 20) // (USART) Inhibit Non Acknowledge
626
#define AT91C_US_DSNACK           (0x1 << 21) // (USART) Disable Successive NACK
627
#define AT91C_US_MAX_ITER         (0x1 << 24) // (USART) Number of Repetitions
628
#define AT91C_US_FILTER           (0x1 << 28) // (USART) Receive Line Filter
629
// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
630
#define AT91C_US_RXBRK            (0x1 <<  2) // (USART) Break Received/End of Break
631
#define AT91C_US_TIMEOUT          (0x1 <<  8) // (USART) Receiver Time-out
632
#define AT91C_US_ITERATION        (0x1 << 10) // (USART) Max number of Repetitions Reached
633
#define AT91C_US_NACK             (0x1 << 13) // (USART) Non Acknowledge
634
#define AT91C_US_RIIC             (0x1 << 16) // (USART) Ring INdicator Input Change Flag
635
#define AT91C_US_DSRIC            (0x1 << 17) // (USART) Data Set Ready Input Change Flag
636
#define AT91C_US_DCDIC            (0x1 << 18) // (USART) Data Carrier Flag
637
#define AT91C_US_CTSIC            (0x1 << 19) // (USART) Clear To Send Input Change Flag
638
// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
639
// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
640
// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
641
#define AT91C_US_RI               (0x1 << 20) // (USART) Image of RI Input
642
#define AT91C_US_DSR              (0x1 << 21) // (USART) Image of DSR Input
643
#define AT91C_US_DCD              (0x1 << 22) // (USART) Image of DCD Input
644
#define AT91C_US_CTS              (0x1 << 23) // (USART) Image of CTS Input
645
 
646
// *****************************************************************************
647
//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
648
// *****************************************************************************
649
// *** Register offset in AT91S_SSC structure ***
650
#define SSC_CR          ( 0) // Control Register
651
#define SSC_CMR         ( 4) // Clock Mode Register
652
#define SSC_RCMR        (16) // Receive Clock ModeRegister
653
#define SSC_RFMR        (20) // Receive Frame Mode Register
654
#define SSC_TCMR        (24) // Transmit Clock Mode Register
655
#define SSC_TFMR        (28) // Transmit Frame Mode Register
656
#define SSC_RHR         (32) // Receive Holding Register
657
#define SSC_THR         (36) // Transmit Holding Register
658
#define SSC_RSHR        (48) // Receive Sync Holding Register
659
#define SSC_TSHR        (52) // Transmit Sync Holding Register
660
#define SSC_SR          (64) // Status Register
661
#define SSC_IER         (68) // Interrupt Enable Register
662
#define SSC_IDR         (72) // Interrupt Disable Register
663
#define SSC_IMR         (76) // Interrupt Mask Register
664
#define SSC_RPR         (256) // Receive Pointer Register
665
#define SSC_RCR         (260) // Receive Counter Register
666
#define SSC_TPR         (264) // Transmit Pointer Register
667
#define SSC_TCR         (268) // Transmit Counter Register
668
#define SSC_RNPR        (272) // Receive Next Pointer Register
669
#define SSC_RNCR        (276) // Receive Next Counter Register
670
#define SSC_TNPR        (280) // Transmit Next Pointer Register
671
#define SSC_TNCR        (284) // Transmit Next Counter Register
672
#define SSC_PTCR        (288) // PDC Transfer Control Register
673
#define SSC_PTSR        (292) // PDC Transfer Status Register
674
// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
675
#define AT91C_SSC_RXEN            (0x1 <<  0) // (SSC) Receive Enable
676
#define AT91C_SSC_RXDIS           (0x1 <<  1) // (SSC) Receive Disable
677
#define AT91C_SSC_TXEN            (0x1 <<  8) // (SSC) Transmit Enable
678
#define AT91C_SSC_TXDIS           (0x1 <<  9) // (SSC) Transmit Disable
679
#define AT91C_SSC_SWRST           (0x1 << 15) // (SSC) Software Reset
680
// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
681
#define AT91C_SSC_CKS             (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
682
#define         AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
683
#define         AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
684
#define         AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
685
#define AT91C_SSC_CKO             (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
686
#define         AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
687
#define         AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
688
#define         AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
689
#define AT91C_SSC_CKI             (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
690
#define AT91C_SSC_START           (0xF <<  8) // (SSC) Receive/Transmit Start Selection
691
#define         AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
692
#define         AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
693
#define         AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
694
#define         AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
695
#define         AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
696
#define         AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
697
#define         AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
698
#define         AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
699
#define         AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
700
#define AT91C_SSC_STTDLY          (0xFF << 16) // (SSC) Receive/Transmit Start Delay
701
#define AT91C_SSC_PERIOD          (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
702
// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
703
#define AT91C_SSC_DATLEN          (0x1F <<  0) // (SSC) Data Length
704
#define AT91C_SSC_LOOP            (0x1 <<  5) // (SSC) Loop Mode
705
#define AT91C_SSC_MSBF            (0x1 <<  7) // (SSC) Most Significant Bit First
706
#define AT91C_SSC_DATNB           (0xF <<  8) // (SSC) Data Number per Frame
707
#define AT91C_SSC_FSLEN           (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
708
#define AT91C_SSC_FSOS            (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
709
#define         AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
710
#define         AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
711
#define         AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
712
#define         AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
713
#define         AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
714
#define         AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
715
#define AT91C_SSC_FSEDGE          (0x1 << 24) // (SSC) Frame Sync Edge Detection
716
// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
717
// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
718
#define AT91C_SSC_DATDEF          (0x1 <<  5) // (SSC) Data Default Value
719
#define AT91C_SSC_FSDEN           (0x1 << 23) // (SSC) Frame Sync Data Enable
720
// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
721
#define AT91C_SSC_TXRDY           (0x1 <<  0) // (SSC) Transmit Ready
722
#define AT91C_SSC_TXEMPTY         (0x1 <<  1) // (SSC) Transmit Empty
723
#define AT91C_SSC_ENDTX           (0x1 <<  2) // (SSC) End Of Transmission
724
#define AT91C_SSC_TXBUFE          (0x1 <<  3) // (SSC) Transmit Buffer Empty
725
#define AT91C_SSC_RXRDY           (0x1 <<  4) // (SSC) Receive Ready
726
#define AT91C_SSC_OVRUN           (0x1 <<  5) // (SSC) Receive Overrun
727
#define AT91C_SSC_ENDRX           (0x1 <<  6) // (SSC) End of Reception
728
#define AT91C_SSC_RXBUFF          (0x1 <<  7) // (SSC) Receive Buffer Full
729
#define AT91C_SSC_TXSYN           (0x1 << 10) // (SSC) Transmit Sync
730
#define AT91C_SSC_RXSYN           (0x1 << 11) // (SSC) Receive Sync
731
#define AT91C_SSC_TXENA           (0x1 << 16) // (SSC) Transmit Enable
732
#define AT91C_SSC_RXENA           (0x1 << 17) // (SSC) Receive Enable
733
// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
734
// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
735
// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
736
 
737
// *****************************************************************************
738
//              SOFTWARE API DEFINITION  FOR Two-wire Interface
739
// *****************************************************************************
740
// *** Register offset in AT91S_TWI structure ***
741
#define TWI_CR          ( 0) // Control Register
742
#define TWI_MMR         ( 4) // Master Mode Register
743
#define TWI_IADR        (12) // Internal Address Register
744
#define TWI_CWGR        (16) // Clock Waveform Generator Register
745
#define TWI_SR          (32) // Status Register
746
#define TWI_IER         (36) // Interrupt Enable Register
747
#define TWI_IDR         (40) // Interrupt Disable Register
748
#define TWI_IMR         (44) // Interrupt Mask Register
749
#define TWI_RHR         (48) // Receive Holding Register
750
#define TWI_THR         (52) // Transmit Holding Register
751
// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
752
#define AT91C_TWI_START           (0x1 <<  0) // (TWI) Send a START Condition
753
#define AT91C_TWI_STOP            (0x1 <<  1) // (TWI) Send a STOP Condition
754
#define AT91C_TWI_MSEN            (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
755
#define AT91C_TWI_MSDIS           (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
756
#define AT91C_TWI_SWRST           (0x1 <<  7) // (TWI) Software Reset
757
// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
758
#define AT91C_TWI_IADRSZ          (0x3 <<  8) // (TWI) Internal Device Address Size
759
#define         AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
760
#define         AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
761
#define         AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
762
#define         AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
763
#define AT91C_TWI_MREAD           (0x1 << 12) // (TWI) Master Read Direction
764
#define AT91C_TWI_DADR            (0x7F << 16) // (TWI) Device Address
765
// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
766
#define AT91C_TWI_CLDIV           (0xFF <<  0) // (TWI) Clock Low Divider
767
#define AT91C_TWI_CHDIV           (0xFF <<  8) // (TWI) Clock High Divider
768
#define AT91C_TWI_CKDIV           (0x7 << 16) // (TWI) Clock Divider
769
// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
770
#define AT91C_TWI_TXCOMP          (0x1 <<  0) // (TWI) Transmission Completed
771
#define AT91C_TWI_RXRDY           (0x1 <<  1) // (TWI) Receive holding register ReaDY
772
#define AT91C_TWI_TXRDY           (0x1 <<  2) // (TWI) Transmit holding register ReaDY
773
#define AT91C_TWI_OVRE            (0x1 <<  6) // (TWI) Overrun Error
774
#define AT91C_TWI_UNRE            (0x1 <<  7) // (TWI) Underrun Error
775
#define AT91C_TWI_NACK            (0x1 <<  8) // (TWI) Not Acknowledged
776
// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
777
// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
778
// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
779
 
780
// *****************************************************************************
781
//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
782
// *****************************************************************************
783
// *** Register offset in AT91S_PWMC_CH structure ***
784
#define PWMC_CMR        ( 0) // Channel Mode Register
785
#define PWMC_CDTYR      ( 4) // Channel Duty Cycle Register
786
#define PWMC_CPRDR      ( 8) // Channel Period Register
787
#define PWMC_CCNTR      (12) // Channel Counter Register
788
#define PWMC_CUPDR      (16) // Channel Update Register
789
#define PWMC_Reserved   (20) // Reserved
790
// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
791
#define AT91C_PWMC_CPRE           (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
792
#define         AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH) 
793
#define         AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH) 
794
#define         AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH) 
795
#define AT91C_PWMC_CALG           (0x1 <<  8) // (PWMC_CH) Channel Alignment
796
#define AT91C_PWMC_CPOL           (0x1 <<  9) // (PWMC_CH) Channel Polarity
797
#define AT91C_PWMC_CPD            (0x1 << 10) // (PWMC_CH) Channel Update Period
798
// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
799
#define AT91C_PWMC_CDTY           (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
800
// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
801
#define AT91C_PWMC_CPRD           (0x0 <<  0) // (PWMC_CH) Channel Period
802
// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
803
#define AT91C_PWMC_CCNT           (0x0 <<  0) // (PWMC_CH) Channel Counter
804
// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
805
#define AT91C_PWMC_CUPD           (0x0 <<  0) // (PWMC_CH) Channel Update
806
 
807
// *****************************************************************************
808
//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
809
// *****************************************************************************
810
// *** Register offset in AT91S_PWMC structure ***
811
#define PWMC_MR         ( 0) // PWMC Mode Register
812
#define PWMC_ENA        ( 4) // PWMC Enable Register
813
#define PWMC_DIS        ( 8) // PWMC Disable Register
814
#define PWMC_SR         (12) // PWMC Status Register
815
#define PWMC_IER        (16) // PWMC Interrupt Enable Register
816
#define PWMC_IDR        (20) // PWMC Interrupt Disable Register
817
#define PWMC_IMR        (24) // PWMC Interrupt Mask Register
818
#define PWMC_ISR        (28) // PWMC Interrupt Status Register
819
#define PWMC_VR         (252) // PWMC Version Register
820
#define PWMC_CH         (512) // PWMC Channel
821
// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
822
#define AT91C_PWMC_DIVA           (0xFF <<  0) // (PWMC) CLKA divide factor.
823
#define AT91C_PWMC_PREA           (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
824
#define         AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC) 
825
#define AT91C_PWMC_DIVB           (0xFF << 16) // (PWMC) CLKB divide factor.
826
#define AT91C_PWMC_PREB           (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
827
#define         AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC) 
828
// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
829
#define AT91C_PWMC_CHID0          (0x1 <<  0) // (PWMC) Channel ID 0
830
#define AT91C_PWMC_CHID1          (0x1 <<  1) // (PWMC) Channel ID 1
831
#define AT91C_PWMC_CHID2          (0x1 <<  2) // (PWMC) Channel ID 2
832
#define AT91C_PWMC_CHID3          (0x1 <<  3) // (PWMC) Channel ID 3
833
// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
834
// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
835
// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
836
// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
837
// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
838
// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
839
 
840
// *****************************************************************************
841
//              SOFTWARE API DEFINITION  FOR USB Device Interface
842
// *****************************************************************************
843
// *** Register offset in AT91S_UDP structure ***
844
#define UDP_NUM         ( 0) // Frame Number Register
845
#define UDP_GLBSTATE    ( 4) // Global State Register
846
#define UDP_FADDR       ( 8) // Function Address Register
847
#define UDP_IER         (16) // Interrupt Enable Register
848
#define UDP_IDR         (20) // Interrupt Disable Register
849
#define UDP_IMR         (24) // Interrupt Mask Register
850
#define UDP_ISR         (28) // Interrupt Status Register
851
#define UDP_ICR         (32) // Interrupt Clear Register
852
#define UDP_RSTEP       (40) // Reset Endpoint Register
853
#define UDP_CSR         (48) // Endpoint Control and Status Register
854
#define UDP_FDR         (80) // Endpoint FIFO Data Register
855
#define UDP_TXVC        (116) // Transceiver Control Register
856
// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
857
#define AT91C_UDP_FRM_NUM         (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
858
#define AT91C_UDP_FRM_ERR         (0x1 << 16) // (UDP) Frame Error
859
#define AT91C_UDP_FRM_OK          (0x1 << 17) // (UDP) Frame OK
860
// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
861
#define AT91C_UDP_FADDEN          (0x1 <<  0) // (UDP) Function Address Enable
862
#define AT91C_UDP_CONFG           (0x1 <<  1) // (UDP) Configured
863
#define AT91C_UDP_ESR             (0x1 <<  2) // (UDP) Enable Send Resume
864
#define AT91C_UDP_RSMINPR         (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
865
#define AT91C_UDP_RMWUPE          (0x1 <<  4) // (UDP) Remote Wake Up Enable
866
// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
867
#define AT91C_UDP_FADD            (0xFF <<  0) // (UDP) Function Address Value
868
#define AT91C_UDP_FEN             (0x1 <<  8) // (UDP) Function Enable
869
// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
870
#define AT91C_UDP_EPINT0          (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
871
#define AT91C_UDP_EPINT1          (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
872
#define AT91C_UDP_EPINT2          (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
873
#define AT91C_UDP_EPINT3          (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
874
#define AT91C_UDP_EPINT4          (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
875
#define AT91C_UDP_EPINT5          (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
876
#define AT91C_UDP_RXSUSP          (0x1 <<  8) // (UDP) USB Suspend Interrupt
877
#define AT91C_UDP_RXRSM           (0x1 <<  9) // (UDP) USB Resume Interrupt
878
#define AT91C_UDP_EXTRSM          (0x1 << 10) // (UDP) USB External Resume Interrupt
879
#define AT91C_UDP_SOFINT          (0x1 << 11) // (UDP) USB Start Of frame Interrupt
880
#define AT91C_UDP_WAKEUP          (0x1 << 13) // (UDP) USB Resume Interrupt
881
// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
882
// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
883
// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
884
#define AT91C_UDP_ENDBUSRES       (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
885
// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
886
// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
887
#define AT91C_UDP_EP0             (0x1 <<  0) // (UDP) Reset Endpoint 0
888
#define AT91C_UDP_EP1             (0x1 <<  1) // (UDP) Reset Endpoint 1
889
#define AT91C_UDP_EP2             (0x1 <<  2) // (UDP) Reset Endpoint 2
890
#define AT91C_UDP_EP3             (0x1 <<  3) // (UDP) Reset Endpoint 3
891
#define AT91C_UDP_EP4             (0x1 <<  4) // (UDP) Reset Endpoint 4
892
#define AT91C_UDP_EP5             (0x1 <<  5) // (UDP) Reset Endpoint 5
893
// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
894
#define AT91C_UDP_TXCOMP          (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
895
#define AT91C_UDP_RX_DATA_BK0     (0x1 <<  1) // (UDP) Receive Data Bank 0
896
#define AT91C_UDP_RXSETUP         (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
897
#define AT91C_UDP_ISOERROR        (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
898
#define AT91C_UDP_TXPKTRDY        (0x1 <<  4) // (UDP) Transmit Packet Ready
899
#define AT91C_UDP_FORCESTALL      (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
900
#define AT91C_UDP_RX_DATA_BK1     (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
901
#define AT91C_UDP_DIR             (0x1 <<  7) // (UDP) Transfer Direction
902
#define AT91C_UDP_EPTYPE          (0x7 <<  8) // (UDP) Endpoint type
903
#define         AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
904
#define         AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
905
#define         AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
906
#define         AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
907
#define         AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
908
#define         AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
909
#define         AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
910
#define AT91C_UDP_DTGLE           (0x1 << 11) // (UDP) Data Toggle
911
#define AT91C_UDP_EPEDS           (0x1 << 15) // (UDP) Endpoint Enable Disable
912
#define AT91C_UDP_RXBYTECNT       (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
913
// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
914
#define AT91C_UDP_TXVDIS          (0x1 <<  8) // (UDP) 
915
#define AT91C_UDP_PUON            (0x1 <<  9) // (UDP) Pull-up ON
916
 
917
// *****************************************************************************
918
//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
919
// *****************************************************************************
920
// *** Register offset in AT91S_TC structure ***
921
#define TC_CCR          ( 0) // Channel Control Register
922
#define TC_CMR          ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
923
#define TC_CV           (16) // Counter Value
924
#define TC_RA           (20) // Register A
925
#define TC_RB           (24) // Register B
926
#define TC_RC           (28) // Register C
927
#define TC_SR           (32) // Status Register
928
#define TC_IER          (36) // Interrupt Enable Register
929
#define TC_IDR          (40) // Interrupt Disable Register
930
#define TC_IMR          (44) // Interrupt Mask Register
931
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
932
#define AT91C_TC_CLKEN            (0x1 <<  0) // (TC) Counter Clock Enable Command
933
#define AT91C_TC_CLKDIS           (0x1 <<  1) // (TC) Counter Clock Disable Command
934
#define AT91C_TC_SWTRG            (0x1 <<  2) // (TC) Software Trigger Command
935
// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
936
#define AT91C_TC_CLKS             (0x7 <<  0) // (TC) Clock Selection
937
#define         AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
938
#define         AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
939
#define         AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
940
#define         AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
941
#define         AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
942
#define         AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
943
#define         AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
944
#define         AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
945
#define AT91C_TC_CLKI             (0x1 <<  3) // (TC) Clock Invert
946
#define AT91C_TC_BURST            (0x3 <<  4) // (TC) Burst Signal Selection
947
#define         AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
948
#define         AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
949
#define         AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
950
#define         AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
951
#define AT91C_TC_CPCSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
952
#define AT91C_TC_LDBSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
953
#define AT91C_TC_CPCDIS           (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
954
#define AT91C_TC_LDBDIS           (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
955
#define AT91C_TC_ETRGEDG          (0x3 <<  8) // (TC) External Trigger Edge Selection
956
#define         AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
957
#define         AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
958
#define         AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
959
#define         AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
960
#define AT91C_TC_EEVTEDG          (0x3 <<  8) // (TC) External Event Edge Selection
961
#define         AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
962
#define         AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
963
#define         AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
964
#define         AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
965
#define AT91C_TC_EEVT             (0x3 << 10) // (TC) External Event  Selection
966
#define         AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
967
#define         AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
968
#define         AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
969
#define         AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
970
#define AT91C_TC_ABETRG           (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
971
#define AT91C_TC_ENETRG           (0x1 << 12) // (TC) External Event Trigger enable
972
#define AT91C_TC_WAVESEL          (0x3 << 13) // (TC) Waveform  Selection
973
#define         AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
974
#define         AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
975
#define         AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
976
#define         AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
977
#define AT91C_TC_CPCTRG           (0x1 << 14) // (TC) RC Compare Trigger Enable
978
#define AT91C_TC_WAVE             (0x1 << 15) // (TC) 
979
#define AT91C_TC_ACPA             (0x3 << 16) // (TC) RA Compare Effect on TIOA
980
#define         AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
981
#define         AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
982
#define         AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
983
#define         AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
984
#define AT91C_TC_LDRA             (0x3 << 16) // (TC) RA Loading Selection
985
#define         AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
986
#define         AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
987
#define         AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
988
#define         AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
989
#define AT91C_TC_ACPC             (0x3 << 18) // (TC) RC Compare Effect on TIOA
990
#define         AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
991
#define         AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
992
#define         AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
993
#define         AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
994
#define AT91C_TC_LDRB             (0x3 << 18) // (TC) RB Loading Selection
995
#define         AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
996
#define         AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
997
#define         AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
998
#define         AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
999
#define AT91C_TC_AEEVT            (0x3 << 20) // (TC) External Event Effect on TIOA
1000
#define         AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
1001
#define         AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
1002
#define         AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
1003
#define         AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
1004
#define AT91C_TC_ASWTRG           (0x3 << 22) // (TC) Software Trigger Effect on TIOA
1005
#define         AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
1006
#define         AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
1007
#define         AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
1008
#define         AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
1009
#define AT91C_TC_BCPB             (0x3 << 24) // (TC) RB Compare Effect on TIOB
1010
#define         AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
1011
#define         AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
1012
#define         AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
1013
#define         AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
1014
#define AT91C_TC_BCPC             (0x3 << 26) // (TC) RC Compare Effect on TIOB
1015
#define         AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
1016
#define         AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
1017
#define         AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
1018
#define         AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
1019
#define AT91C_TC_BEEVT            (0x3 << 28) // (TC) External Event Effect on TIOB
1020
#define         AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
1021
#define         AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
1022
#define         AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
1023
#define         AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
1024
#define AT91C_TC_BSWTRG           (0x3 << 30) // (TC) Software Trigger Effect on TIOB
1025
#define         AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
1026
#define         AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
1027
#define         AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
1028
#define         AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
1029
// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
1030
#define AT91C_TC_COVFS            (0x1 <<  0) // (TC) Counter Overflow
1031
#define AT91C_TC_LOVRS            (0x1 <<  1) // (TC) Load Overrun
1032
#define AT91C_TC_CPAS             (0x1 <<  2) // (TC) RA Compare
1033
#define AT91C_TC_CPBS             (0x1 <<  3) // (TC) RB Compare
1034
#define AT91C_TC_CPCS             (0x1 <<  4) // (TC) RC Compare
1035
#define AT91C_TC_LDRAS            (0x1 <<  5) // (TC) RA Loading
1036
#define AT91C_TC_LDRBS            (0x1 <<  6) // (TC) RB Loading
1037
#define AT91C_TC_ETRGS            (0x1 <<  7) // (TC) External Trigger
1038
#define AT91C_TC_CLKSTA           (0x1 << 16) // (TC) Clock Enabling
1039
#define AT91C_TC_MTIOA            (0x1 << 17) // (TC) TIOA Mirror
1040
#define AT91C_TC_MTIOB            (0x1 << 18) // (TC) TIOA Mirror
1041
// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
1042
// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
1043
// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
1044
 
1045
// *****************************************************************************
1046
//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
1047
// *****************************************************************************
1048
// *** Register offset in AT91S_TCB structure ***
1049
#define TCB_TC0         ( 0) // TC Channel 0
1050
#define TCB_TC1         (64) // TC Channel 1
1051
#define TCB_TC2         (128) // TC Channel 2
1052
#define TCB_BCR         (192) // TC Block Control Register
1053
#define TCB_BMR         (196) // TC Block Mode Register
1054
// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
1055
#define AT91C_TCB_SYNC            (0x1 <<  0) // (TCB) Synchro Command
1056
// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
1057
#define AT91C_TCB_TC0XC0S         (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
1058
#define         AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
1059
#define         AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
1060
#define         AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
1061
#define         AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
1062
#define AT91C_TCB_TC1XC1S         (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
1063
#define         AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
1064
#define         AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
1065
#define         AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
1066
#define         AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
1067
#define AT91C_TCB_TC2XC2S         (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
1068
#define         AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
1069
#define         AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
1070
#define         AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
1071
#define         AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
1072
 
1073
// *****************************************************************************
1074
//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
1075
// *****************************************************************************
1076
// *** Register offset in AT91S_CAN_MB structure ***
1077
#define CAN_MB_MMR      ( 0) // MailBox Mode Register
1078
#define CAN_MB_MAM      ( 4) // MailBox Acceptance Mask Register
1079
#define CAN_MB_MID      ( 8) // MailBox ID Register
1080
#define CAN_MB_MFID     (12) // MailBox Family ID Register
1081
#define CAN_MB_MSR      (16) // MailBox Status Register
1082
#define CAN_MB_MDL      (20) // MailBox Data Low Register
1083
#define CAN_MB_MDH      (24) // MailBox Data High Register
1084
#define CAN_MB_MCR      (28) // MailBox Control Register
1085
// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
1086
#define AT91C_CAN_MTIMEMARK       (0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
1087
#define AT91C_CAN_PRIOR           (0xF << 16) // (CAN_MB) Mailbox Priority
1088
#define AT91C_CAN_MOT             (0x7 << 24) // (CAN_MB) Mailbox Object Type
1089
#define         AT91C_CAN_MOT_DIS                  (0x0 << 24) // (CAN_MB) 
1090
#define         AT91C_CAN_MOT_RX                   (0x1 << 24) // (CAN_MB) 
1091
#define         AT91C_CAN_MOT_RXOVERWRITE          (0x2 << 24) // (CAN_MB) 
1092
#define         AT91C_CAN_MOT_TX                   (0x3 << 24) // (CAN_MB) 
1093
#define         AT91C_CAN_MOT_CONSUMER             (0x4 << 24) // (CAN_MB) 
1094
#define         AT91C_CAN_MOT_PRODUCER             (0x5 << 24) // (CAN_MB) 
1095
// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
1096
#define AT91C_CAN_MIDvB           (0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
1097
#define AT91C_CAN_MIDvA           (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
1098
#define AT91C_CAN_MIDE            (0x1 << 29) // (CAN_MB) Identifier Version
1099
// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
1100
// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
1101
// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
1102
#define AT91C_CAN_MTIMESTAMP      (0xFFFF <<  0) // (CAN_MB) Timer Value
1103
#define AT91C_CAN_MDLC            (0xF << 16) // (CAN_MB) Mailbox Data Length Code
1104
#define AT91C_CAN_MRTR            (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
1105
#define AT91C_CAN_MABT            (0x1 << 22) // (CAN_MB) Mailbox Message Abort
1106
#define AT91C_CAN_MRDY            (0x1 << 23) // (CAN_MB) Mailbox Ready
1107
#define AT91C_CAN_MMI             (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
1108
// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
1109
// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
1110
// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
1111
#define AT91C_CAN_MACR            (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
1112
#define AT91C_CAN_MTCR            (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
1113
 
1114
// *****************************************************************************
1115
//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
1116
// *****************************************************************************
1117
// *** Register offset in AT91S_CAN structure ***
1118
#define CAN_MR          ( 0) // Mode Register
1119
#define CAN_IER         ( 4) // Interrupt Enable Register
1120
#define CAN_IDR         ( 8) // Interrupt Disable Register
1121
#define CAN_IMR         (12) // Interrupt Mask Register
1122
#define CAN_SR          (16) // Status Register
1123
#define CAN_BR          (20) // Baudrate Register
1124
#define CAN_TIM         (24) // Timer Register
1125
#define CAN_TIMESTP     (28) // Time Stamp Register
1126
#define CAN_ECR         (32) // Error Counter Register
1127
#define CAN_TCR         (36) // Transfer Command Register
1128
#define CAN_ACR         (40) // Abort Command Register
1129
#define CAN_VR          (252) // Version Register
1130
#define CAN_MB0         (512) // CAN Mailbox 0
1131
#define CAN_MB1         (544) // CAN Mailbox 1
1132
#define CAN_MB2         (576) // CAN Mailbox 2
1133
#define CAN_MB3         (608) // CAN Mailbox 3
1134
#define CAN_MB4         (640) // CAN Mailbox 4
1135
#define CAN_MB5         (672) // CAN Mailbox 5
1136
#define CAN_MB6         (704) // CAN Mailbox 6
1137
#define CAN_MB7         (736) // CAN Mailbox 7
1138
#define CAN_MB8         (768) // CAN Mailbox 8
1139
#define CAN_MB9         (800) // CAN Mailbox 9
1140
#define CAN_MB10        (832) // CAN Mailbox 10
1141
#define CAN_MB11        (864) // CAN Mailbox 11
1142
#define CAN_MB12        (896) // CAN Mailbox 12
1143
#define CAN_MB13        (928) // CAN Mailbox 13
1144
#define CAN_MB14        (960) // CAN Mailbox 14
1145
#define CAN_MB15        (992) // CAN Mailbox 15
1146
// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
1147
#define AT91C_CAN_CANEN           (0x1 <<  0) // (CAN) CAN Controller Enable
1148
#define AT91C_CAN_LPM             (0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
1149
#define AT91C_CAN_ABM             (0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
1150
#define AT91C_CAN_OVL             (0x1 <<  3) // (CAN) Disable/Enable Overload Frame
1151
#define AT91C_CAN_TEOF            (0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
1152
#define AT91C_CAN_TTM             (0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
1153
#define AT91C_CAN_TIMFRZ          (0x1 <<  6) // (CAN) Enable Timer Freeze
1154
#define AT91C_CAN_DRPT            (0x1 <<  7) // (CAN) Disable Repeat
1155
// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
1156
#define AT91C_CAN_MB0             (0x1 <<  0) // (CAN) Mailbox 0 Flag
1157
#define AT91C_CAN_MB1             (0x1 <<  1) // (CAN) Mailbox 1 Flag
1158
#define AT91C_CAN_MB2             (0x1 <<  2) // (CAN) Mailbox 2 Flag
1159
#define AT91C_CAN_MB3             (0x1 <<  3) // (CAN) Mailbox 3 Flag
1160
#define AT91C_CAN_MB4             (0x1 <<  4) // (CAN) Mailbox 4 Flag
1161
#define AT91C_CAN_MB5             (0x1 <<  5) // (CAN) Mailbox 5 Flag
1162
#define AT91C_CAN_MB6             (0x1 <<  6) // (CAN) Mailbox 6 Flag
1163
#define AT91C_CAN_MB7             (0x1 <<  7) // (CAN) Mailbox 7 Flag
1164
#define AT91C_CAN_MB8             (0x1 <<  8) // (CAN) Mailbox 8 Flag
1165
#define AT91C_CAN_MB9             (0x1 <<  9) // (CAN) Mailbox 9 Flag
1166
#define AT91C_CAN_MB10            (0x1 << 10) // (CAN) Mailbox 10 Flag
1167
#define AT91C_CAN_MB11            (0x1 << 11) // (CAN) Mailbox 11 Flag
1168
#define AT91C_CAN_MB12            (0x1 << 12) // (CAN) Mailbox 12 Flag
1169
#define AT91C_CAN_MB13            (0x1 << 13) // (CAN) Mailbox 13 Flag
1170
#define AT91C_CAN_MB14            (0x1 << 14) // (CAN) Mailbox 14 Flag
1171
#define AT91C_CAN_MB15            (0x1 << 15) // (CAN) Mailbox 15 Flag
1172
#define AT91C_CAN_ERRA            (0x1 << 16) // (CAN) Error Active Mode Flag
1173
#define AT91C_CAN_WARN            (0x1 << 17) // (CAN) Warning Limit Flag
1174
#define AT91C_CAN_ERRP            (0x1 << 18) // (CAN) Error Passive Mode Flag
1175
#define AT91C_CAN_BOFF            (0x1 << 19) // (CAN) Bus Off Mode Flag
1176
#define AT91C_CAN_SLEEP           (0x1 << 20) // (CAN) Sleep Flag
1177
#define AT91C_CAN_WAKEUP          (0x1 << 21) // (CAN) Wakeup Flag
1178
#define AT91C_CAN_TOVF            (0x1 << 22) // (CAN) Timer Overflow Flag
1179
#define AT91C_CAN_TSTP            (0x1 << 23) // (CAN) Timestamp Flag
1180
#define AT91C_CAN_CERR            (0x1 << 24) // (CAN) CRC Error
1181
#define AT91C_CAN_SERR            (0x1 << 25) // (CAN) Stuffing Error
1182
#define AT91C_CAN_AERR            (0x1 << 26) // (CAN) Acknowledgment Error
1183
#define AT91C_CAN_FERR            (0x1 << 27) // (CAN) Form Error
1184
#define AT91C_CAN_BERR            (0x1 << 28) // (CAN) Bit Error
1185
// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
1186
// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
1187
// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
1188
#define AT91C_CAN_RBSY            (0x1 << 29) // (CAN) Receiver Busy
1189
#define AT91C_CAN_TBSY            (0x1 << 30) // (CAN) Transmitter Busy
1190
#define AT91C_CAN_OVLY            (0x1 << 31) // (CAN) Overload Busy
1191
// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
1192
#define AT91C_CAN_PHASE2          (0x7 <<  0) // (CAN) Phase 2 segment
1193
#define AT91C_CAN_PHASE1          (0x7 <<  4) // (CAN) Phase 1 segment
1194
#define AT91C_CAN_PROPAG          (0x7 <<  8) // (CAN) Programmation time segment
1195
#define AT91C_CAN_SYNC            (0x3 << 12) // (CAN) Re-synchronization jump width segment
1196
#define AT91C_CAN_BRP             (0x7F << 16) // (CAN) Baudrate Prescaler
1197
#define AT91C_CAN_SMP             (0x1 << 24) // (CAN) Sampling mode
1198
// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
1199
#define AT91C_CAN_TIMER           (0xFFFF <<  0) // (CAN) Timer field
1200
// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
1201
// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
1202
#define AT91C_CAN_REC             (0xFF <<  0) // (CAN) Receive Error Counter
1203
#define AT91C_CAN_TEC             (0xFF << 16) // (CAN) Transmit Error Counter
1204
// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
1205
#define AT91C_CAN_TIMRST          (0x1 << 31) // (CAN) Timer Reset Field
1206
// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
1207
 
1208
// *****************************************************************************
1209
//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
1210
// *****************************************************************************
1211
// *** Register offset in AT91S_EMAC structure ***
1212
#define EMAC_NCR        ( 0) // Network Control Register
1213
#define EMAC_NCFGR      ( 4) // Network Configuration Register
1214
#define EMAC_NSR        ( 8) // Network Status Register
1215
#define EMAC_TSR        (20) // Transmit Status Register
1216
#define EMAC_RBQP       (24) // Receive Buffer Queue Pointer
1217
#define EMAC_TBQP       (28) // Transmit Buffer Queue Pointer
1218
#define EMAC_RSR        (32) // Receive Status Register
1219
#define EMAC_ISR        (36) // Interrupt Status Register
1220
#define EMAC_IER        (40) // Interrupt Enable Register
1221
#define EMAC_IDR        (44) // Interrupt Disable Register
1222
#define EMAC_IMR        (48) // Interrupt Mask Register
1223
#define EMAC_MAN        (52) // PHY Maintenance Register
1224
#define EMAC_PTR        (56) // Pause Time Register
1225
#define EMAC_PFR        (60) // Pause Frames received Register
1226
#define EMAC_FTO        (64) // Frames Transmitted OK Register
1227
#define EMAC_SCF        (68) // Single Collision Frame Register
1228
#define EMAC_MCF        (72) // Multiple Collision Frame Register
1229
#define EMAC_FRO        (76) // Frames Received OK Register
1230
#define EMAC_FCSE       (80) // Frame Check Sequence Error Register
1231
#define EMAC_ALE        (84) // Alignment Error Register
1232
#define EMAC_DTF        (88) // Deferred Transmission Frame Register
1233
#define EMAC_LCOL       (92) // Late Collision Register
1234
#define EMAC_ECOL       (96) // Excessive Collision Register
1235
#define EMAC_TUND       (100) // Transmit Underrun Error Register
1236
#define EMAC_CSE        (104) // Carrier Sense Error Register
1237
#define EMAC_RRE        (108) // Receive Ressource Error Register
1238
#define EMAC_ROV        (112) // Receive Overrun Errors Register
1239
#define EMAC_RSE        (116) // Receive Symbol Errors Register
1240
#define EMAC_ELE        (120) // Excessive Length Errors Register
1241
#define EMAC_RJA        (124) // Receive Jabbers Register
1242
#define EMAC_USF        (128) // Undersize Frames Register
1243
#define EMAC_STE        (132) // SQE Test Error Register
1244
#define EMAC_RLE        (136) // Receive Length Field Mismatch Register
1245
#define EMAC_TPF        (140) // Transmitted Pause Frames Register
1246
#define EMAC_HRB        (144) // Hash Address Bottom[31:0]
1247
#define EMAC_HRT        (148) // Hash Address Top[63:32]
1248
#define EMAC_SA1L       (152) // Specific Address 1 Bottom, First 4 bytes
1249
#define EMAC_SA1H       (156) // Specific Address 1 Top, Last 2 bytes
1250
#define EMAC_SA2L       (160) // Specific Address 2 Bottom, First 4 bytes
1251
#define EMAC_SA2H       (164) // Specific Address 2 Top, Last 2 bytes
1252
#define EMAC_SA3L       (168) // Specific Address 3 Bottom, First 4 bytes
1253
#define EMAC_SA3H       (172) // Specific Address 3 Top, Last 2 bytes
1254
#define EMAC_SA4L       (176) // Specific Address 4 Bottom, First 4 bytes
1255
#define EMAC_SA4H       (180) // Specific Address 4 Top, Last 2 bytes
1256
#define EMAC_TID        (184) // Type ID Checking Register
1257
#define EMAC_TPQ        (188) // Transmit Pause Quantum Register
1258
#define EMAC_USRIO      (192) // USER Input/Output Register
1259
#define EMAC_WOL        (196) // Wake On LAN Register
1260
#define EMAC_REV        (252) // Revision Register
1261
// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
1262
#define AT91C_EMAC_LB             (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
1263
#define AT91C_EMAC_LLB            (0x1 <<  1) // (EMAC) Loopback local. 
1264
#define AT91C_EMAC_RE             (0x1 <<  2) // (EMAC) Receive enable. 
1265
#define AT91C_EMAC_TE             (0x1 <<  3) // (EMAC) Transmit enable. 
1266
#define AT91C_EMAC_MPE            (0x1 <<  4) // (EMAC) Management port enable. 
1267
#define AT91C_EMAC_CLRSTAT        (0x1 <<  5) // (EMAC) Clear statistics registers. 
1268
#define AT91C_EMAC_INCSTAT        (0x1 <<  6) // (EMAC) Increment statistics registers. 
1269
#define AT91C_EMAC_WESTAT         (0x1 <<  7) // (EMAC) Write enable for statistics registers. 
1270
#define AT91C_EMAC_BP             (0x1 <<  8) // (EMAC) Back pressure. 
1271
#define AT91C_EMAC_TSTART         (0x1 <<  9) // (EMAC) Start Transmission. 
1272
#define AT91C_EMAC_THALT          (0x1 << 10) // (EMAC) Transmission Halt. 
1273
#define AT91C_EMAC_TPFR           (0x1 << 11) // (EMAC) Transmit pause frame 
1274
#define AT91C_EMAC_TZQ            (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
1275
// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
1276
#define AT91C_EMAC_SPD            (0x1 <<  0) // (EMAC) Speed. 
1277
#define AT91C_EMAC_FD             (0x1 <<  1) // (EMAC) Full duplex. 
1278
#define AT91C_EMAC_JFRAME         (0x1 <<  3) // (EMAC) Jumbo Frames. 
1279
#define AT91C_EMAC_CAF            (0x1 <<  4) // (EMAC) Copy all frames. 
1280
#define AT91C_EMAC_NBC            (0x1 <<  5) // (EMAC) No broadcast. 
1281
#define AT91C_EMAC_MTI            (0x1 <<  6) // (EMAC) Multicast hash event enable
1282
#define AT91C_EMAC_UNI            (0x1 <<  7) // (EMAC) Unicast hash enable. 
1283
#define AT91C_EMAC_BIG            (0x1 <<  8) // (EMAC) Receive 1522 bytes. 
1284
#define AT91C_EMAC_EAE            (0x1 <<  9) // (EMAC) External address match enable. 
1285
#define AT91C_EMAC_CLK            (0x3 << 10) // (EMAC) 
1286
#define         AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8
1287
#define         AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16
1288
#define         AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32
1289
#define         AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64
1290
#define AT91C_EMAC_RTY            (0x1 << 12) // (EMAC) 
1291
#define AT91C_EMAC_PAE            (0x1 << 13) // (EMAC) 
1292
#define AT91C_EMAC_RBOF           (0x3 << 14) // (EMAC) 
1293
#define         AT91C_EMAC_RBOF_OFFSET_0             (0x0 << 14) // (EMAC) no offset from start of receive buffer
1294
#define         AT91C_EMAC_RBOF_OFFSET_1             (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
1295
#define         AT91C_EMAC_RBOF_OFFSET_2             (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
1296
#define         AT91C_EMAC_RBOF_OFFSET_3             (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
1297
#define AT91C_EMAC_RLCE           (0x1 << 16) // (EMAC) Receive Length field Checking Enable
1298
#define AT91C_EMAC_DRFCS          (0x1 << 17) // (EMAC) Discard Receive FCS
1299
#define AT91C_EMAC_EFRHD          (0x1 << 18) // (EMAC) 
1300
#define AT91C_EMAC_IRXFCS         (0x1 << 19) // (EMAC) Ignore RX FCS
1301
// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
1302
#define AT91C_EMAC_LINKR          (0x1 <<  0) // (EMAC) 
1303
#define AT91C_EMAC_MDIO           (0x1 <<  1) // (EMAC) 
1304
#define AT91C_EMAC_IDLE           (0x1 <<  2) // (EMAC) 
1305
// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
1306
#define AT91C_EMAC_UBR            (0x1 <<  0) // (EMAC) 
1307
#define AT91C_EMAC_COL            (0x1 <<  1) // (EMAC) 
1308
#define AT91C_EMAC_RLES           (0x1 <<  2) // (EMAC) 
1309
#define AT91C_EMAC_TGO            (0x1 <<  3) // (EMAC) Transmit Go
1310
#define AT91C_EMAC_BEX            (0x1 <<  4) // (EMAC) Buffers exhausted mid frame
1311
#define AT91C_EMAC_COMP           (0x1 <<  5) // (EMAC) 
1312
#define AT91C_EMAC_UND            (0x1 <<  6) // (EMAC) 
1313
// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
1314
#define AT91C_EMAC_BNA            (0x1 <<  0) // (EMAC) 
1315
#define AT91C_EMAC_REC            (0x1 <<  1) // (EMAC) 
1316
#define AT91C_EMAC_OVR            (0x1 <<  2) // (EMAC) 
1317
// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
1318
#define AT91C_EMAC_MFD            (0x1 <<  0) // (EMAC) 
1319
#define AT91C_EMAC_RCOMP          (0x1 <<  1) // (EMAC) 
1320
#define AT91C_EMAC_RXUBR          (0x1 <<  2) // (EMAC) 
1321
#define AT91C_EMAC_TXUBR          (0x1 <<  3) // (EMAC) 
1322
#define AT91C_EMAC_TUNDR          (0x1 <<  4) // (EMAC) 
1323
#define AT91C_EMAC_RLEX           (0x1 <<  5) // (EMAC) 
1324
#define AT91C_EMAC_TXERR          (0x1 <<  6) // (EMAC) 
1325
#define AT91C_EMAC_TCOMP          (0x1 <<  7) // (EMAC) 
1326
#define AT91C_EMAC_LINK           (0x1 <<  9) // (EMAC) 
1327
#define AT91C_EMAC_ROVR           (0x1 << 10) // (EMAC) 
1328
#define AT91C_EMAC_HRESP          (0x1 << 11) // (EMAC) 
1329
#define AT91C_EMAC_PFRE           (0x1 << 12) // (EMAC) 
1330
#define AT91C_EMAC_PTZ            (0x1 << 13) // (EMAC) 
1331
// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
1332
// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
1333
// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
1334
// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
1335
#define AT91C_EMAC_DATA           (0xFFFF <<  0) // (EMAC) 
1336
#define AT91C_EMAC_CODE           (0x3 << 16) // (EMAC) 
1337
#define AT91C_EMAC_REGA           (0x1F << 18) // (EMAC) 
1338
#define AT91C_EMAC_PHYA           (0x1F << 23) // (EMAC) 
1339
#define AT91C_EMAC_RW             (0x3 << 28) // (EMAC) 
1340
#define AT91C_EMAC_SOF            (0x3 << 30) // (EMAC) 
1341
// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
1342
#define AT91C_EMAC_RMII           (0x1 <<  0) // (EMAC) Reduce MII
1343
// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
1344
#define AT91C_EMAC_IP             (0xFFFF <<  0) // (EMAC) ARP request IP address
1345
#define AT91C_EMAC_MAG            (0x1 << 16) // (EMAC) Magic packet event enable
1346
#define AT91C_EMAC_ARP            (0x1 << 17) // (EMAC) ARP request event enable
1347
#define AT91C_EMAC_SA1            (0x1 << 18) // (EMAC) Specific address register 1 event enable
1348
// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
1349
#define AT91C_EMAC_REVREF         (0xFFFF <<  0) // (EMAC) 
1350
#define AT91C_EMAC_PARTREF        (0xFFFF << 16) // (EMAC) 
1351
 
1352
// *****************************************************************************
1353
//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
1354
// *****************************************************************************
1355
// *** Register offset in AT91S_ADC structure ***
1356
#define ADC_CR          ( 0) // ADC Control Register
1357
#define ADC_MR          ( 4) // ADC Mode Register
1358
#define ADC_CHER        (16) // ADC Channel Enable Register
1359
#define ADC_CHDR        (20) // ADC Channel Disable Register
1360
#define ADC_CHSR        (24) // ADC Channel Status Register
1361
#define ADC_SR          (28) // ADC Status Register
1362
#define ADC_LCDR        (32) // ADC Last Converted Data Register
1363
#define ADC_IER         (36) // ADC Interrupt Enable Register
1364
#define ADC_IDR         (40) // ADC Interrupt Disable Register
1365
#define ADC_IMR         (44) // ADC Interrupt Mask Register
1366
#define ADC_CDR0        (48) // ADC Channel Data Register 0
1367
#define ADC_CDR1        (52) // ADC Channel Data Register 1
1368
#define ADC_CDR2        (56) // ADC Channel Data Register 2
1369
#define ADC_CDR3        (60) // ADC Channel Data Register 3
1370
#define ADC_CDR4        (64) // ADC Channel Data Register 4
1371
#define ADC_CDR5        (68) // ADC Channel Data Register 5
1372
#define ADC_CDR6        (72) // ADC Channel Data Register 6
1373
#define ADC_CDR7        (76) // ADC Channel Data Register 7
1374
#define ADC_RPR         (256) // Receive Pointer Register
1375
#define ADC_RCR         (260) // Receive Counter Register
1376
#define ADC_TPR         (264) // Transmit Pointer Register
1377
#define ADC_TCR         (268) // Transmit Counter Register
1378
#define ADC_RNPR        (272) // Receive Next Pointer Register
1379
#define ADC_RNCR        (276) // Receive Next Counter Register
1380
#define ADC_TNPR        (280) // Transmit Next Pointer Register
1381
#define ADC_TNCR        (284) // Transmit Next Counter Register
1382
#define ADC_PTCR        (288) // PDC Transfer Control Register
1383
#define ADC_PTSR        (292) // PDC Transfer Status Register
1384
// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
1385
#define AT91C_ADC_SWRST           (0x1 <<  0) // (ADC) Software Reset
1386
#define AT91C_ADC_START           (0x1 <<  1) // (ADC) Start Conversion
1387
// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
1388
#define AT91C_ADC_TRGEN           (0x1 <<  0) // (ADC) Trigger Enable
1389
#define         AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
1390
#define         AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
1391
#define AT91C_ADC_TRGSEL          (0x7 <<  1) // (ADC) Trigger Selection
1392
#define         AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
1393
#define         AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
1394
#define         AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
1395
#define         AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
1396
#define         AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
1397
#define         AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
1398
#define         AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
1399
#define AT91C_ADC_LOWRES          (0x1 <<  4) // (ADC) Resolution.
1400
#define         AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
1401
#define         AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
1402
#define AT91C_ADC_SLEEP           (0x1 <<  5) // (ADC) Sleep Mode
1403
#define         AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
1404
#define         AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
1405
#define AT91C_ADC_PRESCAL         (0x3F <<  8) // (ADC) Prescaler rate selection
1406
#define AT91C_ADC_STARTUP         (0x1F << 16) // (ADC) Startup Time
1407
#define AT91C_ADC_SHTIM           (0xF << 24) // (ADC) Sample & Hold Time
1408
// --------     ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
1409
#define AT91C_ADC_CH0             (0x1 <<  0) // (ADC) Channel 0
1410
#define AT91C_ADC_CH1             (0x1 <<  1) // (ADC) Channel 1
1411
#define AT91C_ADC_CH2             (0x1 <<  2) // (ADC) Channel 2
1412
#define AT91C_ADC_CH3             (0x1 <<  3) // (ADC) Channel 3
1413
#define AT91C_ADC_CH4             (0x1 <<  4) // (ADC) Channel 4
1414
#define AT91C_ADC_CH5             (0x1 <<  5) // (ADC) Channel 5
1415
#define AT91C_ADC_CH6             (0x1 <<  6) // (ADC) Channel 6
1416
#define AT91C_ADC_CH7             (0x1 <<  7) // (ADC) Channel 7
1417
// --------     ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
1418
// --------     ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
1419
// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
1420
#define AT91C_ADC_EOC0            (0x1 <<  0) // (ADC) End of Conversion
1421
#define AT91C_ADC_EOC1            (0x1 <<  1) // (ADC) End of Conversion
1422
#define AT91C_ADC_EOC2            (0x1 <<  2) // (ADC) End of Conversion
1423
#define AT91C_ADC_EOC3            (0x1 <<  3) // (ADC) End of Conversion
1424
#define AT91C_ADC_EOC4            (0x1 <<  4) // (ADC) End of Conversion
1425
#define AT91C_ADC_EOC5            (0x1 <<  5) // (ADC) End of Conversion
1426
#define AT91C_ADC_EOC6            (0x1 <<  6) // (ADC) End of Conversion
1427
#define AT91C_ADC_EOC7            (0x1 <<  7) // (ADC) End of Conversion
1428
#define AT91C_ADC_OVRE0           (0x1 <<  8) // (ADC) Overrun Error
1429
#define AT91C_ADC_OVRE1           (0x1 <<  9) // (ADC) Overrun Error
1430
#define AT91C_ADC_OVRE2           (0x1 << 10) // (ADC) Overrun Error
1431
#define AT91C_ADC_OVRE3           (0x1 << 11) // (ADC) Overrun Error
1432
#define AT91C_ADC_OVRE4           (0x1 << 12) // (ADC) Overrun Error
1433
#define AT91C_ADC_OVRE5           (0x1 << 13) // (ADC) Overrun Error
1434
#define AT91C_ADC_OVRE6           (0x1 << 14) // (ADC) Overrun Error
1435
#define AT91C_ADC_OVRE7           (0x1 << 15) // (ADC) Overrun Error
1436
#define AT91C_ADC_DRDY            (0x1 << 16) // (ADC) Data Ready
1437
#define AT91C_ADC_GOVRE           (0x1 << 17) // (ADC) General Overrun
1438
#define AT91C_ADC_ENDRX           (0x1 << 18) // (ADC) End of Receiver Transfer
1439
#define AT91C_ADC_RXBUFF          (0x1 << 19) // (ADC) RXBUFF Interrupt
1440
// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
1441
#define AT91C_ADC_LDATA           (0x3FF <<  0) // (ADC) Last Data Converted
1442
// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
1443
// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
1444
// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
1445
// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
1446
#define AT91C_ADC_DATA            (0x3FF <<  0) // (ADC) Converted Data
1447
// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
1448
// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
1449
// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
1450
// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
1451
// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
1452
// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
1453
// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
1454
 
1455
// *****************************************************************************
1456
//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
1457
// *****************************************************************************
1458
// *** Register offset in AT91S_AES structure ***
1459
#define AES_CR          ( 0) // Control Register
1460
#define AES_MR          ( 4) // Mode Register
1461
#define AES_IER         (16) // Interrupt Enable Register
1462
#define AES_IDR         (20) // Interrupt Disable Register
1463
#define AES_IMR         (24) // Interrupt Mask Register
1464
#define AES_ISR         (28) // Interrupt Status Register
1465
#define AES_KEYWxR      (32) // Key Word x Register
1466
#define AES_IDATAxR     (64) // Input Data x Register
1467
#define AES_ODATAxR     (80) // Output Data x Register
1468
#define AES_IVxR        (96) // Initialization Vector x Register
1469
#define AES_VR          (252) // AES Version Register
1470
#define AES_RPR         (256) // Receive Pointer Register
1471
#define AES_RCR         (260) // Receive Counter Register
1472
#define AES_TPR         (264) // Transmit Pointer Register
1473
#define AES_TCR         (268) // Transmit Counter Register
1474
#define AES_RNPR        (272) // Receive Next Pointer Register
1475
#define AES_RNCR        (276) // Receive Next Counter Register
1476
#define AES_TNPR        (280) // Transmit Next Pointer Register
1477
#define AES_TNCR        (284) // Transmit Next Counter Register
1478
#define AES_PTCR        (288) // PDC Transfer Control Register
1479
#define AES_PTSR        (292) // PDC Transfer Status Register
1480
// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
1481
#define AT91C_AES_START           (0x1 <<  0) // (AES) Starts Processing
1482
#define AT91C_AES_SWRST           (0x1 <<  8) // (AES) Software Reset
1483
#define AT91C_AES_LOADSEED        (0x1 << 16) // (AES) Random Number Generator Seed Loading
1484
// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
1485
#define AT91C_AES_CIPHER          (0x1 <<  0) // (AES) Processing Mode
1486
#define AT91C_AES_PROCDLY         (0xF <<  4) // (AES) Processing Delay
1487
#define AT91C_AES_SMOD            (0x3 <<  8) // (AES) Start Mode
1488
#define         AT91C_AES_SMOD_MANUAL               (0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
1489
#define         AT91C_AES_SMOD_AUTO                 (0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
1490
#define         AT91C_AES_SMOD_PDC                  (0x2 <<  8) // (AES) PDC Mode (cf datasheet).
1491
#define AT91C_AES_OPMOD           (0x7 << 12) // (AES) Operation Mode
1492
#define         AT91C_AES_OPMOD_ECB                  (0x0 << 12) // (AES) ECB Electronic CodeBook mode.
1493
#define         AT91C_AES_OPMOD_CBC                  (0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
1494
#define         AT91C_AES_OPMOD_OFB                  (0x2 << 12) // (AES) OFB Output Feedback mode.
1495
#define         AT91C_AES_OPMOD_CFB                  (0x3 << 12) // (AES) CFB Cipher Feedback mode.
1496
#define         AT91C_AES_OPMOD_CTR                  (0x4 << 12) // (AES) CTR Counter mode.
1497
#define AT91C_AES_LOD             (0x1 << 15) // (AES) Last Output Data Mode
1498
#define AT91C_AES_CFBS            (0x7 << 16) // (AES) Cipher Feedback Data Size
1499
#define         AT91C_AES_CFBS_128_BIT              (0x0 << 16) // (AES) 128-bit.
1500
#define         AT91C_AES_CFBS_64_BIT               (0x1 << 16) // (AES) 64-bit.
1501
#define         AT91C_AES_CFBS_32_BIT               (0x2 << 16) // (AES) 32-bit.
1502
#define         AT91C_AES_CFBS_16_BIT               (0x3 << 16) // (AES) 16-bit.
1503
#define         AT91C_AES_CFBS_8_BIT                (0x4 << 16) // (AES) 8-bit.
1504
#define AT91C_AES_CKEY            (0xF << 20) // (AES) Countermeasure Key
1505
#define AT91C_AES_CTYPE           (0x1F << 24) // (AES) Countermeasure Type
1506
#define         AT91C_AES_CTYPE_TYPE1_EN             (0x1 << 24) // (AES) Countermeasure type 1 is enabled.
1507
#define         AT91C_AES_CTYPE_TYPE2_EN             (0x2 << 24) // (AES) Countermeasure type 2 is enabled.
1508
#define         AT91C_AES_CTYPE_TYPE3_EN             (0x4 << 24) // (AES) Countermeasure type 3 is enabled.
1509
#define         AT91C_AES_CTYPE_TYPE4_EN             (0x8 << 24) // (AES) Countermeasure type 4 is enabled.
1510
#define         AT91C_AES_CTYPE_TYPE5_EN             (0x10 << 24) // (AES) Countermeasure type 5 is enabled.
1511
// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
1512
#define AT91C_AES_DATRDY          (0x1 <<  0) // (AES) DATRDY
1513
#define AT91C_AES_ENDRX           (0x1 <<  1) // (AES) PDC Read Buffer End
1514
#define AT91C_AES_ENDTX           (0x1 <<  2) // (AES) PDC Write Buffer End
1515
#define AT91C_AES_RXBUFF          (0x1 <<  3) // (AES) PDC Read Buffer Full
1516
#define AT91C_AES_TXBUFE          (0x1 <<  4) // (AES) PDC Write Buffer Empty
1517
#define AT91C_AES_URAD            (0x1 <<  8) // (AES) Unspecified Register Access Detection
1518
// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
1519
// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
1520
// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
1521
#define AT91C_AES_URAT            (0x7 << 12) // (AES) Unspecified Register Access Type Status
1522
#define         AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
1523
#define         AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing.
1524
#define         AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing.
1525
#define         AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  (0x3 << 12) // (AES) Output data register read during the sub-keys generation.
1526
#define         AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation.
1527
#define         AT91C_AES_URAT_WO_REG_READ          (0x5 << 12) // (AES) Write-only register read access.
1528
 
1529
// *****************************************************************************
1530
//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
1531
// *****************************************************************************
1532
// *** Register offset in AT91S_TDES structure ***
1533
#define TDES_CR         ( 0) // Control Register
1534
#define TDES_MR         ( 4) // Mode Register
1535
#define TDES_IER        (16) // Interrupt Enable Register
1536
#define TDES_IDR        (20) // Interrupt Disable Register
1537
#define TDES_IMR        (24) // Interrupt Mask Register
1538
#define TDES_ISR        (28) // Interrupt Status Register
1539
#define TDES_KEY1WxR    (32) // Key 1 Word x Register
1540
#define TDES_KEY2WxR    (40) // Key 2 Word x Register
1541
#define TDES_KEY3WxR    (48) // Key 3 Word x Register
1542
#define TDES_IDATAxR    (64) // Input Data x Register
1543
#define TDES_ODATAxR    (80) // Output Data x Register
1544
#define TDES_IVxR       (96) // Initialization Vector x Register
1545
#define TDES_VR         (252) // TDES Version Register
1546
#define TDES_RPR        (256) // Receive Pointer Register
1547
#define TDES_RCR        (260) // Receive Counter Register
1548
#define TDES_TPR        (264) // Transmit Pointer Register
1549
#define TDES_TCR        (268) // Transmit Counter Register
1550
#define TDES_RNPR       (272) // Receive Next Pointer Register
1551
#define TDES_RNCR       (276) // Receive Next Counter Register
1552
#define TDES_TNPR       (280) // Transmit Next Pointer Register
1553
#define TDES_TNCR       (284) // Transmit Next Counter Register
1554
#define TDES_PTCR       (288) // PDC Transfer Control Register
1555
#define TDES_PTSR       (292) // PDC Transfer Status Register
1556
// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
1557
#define AT91C_TDES_START          (0x1 <<  0) // (TDES) Starts Processing
1558
#define AT91C_TDES_SWRST          (0x1 <<  8) // (TDES) Software Reset
1559
// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
1560
#define AT91C_TDES_CIPHER         (0x1 <<  0) // (TDES) Processing Mode
1561
#define AT91C_TDES_TDESMOD        (0x1 <<  1) // (TDES) Single or Triple DES Mode
1562
#define AT91C_TDES_KEYMOD         (0x1 <<  4) // (TDES) Key Mode
1563
#define AT91C_TDES_SMOD           (0x3 <<  8) // (TDES) Start Mode
1564
#define         AT91C_TDES_SMOD_MANUAL               (0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
1565
#define         AT91C_TDES_SMOD_AUTO                 (0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
1566
#define         AT91C_TDES_SMOD_PDC                  (0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
1567
#define AT91C_TDES_OPMOD          (0x3 << 12) // (TDES) Operation Mode
1568
#define         AT91C_TDES_OPMOD_ECB                  (0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
1569
#define         AT91C_TDES_OPMOD_CBC                  (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
1570
#define         AT91C_TDES_OPMOD_OFB                  (0x2 << 12) // (TDES) OFB Output Feedback mode.
1571
#define         AT91C_TDES_OPMOD_CFB                  (0x3 << 12) // (TDES) CFB Cipher Feedback mode.
1572
#define AT91C_TDES_LOD            (0x1 << 15) // (TDES) Last Output Data Mode
1573
#define AT91C_TDES_CFBS           (0x3 << 16) // (TDES) Cipher Feedback Data Size
1574
#define         AT91C_TDES_CFBS_64_BIT               (0x0 << 16) // (TDES) 64-bit.
1575
#define         AT91C_TDES_CFBS_32_BIT               (0x1 << 16) // (TDES) 32-bit.
1576
#define         AT91C_TDES_CFBS_16_BIT               (0x2 << 16) // (TDES) 16-bit.
1577
#define         AT91C_TDES_CFBS_8_BIT                (0x3 << 16) // (TDES) 8-bit.
1578
// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
1579
#define AT91C_TDES_DATRDY         (0x1 <<  0) // (TDES) DATRDY
1580
#define AT91C_TDES_ENDRX          (0x1 <<  1) // (TDES) PDC Read Buffer End
1581
#define AT91C_TDES_ENDTX          (0x1 <<  2) // (TDES) PDC Write Buffer End
1582
#define AT91C_TDES_RXBUFF         (0x1 <<  3) // (TDES) PDC Read Buffer Full
1583
#define AT91C_TDES_TXBUFE         (0x1 <<  4) // (TDES) PDC Write Buffer Empty
1584
#define AT91C_TDES_URAD           (0x1 <<  8) // (TDES) Unspecified Register Access Detection
1585
// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
1586
// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
1587
// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
1588
#define AT91C_TDES_URAT           (0x3 << 12) // (TDES) Unspecified Register Access Type Status
1589
#define         AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
1590
#define         AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing.
1591
#define         AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing.
1592
#define         AT91C_TDES_URAT_WO_REG_READ          (0x3 << 12) // (TDES) Write-only register read access.
1593
 
1594
// *****************************************************************************
1595
//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
1596
// *****************************************************************************
1597
// ========== Register definition for SYS peripheral ========== 
1598
// ========== Register definition for AIC peripheral ========== 
1599
#define AT91C_AIC_IVR             (0xFFFFF100) // (AIC) IRQ Vector Register
1600
#define AT91C_AIC_SMR             (0xFFFFF000) // (AIC) Source Mode Register
1601
#define AT91C_AIC_FVR             (0xFFFFF104) // (AIC) FIQ Vector Register
1602
#define AT91C_AIC_DCR             (0xFFFFF138) // (AIC) Debug Control Register (Protect)
1603
#define AT91C_AIC_EOICR           (0xFFFFF130) // (AIC) End of Interrupt Command Register
1604
#define AT91C_AIC_SVR             (0xFFFFF080) // (AIC) Source Vector Register
1605
#define AT91C_AIC_FFSR            (0xFFFFF148) // (AIC) Fast Forcing Status Register
1606
#define AT91C_AIC_ICCR            (0xFFFFF128) // (AIC) Interrupt Clear Command Register
1607
#define AT91C_AIC_ISR             (0xFFFFF108) // (AIC) Interrupt Status Register
1608
#define AT91C_AIC_IMR             (0xFFFFF110) // (AIC) Interrupt Mask Register
1609
#define AT91C_AIC_IPR             (0xFFFFF10C) // (AIC) Interrupt Pending Register
1610
#define AT91C_AIC_FFER            (0xFFFFF140) // (AIC) Fast Forcing Enable Register
1611
#define AT91C_AIC_IECR            (0xFFFFF120) // (AIC) Interrupt Enable Command Register
1612
#define AT91C_AIC_ISCR            (0xFFFFF12C) // (AIC) Interrupt Set Command Register
1613
#define AT91C_AIC_FFDR            (0xFFFFF144) // (AIC) Fast Forcing Disable Register
1614
#define AT91C_AIC_CISR            (0xFFFFF114) // (AIC) Core Interrupt Status Register
1615
#define AT91C_AIC_IDCR            (0xFFFFF124) // (AIC) Interrupt Disable Command Register
1616
#define AT91C_AIC_SPU             (0xFFFFF134) // (AIC) Spurious Vector Register
1617
// ========== Register definition for PDC_DBGU peripheral ========== 
1618
#define AT91C_DBGU_TCR            (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
1619
#define AT91C_DBGU_RNPR           (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
1620
#define AT91C_DBGU_TNPR           (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
1621
#define AT91C_DBGU_TPR            (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
1622
#define AT91C_DBGU_RPR            (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
1623
#define AT91C_DBGU_RCR            (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
1624
#define AT91C_DBGU_RNCR           (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
1625
#define AT91C_DBGU_PTCR           (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
1626
#define AT91C_DBGU_PTSR           (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
1627
#define AT91C_DBGU_TNCR           (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
1628
// ========== Register definition for DBGU peripheral ========== 
1629
#define AT91C_DBGU_EXID           (0xFFFFF244) // (DBGU) Chip ID Extension Register
1630
#define AT91C_DBGU_BRGR           (0xFFFFF220) // (DBGU) Baud Rate Generator Register
1631
#define AT91C_DBGU_IDR            (0xFFFFF20C) // (DBGU) Interrupt Disable Register
1632
#define AT91C_DBGU_CSR            (0xFFFFF214) // (DBGU) Channel Status Register
1633
#define AT91C_DBGU_CIDR           (0xFFFFF240) // (DBGU) Chip ID Register
1634
#define AT91C_DBGU_MR             (0xFFFFF204) // (DBGU) Mode Register
1635
#define AT91C_DBGU_IMR            (0xFFFFF210) // (DBGU) Interrupt Mask Register
1636
#define AT91C_DBGU_CR             (0xFFFFF200) // (DBGU) Control Register
1637
#define AT91C_DBGU_FNTR           (0xFFFFF248) // (DBGU) Force NTRST Register
1638
#define AT91C_DBGU_THR            (0xFFFFF21C) // (DBGU) Transmitter Holding Register
1639
#define AT91C_DBGU_RHR            (0xFFFFF218) // (DBGU) Receiver Holding Register
1640
#define AT91C_DBGU_IER            (0xFFFFF208) // (DBGU) Interrupt Enable Register
1641
// ========== Register definition for PIOA peripheral ========== 
1642
#define AT91C_PIOA_ODR            (0xFFFFF414) // (PIOA) Output Disable Registerr
1643
#define AT91C_PIOA_SODR           (0xFFFFF430) // (PIOA) Set Output Data Register
1644
#define AT91C_PIOA_ISR            (0xFFFFF44C) // (PIOA) Interrupt Status Register
1645
#define AT91C_PIOA_ABSR           (0xFFFFF478) // (PIOA) AB Select Status Register
1646
#define AT91C_PIOA_IER            (0xFFFFF440) // (PIOA) Interrupt Enable Register
1647
#define AT91C_PIOA_PPUDR          (0xFFFFF460) // (PIOA) Pull-up Disable Register
1648
#define AT91C_PIOA_IMR            (0xFFFFF448) // (PIOA) Interrupt Mask Register
1649
#define AT91C_PIOA_PER            (0xFFFFF400) // (PIOA) PIO Enable Register
1650
#define AT91C_PIOA_IFDR           (0xFFFFF424) // (PIOA) Input Filter Disable Register
1651
#define AT91C_PIOA_OWDR           (0xFFFFF4A4) // (PIOA) Output Write Disable Register
1652
#define AT91C_PIOA_MDSR           (0xFFFFF458) // (PIOA) Multi-driver Status Register
1653
#define AT91C_PIOA_IDR            (0xFFFFF444) // (PIOA) Interrupt Disable Register
1654
#define AT91C_PIOA_ODSR           (0xFFFFF438) // (PIOA) Output Data Status Register
1655
#define AT91C_PIOA_PPUSR          (0xFFFFF468) // (PIOA) Pull-up Status Register
1656
#define AT91C_PIOA_OWSR           (0xFFFFF4A8) // (PIOA) Output Write Status Register
1657
#define AT91C_PIOA_BSR            (0xFFFFF474) // (PIOA) Select B Register
1658
#define AT91C_PIOA_OWER           (0xFFFFF4A0) // (PIOA) Output Write Enable Register
1659
#define AT91C_PIOA_IFER           (0xFFFFF420) // (PIOA) Input Filter Enable Register
1660
#define AT91C_PIOA_PDSR           (0xFFFFF43C) // (PIOA) Pin Data Status Register
1661
#define AT91C_PIOA_PPUER          (0xFFFFF464) // (PIOA) Pull-up Enable Register
1662
#define AT91C_PIOA_OSR            (0xFFFFF418) // (PIOA) Output Status Register
1663
#define AT91C_PIOA_ASR            (0xFFFFF470) // (PIOA) Select A Register
1664
#define AT91C_PIOA_MDDR           (0xFFFFF454) // (PIOA) Multi-driver Disable Register
1665
#define AT91C_PIOA_CODR           (0xFFFFF434) // (PIOA) Clear Output Data Register
1666
#define AT91C_PIOA_MDER           (0xFFFFF450) // (PIOA) Multi-driver Enable Register
1667
#define AT91C_PIOA_PDR            (0xFFFFF404) // (PIOA) PIO Disable Register
1668
#define AT91C_PIOA_IFSR           (0xFFFFF428) // (PIOA) Input Filter Status Register
1669
#define AT91C_PIOA_OER            (0xFFFFF410) // (PIOA) Output Enable Register
1670
#define AT91C_PIOA_PSR            (0xFFFFF408) // (PIOA) PIO Status Register
1671
// ========== Register definition for PIOB peripheral ========== 
1672
#define AT91C_PIOB_OWDR           (0xFFFFF6A4) // (PIOB) Output Write Disable Register
1673
#define AT91C_PIOB_MDER           (0xFFFFF650) // (PIOB) Multi-driver Enable Register
1674
#define AT91C_PIOB_PPUSR          (0xFFFFF668) // (PIOB) Pull-up Status Register
1675
#define AT91C_PIOB_IMR            (0xFFFFF648) // (PIOB) Interrupt Mask Register
1676
#define AT91C_PIOB_ASR            (0xFFFFF670) // (PIOB) Select A Register
1677
#define AT91C_PIOB_PPUDR          (0xFFFFF660) // (PIOB) Pull-up Disable Register
1678
#define AT91C_PIOB_PSR            (0xFFFFF608) // (PIOB) PIO Status Register
1679
#define AT91C_PIOB_IER            (0xFFFFF640) // (PIOB) Interrupt Enable Register
1680
#define AT91C_PIOB_CODR           (0xFFFFF634) // (PIOB) Clear Output Data Register
1681
#define AT91C_PIOB_OWER           (0xFFFFF6A0) // (PIOB) Output Write Enable Register
1682
#define AT91C_PIOB_ABSR           (0xFFFFF678) // (PIOB) AB Select Status Register
1683
#define AT91C_PIOB_IFDR           (0xFFFFF624) // (PIOB) Input Filter Disable Register
1684
#define AT91C_PIOB_PDSR           (0xFFFFF63C) // (PIOB) Pin Data Status Register
1685
#define AT91C_PIOB_IDR            (0xFFFFF644) // (PIOB) Interrupt Disable Register
1686
#define AT91C_PIOB_OWSR           (0xFFFFF6A8) // (PIOB) Output Write Status Register
1687
#define AT91C_PIOB_PDR            (0xFFFFF604) // (PIOB) PIO Disable Register
1688
#define AT91C_PIOB_ODR            (0xFFFFF614) // (PIOB) Output Disable Registerr
1689
#define AT91C_PIOB_IFSR           (0xFFFFF628) // (PIOB) Input Filter Status Register
1690
#define AT91C_PIOB_PPUER          (0xFFFFF664) // (PIOB) Pull-up Enable Register
1691
#define AT91C_PIOB_SODR           (0xFFFFF630) // (PIOB) Set Output Data Register
1692
#define AT91C_PIOB_ISR            (0xFFFFF64C) // (PIOB) Interrupt Status Register
1693
#define AT91C_PIOB_ODSR           (0xFFFFF638) // (PIOB) Output Data Status Register
1694
#define AT91C_PIOB_OSR            (0xFFFFF618) // (PIOB) Output Status Register
1695
#define AT91C_PIOB_MDSR           (0xFFFFF658) // (PIOB) Multi-driver Status Register
1696
#define AT91C_PIOB_IFER           (0xFFFFF620) // (PIOB) Input Filter Enable Register
1697
#define AT91C_PIOB_BSR            (0xFFFFF674) // (PIOB) Select B Register
1698
#define AT91C_PIOB_MDDR           (0xFFFFF654) // (PIOB) Multi-driver Disable Register
1699
#define AT91C_PIOB_OER            (0xFFFFF610) // (PIOB) Output Enable Register
1700
#define AT91C_PIOB_PER            (0xFFFFF600) // (PIOB) PIO Enable Register
1701
// ========== Register definition for CKGR peripheral ========== 
1702
#define AT91C_CKGR_MOR            (0xFFFFFC20) // (CKGR) Main Oscillator Register
1703
#define AT91C_CKGR_PLLR           (0xFFFFFC2C) // (CKGR) PLL Register
1704
#define AT91C_CKGR_MCFR           (0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
1705
// ========== Register definition for PMC peripheral ========== 
1706
#define AT91C_PMC_IDR             (0xFFFFFC64) // (PMC) Interrupt Disable Register
1707
#define AT91C_PMC_MOR             (0xFFFFFC20) // (PMC) Main Oscillator Register
1708
#define AT91C_PMC_PLLR            (0xFFFFFC2C) // (PMC) PLL Register
1709
#define AT91C_PMC_PCER            (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
1710
#define AT91C_PMC_PCKR            (0xFFFFFC40) // (PMC) Programmable Clock Register
1711
#define AT91C_PMC_MCKR            (0xFFFFFC30) // (PMC) Master Clock Register
1712
#define AT91C_PMC_SCDR            (0xFFFFFC04) // (PMC) System Clock Disable Register
1713
#define AT91C_PMC_PCDR            (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
1714
#define AT91C_PMC_SCSR            (0xFFFFFC08) // (PMC) System Clock Status Register
1715
#define AT91C_PMC_PCSR            (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
1716
#define AT91C_PMC_MCFR            (0xFFFFFC24) // (PMC) Main Clock  Frequency Register
1717
#define AT91C_PMC_SCER            (0xFFFFFC00) // (PMC) System Clock Enable Register
1718
#define AT91C_PMC_IMR             (0xFFFFFC6C) // (PMC) Interrupt Mask Register
1719
#define AT91C_PMC_IER             (0xFFFFFC60) // (PMC) Interrupt Enable Register
1720
#define AT91C_PMC_SR              (0xFFFFFC68) // (PMC) Status Register
1721
// ========== Register definition for RSTC peripheral ========== 
1722
#define AT91C_RSTC_RCR            (0xFFFFFD00) // (RSTC) Reset Control Register
1723
#define AT91C_RSTC_RMR            (0xFFFFFD08) // (RSTC) Reset Mode Register
1724
#define AT91C_RSTC_RSR            (0xFFFFFD04) // (RSTC) Reset Status Register
1725
// ========== Register definition for RTTC peripheral ========== 
1726
#define AT91C_RTTC_RTSR           (0xFFFFFD2C) // (RTTC) Real-time Status Register
1727
#define AT91C_RTTC_RTMR           (0xFFFFFD20) // (RTTC) Real-time Mode Register
1728
#define AT91C_RTTC_RTVR           (0xFFFFFD28) // (RTTC) Real-time Value Register
1729
#define AT91C_RTTC_RTAR           (0xFFFFFD24) // (RTTC) Real-time Alarm Register
1730
// ========== Register definition for PITC peripheral ========== 
1731
#define AT91C_PITC_PIVR           (0xFFFFFD38) // (PITC) Period Interval Value Register
1732
#define AT91C_PITC_PISR           (0xFFFFFD34) // (PITC) Period Interval Status Register
1733
#define AT91C_PITC_PIIR           (0xFFFFFD3C) // (PITC) Period Interval Image Register
1734
#define AT91C_PITC_PIMR           (0xFFFFFD30) // (PITC) Period Interval Mode Register
1735
// ========== Register definition for WDTC peripheral ========== 
1736
#define AT91C_WDTC_WDCR           (0xFFFFFD40) // (WDTC) Watchdog Control Register
1737
#define AT91C_WDTC_WDSR           (0xFFFFFD48) // (WDTC) Watchdog Status Register
1738
#define AT91C_WDTC_WDMR           (0xFFFFFD44) // (WDTC) Watchdog Mode Register
1739
// ========== Register definition for VREG peripheral ========== 
1740
#define AT91C_VREG_MR             (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
1741
// ========== Register definition for MC peripheral ========== 
1742
#define AT91C_MC_ASR              (0xFFFFFF04) // (MC) MC Abort Status Register
1743
#define AT91C_MC_RCR              (0xFFFFFF00) // (MC) MC Remap Control Register
1744
#define AT91C_MC_FCR              (0xFFFFFF64) // (MC) MC Flash Command Register
1745
#define AT91C_MC_AASR             (0xFFFFFF08) // (MC) MC Abort Address Status Register
1746
#define AT91C_MC_FSR              (0xFFFFFF68) // (MC) MC Flash Status Register
1747
#define AT91C_MC_FMR              (0xFFFFFF60) // (MC) MC Flash Mode Register
1748
// ========== Register definition for PDC_SPI1 peripheral ========== 
1749
#define AT91C_SPI1_PTCR           (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
1750
#define AT91C_SPI1_RPR            (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
1751
#define AT91C_SPI1_TNCR           (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
1752
#define AT91C_SPI1_TPR            (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
1753
#define AT91C_SPI1_TNPR           (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
1754
#define AT91C_SPI1_TCR            (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
1755
#define AT91C_SPI1_RCR            (0xFFFE4104) // (PDC_SPI1) Receive Counter Register
1756
#define AT91C_SPI1_RNPR           (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
1757
#define AT91C_SPI1_RNCR           (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
1758
#define AT91C_SPI1_PTSR           (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
1759
// ========== Register definition for SPI1 peripheral ========== 
1760
#define AT91C_SPI1_IMR            (0xFFFE401C) // (SPI1) Interrupt Mask Register
1761
#define AT91C_SPI1_IER            (0xFFFE4014) // (SPI1) Interrupt Enable Register
1762
#define AT91C_SPI1_MR             (0xFFFE4004) // (SPI1) Mode Register
1763
#define AT91C_SPI1_RDR            (0xFFFE4008) // (SPI1) Receive Data Register
1764
#define AT91C_SPI1_IDR            (0xFFFE4018) // (SPI1) Interrupt Disable Register
1765
#define AT91C_SPI1_SR             (0xFFFE4010) // (SPI1) Status Register
1766
#define AT91C_SPI1_TDR            (0xFFFE400C) // (SPI1) Transmit Data Register
1767
#define AT91C_SPI1_CR             (0xFFFE4000) // (SPI1) Control Register
1768
#define AT91C_SPI1_CSR            (0xFFFE4030) // (SPI1) Chip Select Register
1769
// ========== Register definition for PDC_SPI0 peripheral ========== 
1770
#define AT91C_SPI0_PTCR           (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
1771
#define AT91C_SPI0_TPR            (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
1772
#define AT91C_SPI0_TCR            (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
1773
#define AT91C_SPI0_RCR            (0xFFFE0104) // (PDC_SPI0) Receive Counter Register
1774
#define AT91C_SPI0_PTSR           (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
1775
#define AT91C_SPI0_RNPR           (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
1776
#define AT91C_SPI0_RPR            (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
1777
#define AT91C_SPI0_TNCR           (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
1778
#define AT91C_SPI0_RNCR           (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
1779
#define AT91C_SPI0_TNPR           (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
1780
// ========== Register definition for SPI0 peripheral ========== 
1781
#define AT91C_SPI0_IER            (0xFFFE0014) // (SPI0) Interrupt Enable Register
1782
#define AT91C_SPI0_SR             (0xFFFE0010) // (SPI0) Status Register
1783
#define AT91C_SPI0_IDR            (0xFFFE0018) // (SPI0) Interrupt Disable Register
1784
#define AT91C_SPI0_CR             (0xFFFE0000) // (SPI0) Control Register
1785
#define AT91C_SPI0_MR             (0xFFFE0004) // (SPI0) Mode Register
1786
#define AT91C_SPI0_IMR            (0xFFFE001C) // (SPI0) Interrupt Mask Register
1787
#define AT91C_SPI0_TDR            (0xFFFE000C) // (SPI0) Transmit Data Register
1788
#define AT91C_SPI0_RDR            (0xFFFE0008) // (SPI0) Receive Data Register
1789
#define AT91C_SPI0_CSR            (0xFFFE0030) // (SPI0) Chip Select Register
1790
// ========== Register definition for PDC_US1 peripheral ========== 
1791
#define AT91C_US1_RNCR            (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
1792
#define AT91C_US1_PTCR            (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
1793
#define AT91C_US1_TCR             (0xFFFC410C) // (PDC_US1) Transmit Counter Register
1794
#define AT91C_US1_PTSR            (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
1795
#define AT91C_US1_TNPR            (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
1796
#define AT91C_US1_RCR             (0xFFFC4104) // (PDC_US1) Receive Counter Register
1797
#define AT91C_US1_RNPR            (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
1798
#define AT91C_US1_RPR             (0xFFFC4100) // (PDC_US1) Receive Pointer Register
1799
#define AT91C_US1_TNCR            (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
1800
#define AT91C_US1_TPR             (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
1801
// ========== Register definition for US1 peripheral ========== 
1802
#define AT91C_US1_IF              (0xFFFC404C) // (US1) IRDA_FILTER Register
1803
#define AT91C_US1_NER             (0xFFFC4044) // (US1) Nb Errors Register
1804
#define AT91C_US1_RTOR            (0xFFFC4024) // (US1) Receiver Time-out Register
1805
#define AT91C_US1_CSR             (0xFFFC4014) // (US1) Channel Status Register
1806
#define AT91C_US1_IDR             (0xFFFC400C) // (US1) Interrupt Disable Register
1807
#define AT91C_US1_IER             (0xFFFC4008) // (US1) Interrupt Enable Register
1808
#define AT91C_US1_THR             (0xFFFC401C) // (US1) Transmitter Holding Register
1809
#define AT91C_US1_TTGR            (0xFFFC4028) // (US1) Transmitter Time-guard Register
1810
#define AT91C_US1_RHR             (0xFFFC4018) // (US1) Receiver Holding Register
1811
#define AT91C_US1_BRGR            (0xFFFC4020) // (US1) Baud Rate Generator Register
1812
#define AT91C_US1_IMR             (0xFFFC4010) // (US1) Interrupt Mask Register
1813
#define AT91C_US1_FIDI            (0xFFFC4040) // (US1) FI_DI_Ratio Register
1814
#define AT91C_US1_CR              (0xFFFC4000) // (US1) Control Register
1815
#define AT91C_US1_MR              (0xFFFC4004) // (US1) Mode Register
1816
// ========== Register definition for PDC_US0 peripheral ========== 
1817
#define AT91C_US0_TNPR            (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
1818
#define AT91C_US0_RNPR            (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
1819
#define AT91C_US0_TCR             (0xFFFC010C) // (PDC_US0) Transmit Counter Register
1820
#define AT91C_US0_PTCR            (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
1821
#define AT91C_US0_PTSR            (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
1822
#define AT91C_US0_TNCR            (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
1823
#define AT91C_US0_TPR             (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
1824
#define AT91C_US0_RCR             (0xFFFC0104) // (PDC_US0) Receive Counter Register
1825
#define AT91C_US0_RPR             (0xFFFC0100) // (PDC_US0) Receive Pointer Register
1826
#define AT91C_US0_RNCR            (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
1827
// ========== Register definition for US0 peripheral ========== 
1828
#define AT91C_US0_BRGR            (0xFFFC0020) // (US0) Baud Rate Generator Register
1829
#define AT91C_US0_NER             (0xFFFC0044) // (US0) Nb Errors Register
1830
#define AT91C_US0_CR              (0xFFFC0000) // (US0) Control Register
1831
#define AT91C_US0_IMR             (0xFFFC0010) // (US0) Interrupt Mask Register
1832
#define AT91C_US0_FIDI            (0xFFFC0040) // (US0) FI_DI_Ratio Register
1833
#define AT91C_US0_TTGR            (0xFFFC0028) // (US0) Transmitter Time-guard Register
1834
#define AT91C_US0_MR              (0xFFFC0004) // (US0) Mode Register
1835
#define AT91C_US0_RTOR            (0xFFFC0024) // (US0) Receiver Time-out Register
1836
#define AT91C_US0_CSR             (0xFFFC0014) // (US0) Channel Status Register
1837
#define AT91C_US0_RHR             (0xFFFC0018) // (US0) Receiver Holding Register
1838
#define AT91C_US0_IDR             (0xFFFC000C) // (US0) Interrupt Disable Register
1839
#define AT91C_US0_THR             (0xFFFC001C) // (US0) Transmitter Holding Register
1840
#define AT91C_US0_IF              (0xFFFC004C) // (US0) IRDA_FILTER Register
1841
#define AT91C_US0_IER             (0xFFFC0008) // (US0) Interrupt Enable Register
1842
// ========== Register definition for PDC_SSC peripheral ========== 
1843
#define AT91C_SSC_TNCR            (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
1844
#define AT91C_SSC_RPR             (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
1845
#define AT91C_SSC_RNCR            (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
1846
#define AT91C_SSC_TPR             (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
1847
#define AT91C_SSC_PTCR            (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
1848
#define AT91C_SSC_TCR             (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
1849
#define AT91C_SSC_RCR             (0xFFFD4104) // (PDC_SSC) Receive Counter Register
1850
#define AT91C_SSC_RNPR            (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
1851
#define AT91C_SSC_TNPR            (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
1852
#define AT91C_SSC_PTSR            (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
1853
// ========== Register definition for SSC peripheral ========== 
1854
#define AT91C_SSC_RHR             (0xFFFD4020) // (SSC) Receive Holding Register
1855
#define AT91C_SSC_RSHR            (0xFFFD4030) // (SSC) Receive Sync Holding Register
1856
#define AT91C_SSC_TFMR            (0xFFFD401C) // (SSC) Transmit Frame Mode Register
1857
#define AT91C_SSC_IDR             (0xFFFD4048) // (SSC) Interrupt Disable Register
1858
#define AT91C_SSC_THR             (0xFFFD4024) // (SSC) Transmit Holding Register
1859
#define AT91C_SSC_RCMR            (0xFFFD4010) // (SSC) Receive Clock ModeRegister
1860
#define AT91C_SSC_IER             (0xFFFD4044) // (SSC) Interrupt Enable Register
1861
#define AT91C_SSC_TSHR            (0xFFFD4034) // (SSC) Transmit Sync Holding Register
1862
#define AT91C_SSC_SR              (0xFFFD4040) // (SSC) Status Register
1863
#define AT91C_SSC_CMR             (0xFFFD4004) // (SSC) Clock Mode Register
1864
#define AT91C_SSC_TCMR            (0xFFFD4018) // (SSC) Transmit Clock Mode Register
1865
#define AT91C_SSC_CR              (0xFFFD4000) // (SSC) Control Register
1866
#define AT91C_SSC_IMR             (0xFFFD404C) // (SSC) Interrupt Mask Register
1867
#define AT91C_SSC_RFMR            (0xFFFD4014) // (SSC) Receive Frame Mode Register
1868
// ========== Register definition for TWI peripheral ========== 
1869
#define AT91C_TWI_IER             (0xFFFB8024) // (TWI) Interrupt Enable Register
1870
#define AT91C_TWI_CR              (0xFFFB8000) // (TWI) Control Register
1871
#define AT91C_TWI_SR              (0xFFFB8020) // (TWI) Status Register
1872
#define AT91C_TWI_IMR             (0xFFFB802C) // (TWI) Interrupt Mask Register
1873
#define AT91C_TWI_THR             (0xFFFB8034) // (TWI) Transmit Holding Register
1874
#define AT91C_TWI_IDR             (0xFFFB8028) // (TWI) Interrupt Disable Register
1875
#define AT91C_TWI_IADR            (0xFFFB800C) // (TWI) Internal Address Register
1876
#define AT91C_TWI_MMR             (0xFFFB8004) // (TWI) Master Mode Register
1877
#define AT91C_TWI_CWGR            (0xFFFB8010) // (TWI) Clock Waveform Generator Register
1878
#define AT91C_TWI_RHR             (0xFFFB8030) // (TWI) Receive Holding Register
1879
// ========== Register definition for PWMC_CH3 peripheral ========== 
1880
#define AT91C_PWMC_CH3_CUPDR      (0xFFFCC270) // (PWMC_CH3) Channel Update Register
1881
#define AT91C_PWMC_CH3_Reserved   (0xFFFCC274) // (PWMC_CH3) Reserved
1882
#define AT91C_PWMC_CH3_CPRDR      (0xFFFCC268) // (PWMC_CH3) Channel Period Register
1883
#define AT91C_PWMC_CH3_CDTYR      (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
1884
#define AT91C_PWMC_CH3_CCNTR      (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
1885
#define AT91C_PWMC_CH3_CMR        (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
1886
// ========== Register definition for PWMC_CH2 peripheral ========== 
1887
#define AT91C_PWMC_CH2_Reserved   (0xFFFCC254) // (PWMC_CH2) Reserved
1888
#define AT91C_PWMC_CH2_CMR        (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
1889
#define AT91C_PWMC_CH2_CCNTR      (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
1890
#define AT91C_PWMC_CH2_CPRDR      (0xFFFCC248) // (PWMC_CH2) Channel Period Register
1891
#define AT91C_PWMC_CH2_CUPDR      (0xFFFCC250) // (PWMC_CH2) Channel Update Register
1892
#define AT91C_PWMC_CH2_CDTYR      (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
1893
// ========== Register definition for PWMC_CH1 peripheral ========== 
1894
#define AT91C_PWMC_CH1_Reserved   (0xFFFCC234) // (PWMC_CH1) Reserved
1895
#define AT91C_PWMC_CH1_CUPDR      (0xFFFCC230) // (PWMC_CH1) Channel Update Register
1896
#define AT91C_PWMC_CH1_CPRDR      (0xFFFCC228) // (PWMC_CH1) Channel Period Register
1897
#define AT91C_PWMC_CH1_CCNTR      (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
1898
#define AT91C_PWMC_CH1_CDTYR      (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
1899
#define AT91C_PWMC_CH1_CMR        (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
1900
// ========== Register definition for PWMC_CH0 peripheral ========== 
1901
#define AT91C_PWMC_CH0_Reserved   (0xFFFCC214) // (PWMC_CH0) Reserved
1902
#define AT91C_PWMC_CH0_CPRDR      (0xFFFCC208) // (PWMC_CH0) Channel Period Register
1903
#define AT91C_PWMC_CH0_CDTYR      (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
1904
#define AT91C_PWMC_CH0_CMR        (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
1905
#define AT91C_PWMC_CH0_CUPDR      (0xFFFCC210) // (PWMC_CH0) Channel Update Register
1906
#define AT91C_PWMC_CH0_CCNTR      (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
1907
// ========== Register definition for PWMC peripheral ========== 
1908
#define AT91C_PWMC_IDR            (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
1909
#define AT91C_PWMC_DIS            (0xFFFCC008) // (PWMC) PWMC Disable Register
1910
#define AT91C_PWMC_IER            (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
1911
#define AT91C_PWMC_VR             (0xFFFCC0FC) // (PWMC) PWMC Version Register
1912
#define AT91C_PWMC_ISR            (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
1913
#define AT91C_PWMC_SR             (0xFFFCC00C) // (PWMC) PWMC Status Register
1914
#define AT91C_PWMC_IMR            (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
1915
#define AT91C_PWMC_MR             (0xFFFCC000) // (PWMC) PWMC Mode Register
1916
#define AT91C_PWMC_ENA            (0xFFFCC004) // (PWMC) PWMC Enable Register
1917
// ========== Register definition for UDP peripheral ========== 
1918
#define AT91C_UDP_IMR             (0xFFFB0018) // (UDP) Interrupt Mask Register
1919
#define AT91C_UDP_FADDR           (0xFFFB0008) // (UDP) Function Address Register
1920
#define AT91C_UDP_NUM             (0xFFFB0000) // (UDP) Frame Number Register
1921
#define AT91C_UDP_FDR             (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
1922
#define AT91C_UDP_ISR             (0xFFFB001C) // (UDP) Interrupt Status Register
1923
#define AT91C_UDP_CSR             (0xFFFB0030) // (UDP) Endpoint Control and Status Register
1924
#define AT91C_UDP_IDR             (0xFFFB0014) // (UDP) Interrupt Disable Register
1925
#define AT91C_UDP_ICR             (0xFFFB0020) // (UDP) Interrupt Clear Register
1926
#define AT91C_UDP_RSTEP           (0xFFFB0028) // (UDP) Reset Endpoint Register
1927
#define AT91C_UDP_TXVC            (0xFFFB0074) // (UDP) Transceiver Control Register
1928
#define AT91C_UDP_GLBSTATE        (0xFFFB0004) // (UDP) Global State Register
1929
#define AT91C_UDP_IER             (0xFFFB0010) // (UDP) Interrupt Enable Register
1930
// ========== Register definition for TC0 peripheral ========== 
1931
#define AT91C_TC0_SR              (0xFFFA0020) // (TC0) Status Register
1932
#define AT91C_TC0_RC              (0xFFFA001C) // (TC0) Register C
1933
#define AT91C_TC0_RB              (0xFFFA0018) // (TC0) Register B
1934
#define AT91C_TC0_CCR             (0xFFFA0000) // (TC0) Channel Control Register
1935
#define AT91C_TC0_CMR             (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
1936
#define AT91C_TC0_IER             (0xFFFA0024) // (TC0) Interrupt Enable Register
1937
#define AT91C_TC0_RA              (0xFFFA0014) // (TC0) Register A
1938
#define AT91C_TC0_IDR             (0xFFFA0028) // (TC0) Interrupt Disable Register
1939
#define AT91C_TC0_CV              (0xFFFA0010) // (TC0) Counter Value
1940
#define AT91C_TC0_IMR             (0xFFFA002C) // (TC0) Interrupt Mask Register
1941
// ========== Register definition for TC1 peripheral ========== 
1942
#define AT91C_TC1_RB              (0xFFFA0058) // (TC1) Register B
1943
#define AT91C_TC1_CCR             (0xFFFA0040) // (TC1) Channel Control Register
1944
#define AT91C_TC1_IER             (0xFFFA0064) // (TC1) Interrupt Enable Register
1945
#define AT91C_TC1_IDR             (0xFFFA0068) // (TC1) Interrupt Disable Register
1946
#define AT91C_TC1_SR              (0xFFFA0060) // (TC1) Status Register
1947
#define AT91C_TC1_CMR             (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
1948
#define AT91C_TC1_RA              (0xFFFA0054) // (TC1) Register A
1949
#define AT91C_TC1_RC              (0xFFFA005C) // (TC1) Register C
1950
#define AT91C_TC1_IMR             (0xFFFA006C) // (TC1) Interrupt Mask Register
1951
#define AT91C_TC1_CV              (0xFFFA0050) // (TC1) Counter Value
1952
// ========== Register definition for TC2 peripheral ========== 
1953
#define AT91C_TC2_CMR             (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
1954
#define AT91C_TC2_CCR             (0xFFFA0080) // (TC2) Channel Control Register
1955
#define AT91C_TC2_CV              (0xFFFA0090) // (TC2) Counter Value
1956
#define AT91C_TC2_RA              (0xFFFA0094) // (TC2) Register A
1957
#define AT91C_TC2_RB              (0xFFFA0098) // (TC2) Register B
1958
#define AT91C_TC2_IDR             (0xFFFA00A8) // (TC2) Interrupt Disable Register
1959
#define AT91C_TC2_IMR             (0xFFFA00AC) // (TC2) Interrupt Mask Register
1960
#define AT91C_TC2_RC              (0xFFFA009C) // (TC2) Register C
1961
#define AT91C_TC2_IER             (0xFFFA00A4) // (TC2) Interrupt Enable Register
1962
#define AT91C_TC2_SR              (0xFFFA00A0) // (TC2) Status Register
1963
// ========== Register definition for TCB peripheral ========== 
1964
#define AT91C_TCB_BMR             (0xFFFA00C4) // (TCB) TC Block Mode Register
1965
#define AT91C_TCB_BCR             (0xFFFA00C0) // (TCB) TC Block Control Register
1966
// ========== Register definition for CAN_MB0 peripheral ========== 
1967
#define AT91C_CAN_MB0_MDL         (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
1968
#define AT91C_CAN_MB0_MAM         (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
1969
#define AT91C_CAN_MB0_MCR         (0xFFFD021C) // (CAN_MB0) MailBox Control Register
1970
#define AT91C_CAN_MB0_MID         (0xFFFD0208) // (CAN_MB0) MailBox ID Register
1971
#define AT91C_CAN_MB0_MSR         (0xFFFD0210) // (CAN_MB0) MailBox Status Register
1972
#define AT91C_CAN_MB0_MFID        (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
1973
#define AT91C_CAN_MB0_MDH         (0xFFFD0218) // (CAN_MB0) MailBox Data High Register
1974
#define AT91C_CAN_MB0_MMR         (0xFFFD0200) // (CAN_MB0) MailBox Mode Register
1975
// ========== Register definition for CAN_MB1 peripheral ========== 
1976
#define AT91C_CAN_MB1_MDL         (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
1977
#define AT91C_CAN_MB1_MID         (0xFFFD0228) // (CAN_MB1) MailBox ID Register
1978
#define AT91C_CAN_MB1_MMR         (0xFFFD0220) // (CAN_MB1) MailBox Mode Register
1979
#define AT91C_CAN_MB1_MSR         (0xFFFD0230) // (CAN_MB1) MailBox Status Register
1980
#define AT91C_CAN_MB1_MAM         (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
1981
#define AT91C_CAN_MB1_MDH         (0xFFFD0238) // (CAN_MB1) MailBox Data High Register
1982
#define AT91C_CAN_MB1_MCR         (0xFFFD023C) // (CAN_MB1) MailBox Control Register
1983
#define AT91C_CAN_MB1_MFID        (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
1984
// ========== Register definition for CAN_MB2 peripheral ========== 
1985
#define AT91C_CAN_MB2_MCR         (0xFFFD025C) // (CAN_MB2) MailBox Control Register
1986
#define AT91C_CAN_MB2_MDH         (0xFFFD0258) // (CAN_MB2) MailBox Data High Register
1987
#define AT91C_CAN_MB2_MID         (0xFFFD0248) // (CAN_MB2) MailBox ID Register
1988
#define AT91C_CAN_MB2_MDL         (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
1989
#define AT91C_CAN_MB2_MMR         (0xFFFD0240) // (CAN_MB2) MailBox Mode Register
1990
#define AT91C_CAN_MB2_MAM         (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
1991
#define AT91C_CAN_MB2_MFID        (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
1992
#define AT91C_CAN_MB2_MSR         (0xFFFD0250) // (CAN_MB2) MailBox Status Register
1993
// ========== Register definition for CAN_MB3 peripheral ========== 
1994
#define AT91C_CAN_MB3_MFID        (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
1995
#define AT91C_CAN_MB3_MAM         (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
1996
#define AT91C_CAN_MB3_MID         (0xFFFD0268) // (CAN_MB3) MailBox ID Register
1997
#define AT91C_CAN_MB3_MCR         (0xFFFD027C) // (CAN_MB3) MailBox Control Register
1998
#define AT91C_CAN_MB3_MMR         (0xFFFD0260) // (CAN_MB3) MailBox Mode Register
1999
#define AT91C_CAN_MB3_MSR         (0xFFFD0270) // (CAN_MB3) MailBox Status Register
2000
#define AT91C_CAN_MB3_MDL         (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
2001
#define AT91C_CAN_MB3_MDH         (0xFFFD0278) // (CAN_MB3) MailBox Data High Register
2002
// ========== Register definition for CAN_MB4 peripheral ========== 
2003
#define AT91C_CAN_MB4_MID         (0xFFFD0288) // (CAN_MB4) MailBox ID Register
2004
#define AT91C_CAN_MB4_MMR         (0xFFFD0280) // (CAN_MB4) MailBox Mode Register
2005
#define AT91C_CAN_MB4_MDH         (0xFFFD0298) // (CAN_MB4) MailBox Data High Register
2006
#define AT91C_CAN_MB4_MFID        (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
2007
#define AT91C_CAN_MB4_MSR         (0xFFFD0290) // (CAN_MB4) MailBox Status Register
2008
#define AT91C_CAN_MB4_MCR         (0xFFFD029C) // (CAN_MB4) MailBox Control Register
2009
#define AT91C_CAN_MB4_MDL         (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
2010
#define AT91C_CAN_MB4_MAM         (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
2011
// ========== Register definition for CAN_MB5 peripheral ========== 
2012
#define AT91C_CAN_MB5_MSR         (0xFFFD02B0) // (CAN_MB5) MailBox Status Register
2013
#define AT91C_CAN_MB5_MCR         (0xFFFD02BC) // (CAN_MB5) MailBox Control Register
2014
#define AT91C_CAN_MB5_MFID        (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
2015
#define AT91C_CAN_MB5_MDH         (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
2016
#define AT91C_CAN_MB5_MID         (0xFFFD02A8) // (CAN_MB5) MailBox ID Register
2017
#define AT91C_CAN_MB5_MMR         (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
2018
#define AT91C_CAN_MB5_MDL         (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
2019
#define AT91C_CAN_MB5_MAM         (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
2020
// ========== Register definition for CAN_MB6 peripheral ========== 
2021
#define AT91C_CAN_MB6_MFID        (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
2022
#define AT91C_CAN_MB6_MID         (0xFFFD02C8) // (CAN_MB6) MailBox ID Register
2023
#define AT91C_CAN_MB6_MAM         (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
2024
#define AT91C_CAN_MB6_MSR         (0xFFFD02D0) // (CAN_MB6) MailBox Status Register
2025
#define AT91C_CAN_MB6_MDL         (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
2026
#define AT91C_CAN_MB6_MCR         (0xFFFD02DC) // (CAN_MB6) MailBox Control Register
2027
#define AT91C_CAN_MB6_MDH         (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
2028
#define AT91C_CAN_MB6_MMR         (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
2029
// ========== Register definition for CAN_MB7 peripheral ========== 
2030
#define AT91C_CAN_MB7_MCR         (0xFFFD02FC) // (CAN_MB7) MailBox Control Register
2031
#define AT91C_CAN_MB7_MDH         (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
2032
#define AT91C_CAN_MB7_MFID        (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
2033
#define AT91C_CAN_MB7_MDL         (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
2034
#define AT91C_CAN_MB7_MID         (0xFFFD02E8) // (CAN_MB7) MailBox ID Register
2035
#define AT91C_CAN_MB7_MMR         (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
2036
#define AT91C_CAN_MB7_MAM         (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
2037
#define AT91C_CAN_MB7_MSR         (0xFFFD02F0) // (CAN_MB7) MailBox Status Register
2038
// ========== Register definition for CAN peripheral ========== 
2039
#define AT91C_CAN_TCR             (0xFFFD0024) // (CAN) Transfer Command Register
2040
#define AT91C_CAN_IMR             (0xFFFD000C) // (CAN) Interrupt Mask Register
2041
#define AT91C_CAN_IER             (0xFFFD0004) // (CAN) Interrupt Enable Register
2042
#define AT91C_CAN_ECR             (0xFFFD0020) // (CAN) Error Counter Register
2043
#define AT91C_CAN_TIMESTP         (0xFFFD001C) // (CAN) Time Stamp Register
2044
#define AT91C_CAN_MR              (0xFFFD0000) // (CAN) Mode Register
2045
#define AT91C_CAN_IDR             (0xFFFD0008) // (CAN) Interrupt Disable Register
2046
#define AT91C_CAN_ACR             (0xFFFD0028) // (CAN) Abort Command Register
2047
#define AT91C_CAN_TIM             (0xFFFD0018) // (CAN) Timer Register
2048
#define AT91C_CAN_SR              (0xFFFD0010) // (CAN) Status Register
2049
#define AT91C_CAN_BR              (0xFFFD0014) // (CAN) Baudrate Register
2050
#define AT91C_CAN_VR              (0xFFFD00FC) // (CAN) Version Register
2051
// ========== Register definition for EMAC peripheral ========== 
2052
#define AT91C_EMAC_ISR            (0xFFFDC024) // (EMAC) Interrupt Status Register
2053
#define AT91C_EMAC_SA4H           (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
2054
#define AT91C_EMAC_SA1L           (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
2055
#define AT91C_EMAC_ELE            (0xFFFDC078) // (EMAC) Excessive Length Errors Register
2056
#define AT91C_EMAC_LCOL           (0xFFFDC05C) // (EMAC) Late Collision Register
2057
#define AT91C_EMAC_RLE            (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
2058
#define AT91C_EMAC_WOL            (0xFFFDC0C4) // (EMAC) Wake On LAN Register
2059
#define AT91C_EMAC_DTF            (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
2060
#define AT91C_EMAC_TUND           (0xFFFDC064) // (EMAC) Transmit Underrun Error Register
2061
#define AT91C_EMAC_NCR            (0xFFFDC000) // (EMAC) Network Control Register
2062
#define AT91C_EMAC_SA4L           (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
2063
#define AT91C_EMAC_RSR            (0xFFFDC020) // (EMAC) Receive Status Register
2064
#define AT91C_EMAC_SA3L           (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
2065
#define AT91C_EMAC_TSR            (0xFFFDC014) // (EMAC) Transmit Status Register
2066
#define AT91C_EMAC_IDR            (0xFFFDC02C) // (EMAC) Interrupt Disable Register
2067
#define AT91C_EMAC_RSE            (0xFFFDC074) // (EMAC) Receive Symbol Errors Register
2068
#define AT91C_EMAC_ECOL           (0xFFFDC060) // (EMAC) Excessive Collision Register
2069
#define AT91C_EMAC_TID            (0xFFFDC0B8) // (EMAC) Type ID Checking Register
2070
#define AT91C_EMAC_HRB            (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
2071
#define AT91C_EMAC_TBQP           (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
2072
#define AT91C_EMAC_USRIO          (0xFFFDC0C0) // (EMAC) USER Input/Output Register
2073
#define AT91C_EMAC_PTR            (0xFFFDC038) // (EMAC) Pause Time Register
2074
#define AT91C_EMAC_SA2H           (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
2075
#define AT91C_EMAC_ROV            (0xFFFDC070) // (EMAC) Receive Overrun Errors Register
2076
#define AT91C_EMAC_ALE            (0xFFFDC054) // (EMAC) Alignment Error Register
2077
#define AT91C_EMAC_RJA            (0xFFFDC07C) // (EMAC) Receive Jabbers Register
2078
#define AT91C_EMAC_RBQP           (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
2079
#define AT91C_EMAC_TPF            (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
2080
#define AT91C_EMAC_NCFGR          (0xFFFDC004) // (EMAC) Network Configuration Register
2081
#define AT91C_EMAC_HRT            (0xFFFDC094) // (EMAC) Hash Address Top[63:32]
2082
#define AT91C_EMAC_USF            (0xFFFDC080) // (EMAC) Undersize Frames Register
2083
#define AT91C_EMAC_FCSE           (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
2084
#define AT91C_EMAC_TPQ            (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
2085
#define AT91C_EMAC_MAN            (0xFFFDC034) // (EMAC) PHY Maintenance Register
2086
#define AT91C_EMAC_FTO            (0xFFFDC040) // (EMAC) Frames Transmitted OK Register
2087
#define AT91C_EMAC_REV            (0xFFFDC0FC) // (EMAC) Revision Register
2088
#define AT91C_EMAC_IMR            (0xFFFDC030) // (EMAC) Interrupt Mask Register
2089
#define AT91C_EMAC_SCF            (0xFFFDC044) // (EMAC) Single Collision Frame Register
2090
#define AT91C_EMAC_PFR            (0xFFFDC03C) // (EMAC) Pause Frames received Register
2091
#define AT91C_EMAC_MCF            (0xFFFDC048) // (EMAC) Multiple Collision Frame Register
2092
#define AT91C_EMAC_NSR            (0xFFFDC008) // (EMAC) Network Status Register
2093
#define AT91C_EMAC_SA2L           (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
2094
#define AT91C_EMAC_FRO            (0xFFFDC04C) // (EMAC) Frames Received OK Register
2095
#define AT91C_EMAC_IER            (0xFFFDC028) // (EMAC) Interrupt Enable Register
2096
#define AT91C_EMAC_SA1H           (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
2097
#define AT91C_EMAC_CSE            (0xFFFDC068) // (EMAC) Carrier Sense Error Register
2098
#define AT91C_EMAC_SA3H           (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
2099
#define AT91C_EMAC_RRE            (0xFFFDC06C) // (EMAC) Receive Ressource Error Register
2100
#define AT91C_EMAC_STE            (0xFFFDC084) // (EMAC) SQE Test Error Register
2101
// ========== Register definition for PDC_ADC peripheral ========== 
2102
#define AT91C_ADC_PTSR            (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
2103
#define AT91C_ADC_PTCR            (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
2104
#define AT91C_ADC_TNPR            (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
2105
#define AT91C_ADC_TNCR            (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
2106
#define AT91C_ADC_RNPR            (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
2107
#define AT91C_ADC_RNCR            (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
2108
#define AT91C_ADC_RPR             (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
2109
#define AT91C_ADC_TCR             (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
2110
#define AT91C_ADC_TPR             (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
2111
#define AT91C_ADC_RCR             (0xFFFD8104) // (PDC_ADC) Receive Counter Register
2112
// ========== Register definition for ADC peripheral ========== 
2113
#define AT91C_ADC_CDR2            (0xFFFD8038) // (ADC) ADC Channel Data Register 2
2114
#define AT91C_ADC_CDR3            (0xFFFD803C) // (ADC) ADC Channel Data Register 3
2115
#define AT91C_ADC_CDR0            (0xFFFD8030) // (ADC) ADC Channel Data Register 0
2116
#define AT91C_ADC_CDR5            (0xFFFD8044) // (ADC) ADC Channel Data Register 5
2117
#define AT91C_ADC_CHDR            (0xFFFD8014) // (ADC) ADC Channel Disable Register
2118
#define AT91C_ADC_SR              (0xFFFD801C) // (ADC) ADC Status Register
2119
#define AT91C_ADC_CDR4            (0xFFFD8040) // (ADC) ADC Channel Data Register 4
2120
#define AT91C_ADC_CDR1            (0xFFFD8034) // (ADC) ADC Channel Data Register 1
2121
#define AT91C_ADC_LCDR            (0xFFFD8020) // (ADC) ADC Last Converted Data Register
2122
#define AT91C_ADC_IDR             (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
2123
#define AT91C_ADC_CR              (0xFFFD8000) // (ADC) ADC Control Register
2124
#define AT91C_ADC_CDR7            (0xFFFD804C) // (ADC) ADC Channel Data Register 7
2125
#define AT91C_ADC_CDR6            (0xFFFD8048) // (ADC) ADC Channel Data Register 6
2126
#define AT91C_ADC_IER             (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
2127
#define AT91C_ADC_CHER            (0xFFFD8010) // (ADC) ADC Channel Enable Register
2128
#define AT91C_ADC_CHSR            (0xFFFD8018) // (ADC) ADC Channel Status Register
2129
#define AT91C_ADC_MR              (0xFFFD8004) // (ADC) ADC Mode Register
2130
#define AT91C_ADC_IMR             (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
2131
// ========== Register definition for PDC_AES peripheral ========== 
2132
#define AT91C_AES_TPR             (0xFFFA4108) // (PDC_AES) Transmit Pointer Register
2133
#define AT91C_AES_PTCR            (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
2134
#define AT91C_AES_RNPR            (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
2135
#define AT91C_AES_TNCR            (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
2136
#define AT91C_AES_TCR             (0xFFFA410C) // (PDC_AES) Transmit Counter Register
2137
#define AT91C_AES_RCR             (0xFFFA4104) // (PDC_AES) Receive Counter Register
2138
#define AT91C_AES_RNCR            (0xFFFA4114) // (PDC_AES) Receive Next Counter Register
2139
#define AT91C_AES_TNPR            (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
2140
#define AT91C_AES_RPR             (0xFFFA4100) // (PDC_AES) Receive Pointer Register
2141
#define AT91C_AES_PTSR            (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
2142
// ========== Register definition for AES peripheral ========== 
2143
#define AT91C_AES_IVxR            (0xFFFA4060) // (AES) Initialization Vector x Register
2144
#define AT91C_AES_MR              (0xFFFA4004) // (AES) Mode Register
2145
#define AT91C_AES_VR              (0xFFFA40FC) // (AES) AES Version Register
2146
#define AT91C_AES_ODATAxR         (0xFFFA4050) // (AES) Output Data x Register
2147
#define AT91C_AES_IDATAxR         (0xFFFA4040) // (AES) Input Data x Register
2148
#define AT91C_AES_CR              (0xFFFA4000) // (AES) Control Register
2149
#define AT91C_AES_IDR             (0xFFFA4014) // (AES) Interrupt Disable Register
2150
#define AT91C_AES_IMR             (0xFFFA4018) // (AES) Interrupt Mask Register
2151
#define AT91C_AES_IER             (0xFFFA4010) // (AES) Interrupt Enable Register
2152
#define AT91C_AES_KEYWxR          (0xFFFA4020) // (AES) Key Word x Register
2153
#define AT91C_AES_ISR             (0xFFFA401C) // (AES) Interrupt Status Register
2154
// ========== Register definition for PDC_TDES peripheral ========== 
2155
#define AT91C_TDES_RNCR           (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
2156
#define AT91C_TDES_TCR            (0xFFFA810C) // (PDC_TDES) Transmit Counter Register
2157
#define AT91C_TDES_RCR            (0xFFFA8104) // (PDC_TDES) Receive Counter Register
2158
#define AT91C_TDES_TNPR           (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
2159
#define AT91C_TDES_RNPR           (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
2160
#define AT91C_TDES_RPR            (0xFFFA8100) // (PDC_TDES) Receive Pointer Register
2161
#define AT91C_TDES_TNCR           (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
2162
#define AT91C_TDES_TPR            (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
2163
#define AT91C_TDES_PTSR           (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
2164
#define AT91C_TDES_PTCR           (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
2165
// ========== Register definition for TDES peripheral ========== 
2166
#define AT91C_TDES_KEY2WxR        (0xFFFA8028) // (TDES) Key 2 Word x Register
2167
#define AT91C_TDES_KEY3WxR        (0xFFFA8030) // (TDES) Key 3 Word x Register
2168
#define AT91C_TDES_IDR            (0xFFFA8014) // (TDES) Interrupt Disable Register
2169
#define AT91C_TDES_VR             (0xFFFA80FC) // (TDES) TDES Version Register
2170
#define AT91C_TDES_IVxR           (0xFFFA8060) // (TDES) Initialization Vector x Register
2171
#define AT91C_TDES_ODATAxR        (0xFFFA8050) // (TDES) Output Data x Register
2172
#define AT91C_TDES_IMR            (0xFFFA8018) // (TDES) Interrupt Mask Register
2173
#define AT91C_TDES_MR             (0xFFFA8004) // (TDES) Mode Register
2174
#define AT91C_TDES_CR             (0xFFFA8000) // (TDES) Control Register
2175
#define AT91C_TDES_IER            (0xFFFA8010) // (TDES) Interrupt Enable Register
2176
#define AT91C_TDES_ISR            (0xFFFA801C) // (TDES) Interrupt Status Register
2177
#define AT91C_TDES_IDATAxR        (0xFFFA8040) // (TDES) Input Data x Register
2178
#define AT91C_TDES_KEY1WxR        (0xFFFA8020) // (TDES) Key 1 Word x Register
2179
 
2180
// *****************************************************************************
2181
//               PIO DEFINITIONS FOR AT91SAM7X256
2182
// *****************************************************************************
2183
#define AT91C_PIO_PA0             (1 <<  0) // Pin Controlled by PA0
2184
#define AT91C_PA0_RXD0            (AT91C_PIO_PA0) //  USART 0 Receive Data
2185
#define AT91C_PIO_PA1             (1 <<  1) // Pin Controlled by PA1
2186
#define AT91C_PA1_TXD0            (AT91C_PIO_PA1) //  USART 0 Transmit Data
2187
#define AT91C_PIO_PA10            (1 << 10) // Pin Controlled by PA10
2188
#define AT91C_PA10_TWD            (AT91C_PIO_PA10) //  TWI Two-wire Serial Data
2189
#define AT91C_PIO_PA11            (1 << 11) // Pin Controlled by PA11
2190
#define AT91C_PA11_TWCK           (AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
2191
#define AT91C_PIO_PA12            (1 << 12) // Pin Controlled by PA12
2192
#define AT91C_PA12_NPCS00         (AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
2193
#define AT91C_PIO_PA13            (1 << 13) // Pin Controlled by PA13
2194
#define AT91C_PA13_NPCS01         (AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
2195
#define AT91C_PA13_PCK1           (AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
2196
#define AT91C_PIO_PA14            (1 << 14) // Pin Controlled by PA14
2197
#define AT91C_PA14_NPCS02         (AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
2198
#define AT91C_PA14_IRQ1           (AT91C_PIO_PA14) //  External Interrupt 1
2199
#define AT91C_PIO_PA15            (1 << 15) // Pin Controlled by PA15
2200
#define AT91C_PA15_NPCS03         (AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
2201
#define AT91C_PA15_TCLK2          (AT91C_PIO_PA15) //  Timer Counter 2 external clock input
2202
#define AT91C_PIO_PA16            (1 << 16) // Pin Controlled by PA16
2203
#define AT91C_PA16_MISO0          (AT91C_PIO_PA16) //  SPI 0 Master In Slave
2204
#define AT91C_PIO_PA17            (1 << 17) // Pin Controlled by PA17
2205
#define AT91C_PA17_MOSI0          (AT91C_PIO_PA17) //  SPI 0 Master Out Slave
2206
#define AT91C_PIO_PA18            (1 << 18) // Pin Controlled by PA18
2207
#define AT91C_PA18_SPCK0          (AT91C_PIO_PA18) //  SPI 0 Serial Clock
2208
#define AT91C_PIO_PA19            (1 << 19) // Pin Controlled by PA19
2209
#define AT91C_PA19_CANRX          (AT91C_PIO_PA19) //  CAN Receive
2210
#define AT91C_PIO_PA2             (1 <<  2) // Pin Controlled by PA2
2211
#define AT91C_PA2_SCK0            (AT91C_PIO_PA2) //  USART 0 Serial Clock
2212
#define AT91C_PA2_NPCS11          (AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
2213
#define AT91C_PIO_PA20            (1 << 20) // Pin Controlled by PA20
2214
#define AT91C_PA20_CANTX          (AT91C_PIO_PA20) //  CAN Transmit
2215
#define AT91C_PIO_PA21            (1 << 21) // Pin Controlled by PA21
2216
#define AT91C_PA21_TF             (AT91C_PIO_PA21) //  SSC Transmit Frame Sync
2217
#define AT91C_PA21_NPCS10         (AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
2218
#define AT91C_PIO_PA22            (1 << 22) // Pin Controlled by PA22
2219
#define AT91C_PA22_TK             (AT91C_PIO_PA22) //  SSC Transmit Clock
2220
#define AT91C_PA22_SPCK1          (AT91C_PIO_PA22) //  SPI 1 Serial Clock
2221
#define AT91C_PIO_PA23            (1 << 23) // Pin Controlled by PA23
2222
#define AT91C_PA23_TD             (AT91C_PIO_PA23) //  SSC Transmit data
2223
#define AT91C_PA23_MOSI1          (AT91C_PIO_PA23) //  SPI 1 Master Out Slave
2224
#define AT91C_PIO_PA24            (1 << 24) // Pin Controlled by PA24
2225
#define AT91C_PA24_RD             (AT91C_PIO_PA24) //  SSC Receive Data
2226
#define AT91C_PA24_MISO1          (AT91C_PIO_PA24) //  SPI 1 Master In Slave
2227
#define AT91C_PIO_PA25            (1 << 25) // Pin Controlled by PA25
2228
#define AT91C_PA25_RK             (AT91C_PIO_PA25) //  SSC Receive Clock
2229
#define AT91C_PA25_NPCS11         (AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
2230
#define AT91C_PIO_PA26            (1 << 26) // Pin Controlled by PA26
2231
#define AT91C_PA26_RF             (AT91C_PIO_PA26) //  SSC Receive Frame Sync
2232
#define AT91C_PA26_NPCS12         (AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
2233
#define AT91C_PIO_PA27            (1 << 27) // Pin Controlled by PA27
2234
#define AT91C_PA27_DRXD           (AT91C_PIO_PA27) //  DBGU Debug Receive Data
2235
#define AT91C_PA27_PCK3           (AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
2236
#define AT91C_PIO_PA28            (1 << 28) // Pin Controlled by PA28
2237
#define AT91C_PA28_DTXD           (AT91C_PIO_PA28) //  DBGU Debug Transmit Data
2238
#define AT91C_PIO_PA29            (1 << 29) // Pin Controlled by PA29
2239
#define AT91C_PA29_FIQ            (AT91C_PIO_PA29) //  AIC Fast Interrupt Input
2240
#define AT91C_PA29_NPCS13         (AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
2241
#define AT91C_PIO_PA3             (1 <<  3) // Pin Controlled by PA3
2242
#define AT91C_PA3_RTS0            (AT91C_PIO_PA3) //  USART 0 Ready To Send
2243
#define AT91C_PA3_NPCS12          (AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
2244
#define AT91C_PIO_PA30            (1 << 30) // Pin Controlled by PA30
2245
#define AT91C_PA30_IRQ0           (AT91C_PIO_PA30) //  External Interrupt 0
2246
#define AT91C_PA30_PCK2           (AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
2247
#define AT91C_PIO_PA4             (1 <<  4) // Pin Controlled by PA4
2248
#define AT91C_PA4_CTS0            (AT91C_PIO_PA4) //  USART 0 Clear To Send
2249
#define AT91C_PA4_NPCS13          (AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
2250
#define AT91C_PIO_PA5             (1 <<  5) // Pin Controlled by PA5
2251
#define AT91C_PA5_RXD1            (AT91C_PIO_PA5) //  USART 1 Receive Data
2252
#define AT91C_PIO_PA6             (1 <<  6) // Pin Controlled by PA6
2253
#define AT91C_PA6_TXD1            (AT91C_PIO_PA6) //  USART 1 Transmit Data
2254
#define AT91C_PIO_PA7             (1 <<  7) // Pin Controlled by PA7
2255
#define AT91C_PA7_SCK1            (AT91C_PIO_PA7) //  USART 1 Serial Clock
2256
#define AT91C_PA7_NPCS01          (AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
2257
#define AT91C_PIO_PA8             (1 <<  8) // Pin Controlled by PA8
2258
#define AT91C_PA8_RTS1            (AT91C_PIO_PA8) //  USART 1 Ready To Send
2259
#define AT91C_PA8_NPCS02          (AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
2260
#define AT91C_PIO_PA9             (1 <<  9) // Pin Controlled by PA9
2261
#define AT91C_PA9_CTS1            (AT91C_PIO_PA9) //  USART 1 Clear To Send
2262
#define AT91C_PA9_NPCS03          (AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
2263
#define AT91C_PIO_PB0             (1 <<  0) // Pin Controlled by PB0
2264
#define AT91C_PB0_ETXCK_EREFCK    (AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
2265
#define AT91C_PB0_PCK0            (AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
2266
#define AT91C_PIO_PB1             (1 <<  1) // Pin Controlled by PB1
2267
#define AT91C_PB1_ETXEN           (AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
2268
#define AT91C_PIO_PB10            (1 << 10) // Pin Controlled by PB10
2269
#define AT91C_PB10_ETX2           (AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
2270
#define AT91C_PB10_NPCS11         (AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
2271
#define AT91C_PIO_PB11            (1 << 11) // Pin Controlled by PB11
2272
#define AT91C_PB11_ETX3           (AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
2273
#define AT91C_PB11_NPCS12         (AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
2274
#define AT91C_PIO_PB12            (1 << 12) // Pin Controlled by PB12
2275
#define AT91C_PB12_ETXER          (AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
2276
#define AT91C_PB12_TCLK0          (AT91C_PIO_PB12) //  Timer Counter 0 external clock input
2277
#define AT91C_PIO_PB13            (1 << 13) // Pin Controlled by PB13
2278
#define AT91C_PB13_ERX2           (AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
2279
#define AT91C_PB13_NPCS01         (AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
2280
#define AT91C_PIO_PB14            (1 << 14) // Pin Controlled by PB14
2281
#define AT91C_PB14_ERX3           (AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
2282
#define AT91C_PB14_NPCS02         (AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
2283
#define AT91C_PIO_PB15            (1 << 15) // Pin Controlled by PB15
2284
#define AT91C_PB15_ERXDV          (AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
2285
#define AT91C_PIO_PB16            (1 << 16) // Pin Controlled by PB16
2286
#define AT91C_PB16_ECOL           (AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
2287
#define AT91C_PB16_NPCS13         (AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
2288
#define AT91C_PIO_PB17            (1 << 17) // Pin Controlled by PB17
2289
#define AT91C_PB17_ERXCK          (AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
2290
#define AT91C_PB17_NPCS03         (AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
2291
#define AT91C_PIO_PB18            (1 << 18) // Pin Controlled by PB18
2292
#define AT91C_PB18_EF100          (AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
2293
#define AT91C_PB18_ADTRG          (AT91C_PIO_PB18) //  ADC External Trigger
2294
#define AT91C_PIO_PB19            (1 << 19) // Pin Controlled by PB19
2295
#define AT91C_PB19_PWM0           (AT91C_PIO_PB19) //  PWM Channel 0
2296
#define AT91C_PB19_TCLK1          (AT91C_PIO_PB19) //  Timer Counter 1 external clock input
2297
#define AT91C_PIO_PB2             (1 <<  2) // Pin Controlled by PB2
2298
#define AT91C_PB2_ETX0            (AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
2299
#define AT91C_PIO_PB20            (1 << 20) // Pin Controlled by PB20
2300
#define AT91C_PB20_PWM1           (AT91C_PIO_PB20) //  PWM Channel 1
2301
#define AT91C_PB20_PCK0           (AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
2302
#define AT91C_PIO_PB21            (1 << 21) // Pin Controlled by PB21
2303
#define AT91C_PB21_PWM2           (AT91C_PIO_PB21) //  PWM Channel 2
2304
#define AT91C_PB21_PCK1           (AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
2305
#define AT91C_PIO_PB22            (1 << 22) // Pin Controlled by PB22
2306
#define AT91C_PB22_PWM3           (AT91C_PIO_PB22) //  PWM Channel 3
2307
#define AT91C_PB22_PCK2           (AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
2308
#define AT91C_PIO_PB23            (1 << 23) // Pin Controlled by PB23
2309
#define AT91C_PB23_TIOA0          (AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
2310
#define AT91C_PB23_DCD1           (AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
2311
#define AT91C_PIO_PB24            (1 << 24) // Pin Controlled by PB24
2312
#define AT91C_PB24_TIOB0          (AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
2313
#define AT91C_PB24_DSR1           (AT91C_PIO_PB24) //  USART 1 Data Set ready
2314
#define AT91C_PIO_PB25            (1 << 25) // Pin Controlled by PB25
2315
#define AT91C_PB25_TIOA1          (AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
2316
#define AT91C_PB25_DTR1           (AT91C_PIO_PB25) //  USART 1 Data Terminal ready
2317
#define AT91C_PIO_PB26            (1 << 26) // Pin Controlled by PB26
2318
#define AT91C_PB26_TIOB1          (AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
2319
#define AT91C_PB26_RI1            (AT91C_PIO_PB26) //  USART 1 Ring Indicator
2320
#define AT91C_PIO_PB27            (1 << 27) // Pin Controlled by PB27
2321
#define AT91C_PB27_TIOA2          (AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
2322
#define AT91C_PB27_PWM0           (AT91C_PIO_PB27) //  PWM Channel 0
2323
#define AT91C_PIO_PB28            (1 << 28) // Pin Controlled by PB28
2324
#define AT91C_PB28_TIOB2          (AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
2325
#define AT91C_PB28_PWM1           (AT91C_PIO_PB28) //  PWM Channel 1
2326
#define AT91C_PIO_PB29            (1 << 29) // Pin Controlled by PB29
2327
#define AT91C_PB29_PCK1           (AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
2328
#define AT91C_PB29_PWM2           (AT91C_PIO_PB29) //  PWM Channel 2
2329
#define AT91C_PIO_PB3             (1 <<  3) // Pin Controlled by PB3
2330
#define AT91C_PB3_ETX1            (AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
2331
#define AT91C_PIO_PB30            (1 << 30) // Pin Controlled by PB30
2332
#define AT91C_PB30_PCK2           (AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
2333
#define AT91C_PB30_PWM3           (AT91C_PIO_PB30) //  PWM Channel 3
2334
#define AT91C_PIO_PB4             (1 <<  4) // Pin Controlled by PB4
2335
#define AT91C_PB4_ECRS_ECRSDV     (AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
2336
#define AT91C_PIO_PB5             (1 <<  5) // Pin Controlled by PB5
2337
#define AT91C_PB5_ERX0            (AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
2338
#define AT91C_PIO_PB6             (1 <<  6) // Pin Controlled by PB6
2339
#define AT91C_PB6_ERX1            (AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
2340
#define AT91C_PIO_PB7             (1 <<  7) // Pin Controlled by PB7
2341
#define AT91C_PB7_ERXER           (AT91C_PIO_PB7) //  Ethernet MAC Receive Error
2342
#define AT91C_PIO_PB8             (1 <<  8) // Pin Controlled by PB8
2343
#define AT91C_PB8_EMDC            (AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
2344
#define AT91C_PIO_PB9             (1 <<  9) // Pin Controlled by PB9
2345
#define AT91C_PB9_EMDIO           (AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
2346
 
2347
// *****************************************************************************
2348
//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
2349
// *****************************************************************************
2350
#define AT91C_ID_FIQ              ( 0) // Advanced Interrupt Controller (FIQ)
2351
#define AT91C_ID_SYS              ( 1) // System Peripheral
2352
#define AT91C_ID_PIOA             ( 2) // Parallel IO Controller A
2353
#define AT91C_ID_PIOB             ( 3) // Parallel IO Controller B
2354
#define AT91C_ID_SPI0             ( 4) // Serial Peripheral Interface 0
2355
#define AT91C_ID_SPI1             ( 5) // Serial Peripheral Interface 1
2356
#define AT91C_ID_US0              ( 6) // USART 0
2357
#define AT91C_ID_US1              ( 7) // USART 1
2358
#define AT91C_ID_SSC              ( 8) // Serial Synchronous Controller
2359
#define AT91C_ID_TWI              ( 9) // Two-Wire Interface
2360
#define AT91C_ID_PWMC             (10) // PWM Controller
2361
#define AT91C_ID_UDP              (11) // USB Device Port
2362
#define AT91C_ID_TC0              (12) // Timer Counter 0
2363
#define AT91C_ID_TC1              (13) // Timer Counter 1
2364
#define AT91C_ID_TC2              (14) // Timer Counter 2
2365
#define AT91C_ID_CAN              (15) // Control Area Network Controller
2366
#define AT91C_ID_EMAC             (16) // Ethernet MAC
2367
#define AT91C_ID_ADC              (17) // Analog-to-Digital Converter
2368
#define AT91C_ID_AES              (18) // Advanced Encryption Standard 128-bit
2369
#define AT91C_ID_TDES             (19) // Triple Data Encryption Standard
2370
#define AT91C_ID_20_Reserved      (20) // Reserved
2371
#define AT91C_ID_21_Reserved      (21) // Reserved
2372
#define AT91C_ID_22_Reserved      (22) // Reserved
2373
#define AT91C_ID_23_Reserved      (23) // Reserved
2374
#define AT91C_ID_24_Reserved      (24) // Reserved
2375
#define AT91C_ID_25_Reserved      (25) // Reserved
2376
#define AT91C_ID_26_Reserved      (26) // Reserved
2377
#define AT91C_ID_27_Reserved      (27) // Reserved
2378
#define AT91C_ID_28_Reserved      (28) // Reserved
2379
#define AT91C_ID_29_Reserved      (29) // Reserved
2380
#define AT91C_ID_IRQ0             (30) // Advanced Interrupt Controller (IRQ0)
2381
#define AT91C_ID_IRQ1             (31) // Advanced Interrupt Controller (IRQ1)
2382
 
2383
// *****************************************************************************
2384
//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
2385
// *****************************************************************************
2386
#define AT91C_BASE_SYS            (0xFFFFF000) // (SYS) Base Address
2387
#define AT91C_BASE_AIC            (0xFFFFF000) // (AIC) Base Address
2388
#define AT91C_BASE_PDC_DBGU       (0xFFFFF300) // (PDC_DBGU) Base Address
2389
#define AT91C_BASE_DBGU           (0xFFFFF200) // (DBGU) Base Address
2390
#define AT91C_BASE_PIOA           (0xFFFFF400) // (PIOA) Base Address
2391
#define AT91C_BASE_PIOB           (0xFFFFF600) // (PIOB) Base Address
2392
#define AT91C_BASE_CKGR           (0xFFFFFC20) // (CKGR) Base Address
2393
#define AT91C_BASE_PMC            (0xFFFFFC00) // (PMC) Base Address
2394
#define AT91C_BASE_RSTC           (0xFFFFFD00) // (RSTC) Base Address
2395
#define AT91C_BASE_RTTC           (0xFFFFFD20) // (RTTC) Base Address
2396
#define AT91C_BASE_PITC           (0xFFFFFD30) // (PITC) Base Address
2397
#define AT91C_BASE_WDTC           (0xFFFFFD40) // (WDTC) Base Address
2398
#define AT91C_BASE_VREG           (0xFFFFFD60) // (VREG) Base Address
2399
#define AT91C_BASE_MC             (0xFFFFFF00) // (MC) Base Address
2400
#define AT91C_BASE_PDC_SPI1       (0xFFFE4100) // (PDC_SPI1) Base Address
2401
#define AT91C_BASE_SPI1           (0xFFFE4000) // (SPI1) Base Address
2402
#define AT91C_BASE_PDC_SPI0       (0xFFFE0100) // (PDC_SPI0) Base Address
2403
#define AT91C_BASE_SPI0           (0xFFFE0000) // (SPI0) Base Address
2404
#define AT91C_BASE_PDC_US1        (0xFFFC4100) // (PDC_US1) Base Address
2405
#define AT91C_BASE_US1            (0xFFFC4000) // (US1) Base Address
2406
#define AT91C_BASE_PDC_US0        (0xFFFC0100) // (PDC_US0) Base Address
2407
#define AT91C_BASE_US0            (0xFFFC0000) // (US0) Base Address
2408
#define AT91C_BASE_PDC_SSC        (0xFFFD4100) // (PDC_SSC) Base Address
2409
#define AT91C_BASE_SSC            (0xFFFD4000) // (SSC) Base Address
2410
#define AT91C_BASE_TWI            (0xFFFB8000) // (TWI) Base Address
2411
#define AT91C_BASE_PWMC_CH3       (0xFFFCC260) // (PWMC_CH3) Base Address
2412
#define AT91C_BASE_PWMC_CH2       (0xFFFCC240) // (PWMC_CH2) Base Address
2413
#define AT91C_BASE_PWMC_CH1       (0xFFFCC220) // (PWMC_CH1) Base Address
2414
#define AT91C_BASE_PWMC_CH0       (0xFFFCC200) // (PWMC_CH0) Base Address
2415
#define AT91C_BASE_PWMC           (0xFFFCC000) // (PWMC) Base Address
2416
#define AT91C_BASE_UDP            (0xFFFB0000) // (UDP) Base Address
2417
#define AT91C_BASE_TC0            (0xFFFA0000) // (TC0) Base Address
2418
#define AT91C_BASE_TC1            (0xFFFA0040) // (TC1) Base Address
2419
#define AT91C_BASE_TC2            (0xFFFA0080) // (TC2) Base Address
2420
#define AT91C_BASE_TCB            (0xFFFA0000) // (TCB) Base Address
2421
#define AT91C_BASE_CAN_MB0        (0xFFFD0200) // (CAN_MB0) Base Address
2422
#define AT91C_BASE_CAN_MB1        (0xFFFD0220) // (CAN_MB1) Base Address
2423
#define AT91C_BASE_CAN_MB2        (0xFFFD0240) // (CAN_MB2) Base Address
2424
#define AT91C_BASE_CAN_MB3        (0xFFFD0260) // (CAN_MB3) Base Address
2425
#define AT91C_BASE_CAN_MB4        (0xFFFD0280) // (CAN_MB4) Base Address
2426
#define AT91C_BASE_CAN_MB5        (0xFFFD02A0) // (CAN_MB5) Base Address
2427
#define AT91C_BASE_CAN_MB6        (0xFFFD02C0) // (CAN_MB6) Base Address
2428
#define AT91C_BASE_CAN_MB7        (0xFFFD02E0) // (CAN_MB7) Base Address
2429
#define AT91C_BASE_CAN            (0xFFFD0000) // (CAN) Base Address
2430
#define AT91C_BASE_EMAC           (0xFFFDC000) // (EMAC) Base Address
2431
#define AT91C_BASE_PDC_ADC        (0xFFFD8100) // (PDC_ADC) Base Address
2432
#define AT91C_BASE_ADC            (0xFFFD8000) // (ADC) Base Address
2433
#define AT91C_BASE_PDC_AES        (0xFFFA4100) // (PDC_AES) Base Address
2434
#define AT91C_BASE_AES            (0xFFFA4000) // (AES) Base Address
2435
#define AT91C_BASE_PDC_TDES       (0xFFFA8100) // (PDC_TDES) Base Address
2436
#define AT91C_BASE_TDES           (0xFFFA8000) // (TDES) Base Address
2437
 
2438
// *****************************************************************************
2439
//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
2440
// *****************************************************************************
2441
#define AT91C_ISRAM                   (0x00200000) // Internal SRAM base address
2442
#define AT91C_ISRAM_SIZE                 (0x00010000) // Internal SRAM size in byte (64 Kbyte)
2443
#define AT91C_IFLASH                 (0x00100000) // Internal ROM base address
2444
#define AT91C_IFLASH_SIZE               (0x00040000) // Internal ROM size in byte (256 Kbyte)
2445
 
2446
 

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