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        EXTERN pxCurrentTCB
        EXTERN ulCriticalNesting
 
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Context save and restore macro definitions
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
portSAVE_CONTEXT MACRO
 
        ; Push R0 as we are going to use the register.
        STMDB   SP!, {R0}
 
        ; Set R0 to point to the task stack pointer.
        STMDB   SP, {SP}^
        NOP
        SUB             SP, SP, #4
        LDMIA   SP!, {R0}
 
        ; Push the return address onto the stack.
        STMDB   R0!, {LR}
 
        ; Now we have saved LR we can use it instead of R0.
        MOV             LR, R0
 
        ; Pop R0 so we can save it onto the system mode stack.
        LDMIA   SP!, {R0}
 
        ; Push all the system mode registers onto the task stack.
        STMDB   LR, {R0-LR}^
        NOP
        SUB             LR, LR, #60
 
        ; Push the SPSR onto the task stack.
        MRS             R0, SPSR
        STMDB   LR!, {R0}
 
        LDR             R0, =ulCriticalNesting
        LDR             R0, [R0]
        STMDB   LR!, {R0}
 
        ; Store the new top of stack for the task.
        LDR             R1, =pxCurrentTCB
        LDR             R0, [R1]
        STR             LR, [R0]
 
        ENDM
 
 
portRESTORE_CONTEXT MACRO
 
        ; Set the LR to the task stack.
        LDR             R1, =pxCurrentTCB
        LDR             R0, [R1]
        LDR             LR, [R0]
 
        ; The critical nesting depth is the first item on the stack.
        ; Load it into the ulCriticalNesting variable.
        LDR             R0, =ulCriticalNesting
        LDMFD   LR!, {R1}
        STR             R1, [R0]
 
        ; Get the SPSR from the stack.
        LDMFD   LR!, {R0}
        MSR             SPSR_cxsf, R0
 
        ; Restore all system mode registers for the task.
        LDMFD   LR, {R0-R14}^
        NOP
 
        ; Restore the return address.
        LDR             LR, [LR, #+60]
 
        ; And return - correcting the offset in the LR to obtain the
        ; correct address.
        SUBS    PC, LR, #4
 
        ENDM
 

Line No.	Rev	Author	Line
1	572	jeremybenn	`EXTERN pxCurrentTCB`
2			`EXTERN ulCriticalNesting`
3
4			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
5			`; Context save and restore macro definitions`
6			`;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;`
7
8			`portSAVE_CONTEXT MACRO`
9
10			`; Push R0 as we are going to use the register.`
11			`STMDB SP!, {R0}`
12
13			`; Set R0 to point to the task stack pointer.`
14			`STMDB SP, {SP}^`
15			`NOP`
16			`SUB SP, SP, #4`
17			`LDMIA SP!, {R0}`
18
19			`; Push the return address onto the stack.`
20			`STMDB R0!, {LR}`
21
22			`; Now we have saved LR we can use it instead of R0.`
23			`MOV LR, R0`
24
25			`; Pop R0 so we can save it onto the system mode stack.`
26			`LDMIA SP!, {R0}`
27
28			`; Push all the system mode registers onto the task stack.`
29			`STMDB LR, {R0-LR}^`
30			`NOP`
31			`SUB LR, LR, #60`
32
33			`; Push the SPSR onto the task stack.`
34			`MRS R0, SPSR`
35			`STMDB LR!, {R0}`
36
37			`LDR R0, =ulCriticalNesting`
38			`LDR R0, [R0]`
39			`STMDB LR!, {R0}`
40
41			`; Store the new top of stack for the task.`
42			`LDR R1, =pxCurrentTCB`
43			`LDR R0, [R1]`
44			`STR LR, [R0]`
45
46			`ENDM`
47
48
49			`portRESTORE_CONTEXT MACRO`
50
51			`; Set the LR to the task stack.`
52			`LDR R1, =pxCurrentTCB`
53			`LDR R0, [R1]`
54			`LDR LR, [R0]`
55
56			`; The critical nesting depth is the first item on the stack.`
57			`; Load it into the ulCriticalNesting variable.`
58			`LDR R0, =ulCriticalNesting`
59			`LDMFD LR!, {R1}`
60			`STR R1, [R0]`
61
62			`; Get the SPSR from the stack.`
63			`LDMFD LR!, {R0}`
64			`MSR SPSR_cxsf, R0`
65
66			`; Restore all system mode registers for the task.`
67			`LDMFD LR, {R0-R14}^`
68			`NOP`
69
70			`; Restore the return address.`
71			`LDR LR, [LR, #+60]`
72
73			`; And return - correcting the offset in the LR to obtain the`
74			`; correct address.`
75			`SUBS PC, LR, #4`
76
77			`ENDM`
78

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[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Source/] [portable/] [IAR/] [STR71x/] [ISR_Support.h] - Blame information for rev 572