OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [freertos-6.1.1/] [Source/] [portable/] [IAR/] [STR75x/] [ISR_Support.h] - Blame information for rev 597

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 572 jeremybenn
;/*
2
;    FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
3
;
4
;    ***************************************************************************
5
;    *                                                                         *
6
;    * If you are:                                                             *
7
;    *                                                                         *
8
;    *    + New to FreeRTOS,                                                   *
9
;    *    + Wanting to learn FreeRTOS or multitasking in general quickly       *
10
;    *    + Looking for basic training,                                        *
11
;    *    + Wanting to improve your FreeRTOS skills and productivity           *
12
;    *                                                                         *
13
;    * then take a look at the FreeRTOS books - available as PDF or paperback  *
14
;    *                                                                         *
15
;    *        "Using the FreeRTOS Real Time Kernel - a Practical Guide"        *
16
;    *                  http://www.FreeRTOS.org/Documentation                  *
17
;    *                                                                         *
18
;    * A pdf reference manual is also available.  Both are usually delivered   *
19
;    * to your inbox within 20 minutes to two hours when purchased between 8am *
20
;    * and 8pm GMT (although please allow up to 24 hours in case of            *
21
;    * exceptional circumstances).  Thank you for your support!                *
22
;    *                                                                         *
23
;    ***************************************************************************
24
;
25
;    This file is part of the FreeRTOS distribution.
26
;
27
;    FreeRTOS is free software; you can redistribute it and/or modify it under
28
;    the terms of the GNU General Public License (version 2) as published by the
29
;    Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
30
;    ***NOTE*** The exception to the GPL is included to allow you to distribute
31
;    a combined work that includes FreeRTOS without being obliged to provide the
32
;    source code for proprietary components outside of the FreeRTOS kernel.
33
;    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
34
;    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
35
;    FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
36
;    more details. You should have received a copy of the GNU General Public
37
;    License and the FreeRTOS license exception along with FreeRTOS; if not it
38
;    can be viewed here: http://www.freertos.org/a00114.html and also obtained
39
;    by writing to Richard Barry, contact details for whom are available on the
40
;    FreeRTOS WEB site.
41
;
42
;    1 tab == 4 spaces!
43
;
44
;    http://www.FreeRTOS.org - Documentation, latest information, license and
45
;    contact details.
46
;
47
;    http://www.SafeRTOS.com - A version that is certified for use in safety
48
;    critical systems.
49
;
50
;    http://www.OpenRTOS.com - Commercial support, development, porting,
51
;    licensing and training services.
52
;*/
53
 
54
        EXTERN pxCurrentTCB
55
        EXTERN ulCriticalNesting
56
 
57
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
58
; Context save and restore macro definitions
59
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
60
 
61
portSAVE_CONTEXT MACRO
62
 
63
        ; Push R0 as we are going to use the register.
64
        STMDB   SP!, {R0}
65
 
66
        ; Set R0 to point to the task stack pointer.
67
        STMDB   SP, {SP}^
68
        NOP
69
        SUB             SP, SP, #4
70
        LDMIA   SP!, {R0}
71
 
72
        ; Push the return address onto the stack.
73
        STMDB   R0!, {LR}
74
 
75
        ; Now we have saved LR we can use it instead of R0.
76
        MOV             LR, R0
77
 
78
        ; Pop R0 so we can save it onto the system mode stack.
79
        LDMIA   SP!, {R0}
80
 
81
        ; Push all the system mode registers onto the task stack.
82
        STMDB   LR, {R0-LR}^
83
        NOP
84
        SUB             LR, LR, #60
85
 
86
        ; Push the SPSR onto the task stack.
87
        MRS             R0, SPSR
88
        STMDB   LR!, {R0}
89
 
90
        LDR             R0, =ulCriticalNesting
91
        LDR             R0, [R0]
92
        STMDB   LR!, {R0}
93
 
94
        ; Store the new top of stack for the task.
95
        LDR             R1, =pxCurrentTCB
96
        LDR             R0, [R1]
97
        STR             LR, [R0]
98
 
99
        ENDM
100
 
101
 
102
portRESTORE_CONTEXT MACRO
103
 
104
        ; Set the LR to the task stack.
105
        LDR             R1, =pxCurrentTCB
106
        LDR             R0, [R1]
107
        LDR             LR, [R0]
108
 
109
        ; The critical nesting depth is the first item on the stack.
110
        ; Load it into the ulCriticalNesting variable.
111
        LDR             R0, =ulCriticalNesting
112
        LDMFD   LR!, {R1}
113
        STR             R1, [R0]
114
 
115
        ; Get the SPSR from the stack.
116
        LDMFD   LR!, {R0}
117
        MSR             SPSR_cxsf, R0
118
 
119
        ; Restore all system mode registers for the task.
120
        LDMFD   LR, {R0-R14}^
121
        NOP
122
 
123
        ; Restore the return address.
124
        LDR             LR, [LR, #+60]
125
 
126
        ; And return - correcting the offset in the LR to obtain the
127
        ; correct address.
128
        SUBS    PC, LR, #4
129
 
130
        ENDM
131
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.