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jeremybenn |
/*
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FreeRTOS V6.1.1 - Copyright (C) 2011 Real Time Engineers Ltd.
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***************************************************************************
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* *
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* If you are: *
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* *
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* + New to FreeRTOS, *
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* + Wanting to learn FreeRTOS or multitasking in general quickly *
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* + Looking for basic training, *
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* + Wanting to improve your FreeRTOS skills and productivity *
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* *
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* then take a look at the FreeRTOS books - available as PDF or paperback *
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* *
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* "Using the FreeRTOS Real Time Kernel - a Practical Guide" *
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* http://www.FreeRTOS.org/Documentation *
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* *
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* A pdf reference manual is also available. Both are usually delivered *
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* to your inbox within 20 minutes to two hours when purchased between 8am *
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* and 8pm GMT (although please allow up to 24 hours in case of *
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* exceptional circumstances). Thank you for your support! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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***NOTE*** The exception to the GPL is included to allow you to distribute
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a combined work that includes FreeRTOS without being obliged to provide the
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source code for proprietary components outside of the FreeRTOS kernel.
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FreeRTOS is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details. You should have received a copy of the GNU General Public
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License and the FreeRTOS license exception along with FreeRTOS; if not it
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can be viewed here: http://www.freertos.org/a00114.html and also obtained
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by writing to Richard Barry, contact details for whom are available on the
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FreeRTOS WEB site.
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1 tab == 4 spaces!
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http://www.FreeRTOS.org - Documentation, latest information, license and
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contact details.
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http://www.SafeRTOS.com - A version that is certified for use in safety
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critical systems.
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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*/
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/*
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Changes between V1.2.4 and V1.2.5
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+ Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
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interrupt flag setting. Using the two bits defined within
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portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
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before the test was performed.
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Changes from V1.2.5
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+ Set the interrupt vector address to 0x08. Previously it was at the
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incorrect address for compatibility mode of 0x18.
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Changes from V2.1.1
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+ PCLATU and PCLATH are now saved as part of the context. This allows
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function pointers to be used within tasks. Thanks to Javier Espeche
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for the enhancement.
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Changes from V2.3.1
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+ TABLAT is now saved as part of the task context.
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Changes from V3.2.0
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+ TBLPTRU is now initialised to zero as the MPLAB compiler expects this
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value and does not write to the register.
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*/
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/* Scheduler include files. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* MPLAB library include file. */
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#include "timers.h"
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the PIC port.
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*----------------------------------------------------------*/
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/* Hardware setup for tick. */
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#define portTIMER_FOSC_SCALE ( ( unsigned long ) 4 )
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/* Initial interrupt enable state for newly created tasks. This value is
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copied into INTCON when a task switches in for the first time. */
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#define portINITAL_INTERRUPT_STATE 0xc0
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/* Just the bit within INTCON for the global interrupt flag. */
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#define portGLOBAL_INTERRUPT_FLAG 0x80
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/* Constant used for context switch macro when we require the interrupt
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enable state to be unchanged when the interrupted task is switched back in. */
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#define portINTERRUPTS_UNCHANGED 0x00
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/* Some memory areas get saved as part of the task context. These memory
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area's get used by the compiler for temporary storage, especially when
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performing mathematical operations, or when using 32bit data types. This
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constant defines the size of memory area which must be saved. */
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#define portCOMPILER_MANAGED_MEMORY_SIZE ( ( unsigned char ) 0x13 )
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/* We require the address of the pxCurrentTCB variable, but don't want to know
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any details of its type. */
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typedef void tskTCB;
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extern volatile tskTCB * volatile pxCurrentTCB;
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/* IO port constants. */
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#define portBIT_SET ( ( unsigned char ) 1 )
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#define portBIT_CLEAR ( ( unsigned char ) 0 )
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/*
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* The serial port ISR's are defined in serial.c, but are called from portable
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* as they use the same vector as the tick ISR.
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*/
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void vSerialTxISR( void );
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void vSerialRxISR( void );
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/*
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* Perform hardware setup to enable ticks.
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*/
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static void prvSetupTimerInterrupt( void );
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/*
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* ISR to maintain the tick, and perform tick context switches if the
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* preemptive scheduler is being used.
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*/
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static void prvTickISR( void );
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/*
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* ISR placed on the low priority vector. This calls the appropriate ISR for
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* the actual interrupt.
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*/
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static void prvLowInterrupt( void );
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/*
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* Macro that pushes all the registers that make up the context of a task onto
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* the stack, then saves the new top of stack into the TCB.
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*
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* If this is called from an ISR then the interrupt enable bits must have been
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* set for the ISR to ever get called. Therefore we want to save the INTCON
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* register with the enable bits forced to be set - and ucForcedInterruptFlags
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* must contain these bit settings. This means the interrupts will again be
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* enabled when the interrupted task is switched back in.
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*
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* If this is called from a manual context switch (i.e. from a call to yield),
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* then we want to save the INTCON so it is restored with its current state,
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* and ucForcedInterruptFlags must be 0. This allows a yield from within
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* a critical section.
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*
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* The compiler uses some locations at the bottom of the memory for temporary
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* storage during math and other computations. This is especially true if
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* 32bit data types are utilised (as they are by the scheduler). The .tmpdata
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* and MATH_DATA sections have to be stored in there entirety as part of a task
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* context. This macro stores from data address 0x00 to
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* portCOMPILER_MANAGED_MEMORY_SIZE. This is sufficient for the demo
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* applications but you should check the map file for your project to ensure
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* this is sufficient for your needs. It is not clear whether this size is
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* fixed for all compilations or has the potential to be program specific.
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*/
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#define portSAVE_CONTEXT( ucForcedInterruptFlags ) \
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{ \
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_asm \
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/* Save the status and WREG registers first, as these will get modified \
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by the operations below. */ \
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MOVFF WREG, PREINC1 \
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MOVFF STATUS, PREINC1 \
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/* Save the INTCON register with the appropriate bits forced if \
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necessary - as described above. */ \
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MOVFF INTCON, WREG \
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IORLW ucForcedInterruptFlags \
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MOVFF WREG, PREINC1 \
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_endasm \
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\
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portDISABLE_INTERRUPTS(); \
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\
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_asm \
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/* Store the necessary registers to the stack. */ \
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MOVFF BSR, PREINC1 \
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MOVFF FSR2L, PREINC1 \
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MOVFF FSR2H, PREINC1 \
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MOVFF FSR0L, PREINC1 \
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MOVFF FSR0H, PREINC1 \
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MOVFF TABLAT, PREINC1 \
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MOVFF TBLPTRU, PREINC1 \
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MOVFF TBLPTRH, PREINC1 \
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MOVFF TBLPTRL, PREINC1 \
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MOVFF PRODH, PREINC1 \
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MOVFF PRODL, PREINC1 \
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MOVFF PCLATU, PREINC1 \
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MOVFF PCLATH, PREINC1 \
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/* Store the .tempdata and MATH_DATA areas as described above. */ \
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CLRF FSR0L, 0 \
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CLRF FSR0H, 0 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF POSTINC0, PREINC1 \
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MOVFF INDF0, PREINC1 \
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MOVFF FSR0L, PREINC1 \
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MOVFF FSR0H, PREINC1 \
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/* Store the hardware stack pointer in a temp register before we \
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modify it. */ \
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MOVFF STKPTR, FSR0L \
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_endasm \
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\
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/* Store each address from the hardware stack. */ \
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while( STKPTR > ( unsigned char ) 0 ) \
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{ \
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_asm \
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MOVFF TOSL, PREINC1 \
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MOVFF TOSH, PREINC1 \
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MOVFF TOSU, PREINC1 \
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POP \
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_endasm \
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} \
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\
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_asm \
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/* Store the number of addresses on the hardware stack (from the \
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temporary register). */ \
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MOVFF FSR0L, PREINC1 \
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MOVF PREINC1, 1, 0 \
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_endasm \
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\
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/* Save the new top of the software stack in the TCB. */ \
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_asm \
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MOVFF pxCurrentTCB, FSR0L \
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MOVFF pxCurrentTCB + 1, FSR0H \
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MOVFF FSR1L, POSTINC0 \
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MOVFF FSR1H, POSTINC0 \
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_endasm \
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}
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/*-----------------------------------------------------------*/
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/*
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* This is the reverse of portSAVE_CONTEXT. See portSAVE_CONTEXT for more
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* details.
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*/
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#define portRESTORE_CONTEXT() \
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{ \
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_asm \
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/* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */ \
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MOVFF pxCurrentTCB, FSR0L \
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MOVFF pxCurrentTCB + 1, FSR0H \
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\
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/* De-reference FSR0 to set the address it holds into FSR1. \
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(i.e. *( pxCurrentTCB->pxTopOfStack ) ). */ \
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MOVFF POSTINC0, FSR1L \
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MOVFF POSTINC0, FSR1H \
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\
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/* How many return addresses are there on the hardware stack? Discard \
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the first byte as we are pointing to the next free space. */ \
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MOVFF POSTDEC1, FSR0L \
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MOVFF POSTDEC1, FSR0L \
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_endasm \
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\
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/* Fill the hardware stack from our software stack. */ \
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STKPTR = 0; \
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\
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| 286 |
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while( STKPTR < FSR0L ) \
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| 287 |
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{ \
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| 288 |
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_asm \
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PUSH \
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| 290 |
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MOVF POSTDEC1, 0, 0 \
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MOVWF TOSU, 0 \
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| 292 |
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MOVF POSTDEC1, 0, 0 \
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MOVWF TOSH, 0 \
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MOVF POSTDEC1, 0, 0 \
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MOVWF TOSL, 0 \
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| 296 |
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_endasm \
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| 297 |
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} \
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| 298 |
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\
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| 299 |
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_asm \
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| 300 |
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/* Restore the .tmpdata and MATH_DATA memory. */ \
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MOVFF POSTDEC1, FSR0H \
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MOVFF POSTDEC1, FSR0L \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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| 306 |
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MOVFF POSTDEC1, POSTDEC0 \
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| 307 |
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MOVFF POSTDEC1, POSTDEC0 \
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| 308 |
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MOVFF POSTDEC1, POSTDEC0 \
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| 309 |
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MOVFF POSTDEC1, POSTDEC0 \
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| 310 |
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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| 312 |
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MOVFF POSTDEC1, POSTDEC0 \
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MOVFF POSTDEC1, POSTDEC0 \
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| 314 |
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MOVFF POSTDEC1, POSTDEC0 \
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| 315 |
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MOVFF POSTDEC1, POSTDEC0 \
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| 316 |
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MOVFF POSTDEC1, POSTDEC0 \
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| 317 |
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MOVFF POSTDEC1, POSTDEC0 \
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| 318 |
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MOVFF POSTDEC1, POSTDEC0 \
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| 319 |
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MOVFF POSTDEC1, POSTDEC0 \
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| 320 |
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MOVFF POSTDEC1, POSTDEC0 \
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| 321 |
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MOVFF POSTDEC1, POSTDEC0 \
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| 322 |
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MOVFF POSTDEC1, INDF0 \
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| 323 |
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/* Restore the other registers forming the tasks context. */ \
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| 324 |
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MOVFF POSTDEC1, PCLATH \
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| 325 |
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MOVFF POSTDEC1, PCLATU \
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| 326 |
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MOVFF POSTDEC1, PRODL \
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| 327 |
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MOVFF POSTDEC1, PRODH \
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| 328 |
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MOVFF POSTDEC1, TBLPTRL \
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| 329 |
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MOVFF POSTDEC1, TBLPTRH \
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| 330 |
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MOVFF POSTDEC1, TBLPTRU \
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| 331 |
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MOVFF POSTDEC1, TABLAT \
|
| 332 |
|
|
MOVFF POSTDEC1, FSR0H \
|
| 333 |
|
|
MOVFF POSTDEC1, FSR0L \
|
| 334 |
|
|
MOVFF POSTDEC1, FSR2H \
|
| 335 |
|
|
MOVFF POSTDEC1, FSR2L \
|
| 336 |
|
|
MOVFF POSTDEC1, BSR \
|
| 337 |
|
|
/* The next byte is the INTCON register. Read this into WREG as some \
|
| 338 |
|
|
manipulation is required. */ \
|
| 339 |
|
|
MOVFF POSTDEC1, WREG \
|
| 340 |
|
|
_endasm \
|
| 341 |
|
|
\
|
| 342 |
|
|
/* From the INTCON register, only the interrupt enable bits form part \
|
| 343 |
|
|
of the tasks context. It is perfectly legitimate for another task to \
|
| 344 |
|
|
have modified any other bits. We therefore only restore the top two bits. \
|
| 345 |
|
|
*/ \
|
| 346 |
|
|
if( WREG & portGLOBAL_INTERRUPT_FLAG ) \
|
| 347 |
|
|
{ \
|
| 348 |
|
|
_asm \
|
| 349 |
|
|
MOVFF POSTDEC1, STATUS \
|
| 350 |
|
|
MOVFF POSTDEC1, WREG \
|
| 351 |
|
|
/* Return enabling interrupts. */ \
|
| 352 |
|
|
RETFIE 0 \
|
| 353 |
|
|
_endasm \
|
| 354 |
|
|
} \
|
| 355 |
|
|
else \
|
| 356 |
|
|
{ \
|
| 357 |
|
|
_asm \
|
| 358 |
|
|
MOVFF POSTDEC1, STATUS \
|
| 359 |
|
|
MOVFF POSTDEC1, WREG \
|
| 360 |
|
|
/* Return without effecting interrupts. The context may have \
|
| 361 |
|
|
been saved from a critical region. */ \
|
| 362 |
|
|
RETURN 0 \
|
| 363 |
|
|
_endasm \
|
| 364 |
|
|
} \
|
| 365 |
|
|
}
|
| 366 |
|
|
/*-----------------------------------------------------------*/
|
| 367 |
|
|
|
| 368 |
|
|
/*
|
| 369 |
|
|
* See header file for description.
|
| 370 |
|
|
*/
|
| 371 |
|
|
portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
|
| 372 |
|
|
{
|
| 373 |
|
|
unsigned long ulAddress;
|
| 374 |
|
|
unsigned char ucBlock;
|
| 375 |
|
|
|
| 376 |
|
|
/* Place a few bytes of known values on the bottom of the stack.
|
| 377 |
|
|
This is just useful for debugging. */
|
| 378 |
|
|
|
| 379 |
|
|
*pxTopOfStack = 0x11;
|
| 380 |
|
|
pxTopOfStack++;
|
| 381 |
|
|
*pxTopOfStack = 0x22;
|
| 382 |
|
|
pxTopOfStack++;
|
| 383 |
|
|
*pxTopOfStack = 0x33;
|
| 384 |
|
|
pxTopOfStack++;
|
| 385 |
|
|
|
| 386 |
|
|
|
| 387 |
|
|
/* Simulate how the stack would look after a call to vPortYield() generated
|
| 388 |
|
|
by the compiler.
|
| 389 |
|
|
|
| 390 |
|
|
First store the function parameters. This is where the task will expect to
|
| 391 |
|
|
find them when it starts running. */
|
| 392 |
|
|
ulAddress = ( unsigned long ) pvParameters;
|
| 393 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
|
| 394 |
|
|
pxTopOfStack++;
|
| 395 |
|
|
|
| 396 |
|
|
ulAddress >>= 8;
|
| 397 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
|
| 398 |
|
|
pxTopOfStack++;
|
| 399 |
|
|
|
| 400 |
|
|
/* Next we just leave a space. When a context is saved the stack pointer
|
| 401 |
|
|
is incremented before it is used so as not to corrupt whatever the stack
|
| 402 |
|
|
pointer is actually pointing to. This is especially necessary during
|
| 403 |
|
|
function epilogue code generated by the compiler. */
|
| 404 |
|
|
*pxTopOfStack = 0x44;
|
| 405 |
|
|
pxTopOfStack++;
|
| 406 |
|
|
|
| 407 |
|
|
/* Next are all the registers that form part of the task context. */
|
| 408 |
|
|
|
| 409 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* WREG. */
|
| 410 |
|
|
pxTopOfStack++;
|
| 411 |
|
|
|
| 412 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) 0xcc; /* Status. */
|
| 413 |
|
|
pxTopOfStack++;
|
| 414 |
|
|
|
| 415 |
|
|
/* INTCON is saved with interrupts enabled. */
|
| 416 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) portINITAL_INTERRUPT_STATE; /* INTCON */
|
| 417 |
|
|
pxTopOfStack++;
|
| 418 |
|
|
|
| 419 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* BSR. */
|
| 420 |
|
|
pxTopOfStack++;
|
| 421 |
|
|
|
| 422 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) 0x22; /* FSR2L. */
|
| 423 |
|
|
pxTopOfStack++;
|
| 424 |
|
|
|
| 425 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) 0x33; /* FSR2H. */
|
| 426 |
|
|
pxTopOfStack++;
|
| 427 |
|
|
|
| 428 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) 0x44; /* FSR0L. */
|
| 429 |
|
|
pxTopOfStack++;
|
| 430 |
|
|
|
| 431 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) 0x55; /* FSR0H. */
|
| 432 |
|
|
pxTopOfStack++;
|
| 433 |
|
|
|
| 434 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) 0x66; /* TABLAT. */
|
| 435 |
|
|
pxTopOfStack++;
|
| 436 |
|
|
|
| 437 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* TBLPTRU. */
|
| 438 |
|
|
pxTopOfStack++;
|
| 439 |
|
|
|
| 440 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) 0x88; /* TBLPTRUH. */
|
| 441 |
|
|
pxTopOfStack++;
|
| 442 |
|
|
|
| 443 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) 0x99; /* TBLPTRUL. */
|
| 444 |
|
|
pxTopOfStack++;
|
| 445 |
|
|
|
| 446 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) 0xaa; /* PRODH. */
|
| 447 |
|
|
pxTopOfStack++;
|
| 448 |
|
|
|
| 449 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) 0xbb; /* PRODL. */
|
| 450 |
|
|
pxTopOfStack++;
|
| 451 |
|
|
|
| 452 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATU. */
|
| 453 |
|
|
pxTopOfStack++;
|
| 454 |
|
|
|
| 455 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* PCLATH. */
|
| 456 |
|
|
pxTopOfStack++;
|
| 457 |
|
|
|
| 458 |
|
|
/* Next the .tmpdata and MATH_DATA sections. */
|
| 459 |
|
|
for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
|
| 460 |
|
|
{
|
| 461 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) ucBlock;
|
| 462 |
|
|
*pxTopOfStack++;
|
| 463 |
|
|
}
|
| 464 |
|
|
|
| 465 |
|
|
/* Store the top of the global data section. */
|
| 466 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
|
| 467 |
|
|
pxTopOfStack++;
|
| 468 |
|
|
|
| 469 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* High. */
|
| 470 |
|
|
pxTopOfStack++;
|
| 471 |
|
|
|
| 472 |
|
|
/* The only function return address so far is the address of the
|
| 473 |
|
|
task. */
|
| 474 |
|
|
ulAddress = ( unsigned long ) pxCode;
|
| 475 |
|
|
|
| 476 |
|
|
/* TOS low. */
|
| 477 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
|
| 478 |
|
|
pxTopOfStack++;
|
| 479 |
|
|
ulAddress >>= 8;
|
| 480 |
|
|
|
| 481 |
|
|
/* TOS high. */
|
| 482 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
|
| 483 |
|
|
pxTopOfStack++;
|
| 484 |
|
|
ulAddress >>= 8;
|
| 485 |
|
|
|
| 486 |
|
|
/* TOS even higher. */
|
| 487 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) ( ulAddress & ( unsigned long ) 0x00ff );
|
| 488 |
|
|
pxTopOfStack++;
|
| 489 |
|
|
|
| 490 |
|
|
/* Store the number of return addresses on the hardware stack - so far only
|
| 491 |
|
|
the address of the task entry point. */
|
| 492 |
|
|
*pxTopOfStack = ( portSTACK_TYPE ) 1;
|
| 493 |
|
|
pxTopOfStack++;
|
| 494 |
|
|
|
| 495 |
|
|
return pxTopOfStack;
|
| 496 |
|
|
}
|
| 497 |
|
|
/*-----------------------------------------------------------*/
|
| 498 |
|
|
|
| 499 |
|
|
portBASE_TYPE xPortStartScheduler( void )
|
| 500 |
|
|
{
|
| 501 |
|
|
/* Setup a timer for the tick ISR is using the preemptive scheduler. */
|
| 502 |
|
|
prvSetupTimerInterrupt();
|
| 503 |
|
|
|
| 504 |
|
|
/* Restore the context of the first task to run. */
|
| 505 |
|
|
portRESTORE_CONTEXT();
|
| 506 |
|
|
|
| 507 |
|
|
/* Should not get here. Use the function name to stop compiler warnings. */
|
| 508 |
|
|
( void ) prvLowInterrupt;
|
| 509 |
|
|
( void ) prvTickISR;
|
| 510 |
|
|
|
| 511 |
|
|
return pdTRUE;
|
| 512 |
|
|
}
|
| 513 |
|
|
/*-----------------------------------------------------------*/
|
| 514 |
|
|
|
| 515 |
|
|
void vPortEndScheduler( void )
|
| 516 |
|
|
{
|
| 517 |
|
|
/* It is unlikely that the scheduler for the PIC port will get stopped
|
| 518 |
|
|
once running. If required disable the tick interrupt here, then return
|
| 519 |
|
|
to xPortStartScheduler(). */
|
| 520 |
|
|
}
|
| 521 |
|
|
/*-----------------------------------------------------------*/
|
| 522 |
|
|
|
| 523 |
|
|
/*
|
| 524 |
|
|
* Manual context switch. This is similar to the tick context switch,
|
| 525 |
|
|
* but does not increment the tick count. It must be identical to the
|
| 526 |
|
|
* tick context switch in how it stores the stack of a task.
|
| 527 |
|
|
*/
|
| 528 |
|
|
void vPortYield( void )
|
| 529 |
|
|
{
|
| 530 |
|
|
/* This can get called with interrupts either enabled or disabled. We
|
| 531 |
|
|
will save the INTCON register with the interrupt enable bits unmodified. */
|
| 532 |
|
|
portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
|
| 533 |
|
|
|
| 534 |
|
|
/* Switch to the highest priority task that is ready to run. */
|
| 535 |
|
|
vTaskSwitchContext();
|
| 536 |
|
|
|
| 537 |
|
|
/* Start executing the task we have just switched to. */
|
| 538 |
|
|
portRESTORE_CONTEXT();
|
| 539 |
|
|
}
|
| 540 |
|
|
/*-----------------------------------------------------------*/
|
| 541 |
|
|
|
| 542 |
|
|
/*
|
| 543 |
|
|
* Vector for ISR. Nothing here must alter any registers!
|
| 544 |
|
|
*/
|
| 545 |
|
|
#pragma code high_vector=0x08
|
| 546 |
|
|
static void prvLowInterrupt( void )
|
| 547 |
|
|
{
|
| 548 |
|
|
/* Was the interrupt the tick? */
|
| 549 |
|
|
if( PIR1bits.CCP1IF )
|
| 550 |
|
|
{
|
| 551 |
|
|
_asm
|
| 552 |
|
|
goto prvTickISR
|
| 553 |
|
|
_endasm
|
| 554 |
|
|
}
|
| 555 |
|
|
|
| 556 |
|
|
/* Was the interrupt a byte being received? */
|
| 557 |
|
|
if( PIR1bits.RCIF )
|
| 558 |
|
|
{
|
| 559 |
|
|
_asm
|
| 560 |
|
|
goto vSerialRxISR
|
| 561 |
|
|
_endasm
|
| 562 |
|
|
}
|
| 563 |
|
|
|
| 564 |
|
|
/* Was the interrupt the Tx register becoming empty? */
|
| 565 |
|
|
if( PIR1bits.TXIF )
|
| 566 |
|
|
{
|
| 567 |
|
|
if( PIE1bits.TXIE )
|
| 568 |
|
|
{
|
| 569 |
|
|
_asm
|
| 570 |
|
|
goto vSerialTxISR
|
| 571 |
|
|
_endasm
|
| 572 |
|
|
}
|
| 573 |
|
|
}
|
| 574 |
|
|
}
|
| 575 |
|
|
#pragma code
|
| 576 |
|
|
|
| 577 |
|
|
/*-----------------------------------------------------------*/
|
| 578 |
|
|
|
| 579 |
|
|
/*
|
| 580 |
|
|
* ISR for the tick.
|
| 581 |
|
|
* This increments the tick count and, if using the preemptive scheduler,
|
| 582 |
|
|
* performs a context switch. This must be identical to the manual
|
| 583 |
|
|
* context switch in how it stores the context of a task.
|
| 584 |
|
|
*/
|
| 585 |
|
|
static void prvTickISR( void )
|
| 586 |
|
|
{
|
| 587 |
|
|
/* Interrupts must have been enabled for the ISR to fire, so we have to
|
| 588 |
|
|
save the context with interrupts enabled. */
|
| 589 |
|
|
portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
|
| 590 |
|
|
PIR1bits.CCP1IF = 0;
|
| 591 |
|
|
|
| 592 |
|
|
/* Maintain the tick count. */
|
| 593 |
|
|
vTaskIncrementTick();
|
| 594 |
|
|
|
| 595 |
|
|
#if configUSE_PREEMPTION == 1
|
| 596 |
|
|
{
|
| 597 |
|
|
/* Switch to the highest priority task that is ready to run. */
|
| 598 |
|
|
vTaskSwitchContext();
|
| 599 |
|
|
}
|
| 600 |
|
|
#endif
|
| 601 |
|
|
|
| 602 |
|
|
portRESTORE_CONTEXT();
|
| 603 |
|
|
}
|
| 604 |
|
|
/*-----------------------------------------------------------*/
|
| 605 |
|
|
|
| 606 |
|
|
/*
|
| 607 |
|
|
* Setup a timer for a regular tick.
|
| 608 |
|
|
*/
|
| 609 |
|
|
static void prvSetupTimerInterrupt( void )
|
| 610 |
|
|
{
|
| 611 |
|
|
const unsigned long ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
|
| 612 |
|
|
unsigned long ulCompareValue;
|
| 613 |
|
|
unsigned char ucByte;
|
| 614 |
|
|
|
| 615 |
|
|
/* Interrupts are disabled when this function is called.
|
| 616 |
|
|
|
| 617 |
|
|
Setup CCP1 to provide the tick interrupt using a compare match on timer
|
| 618 |
|
|
1.
|
| 619 |
|
|
|
| 620 |
|
|
Clear the time count then setup timer. */
|
| 621 |
|
|
TMR1H = ( unsigned char ) 0x00;
|
| 622 |
|
|
TMR1L = ( unsigned char ) 0x00;
|
| 623 |
|
|
|
| 624 |
|
|
/* Set the compare match value. */
|
| 625 |
|
|
ulCompareValue = ulConstCompareValue;
|
| 626 |
|
|
CCPR1L = ( unsigned char ) ( ulCompareValue & ( unsigned long ) 0xff );
|
| 627 |
|
|
ulCompareValue >>= ( unsigned long ) 8;
|
| 628 |
|
|
CCPR1H = ( unsigned char ) ( ulCompareValue & ( unsigned long ) 0xff );
|
| 629 |
|
|
|
| 630 |
|
|
CCP1CONbits.CCP1M0 = portBIT_SET; /*< Compare match mode. */
|
| 631 |
|
|
CCP1CONbits.CCP1M1 = portBIT_SET; /*< Compare match mode. */
|
| 632 |
|
|
CCP1CONbits.CCP1M2 = portBIT_CLEAR; /*< Compare match mode. */
|
| 633 |
|
|
CCP1CONbits.CCP1M3 = portBIT_SET; /*< Compare match mode. */
|
| 634 |
|
|
PIE1bits.CCP1IE = portBIT_SET; /*< Interrupt enable. */
|
| 635 |
|
|
|
| 636 |
|
|
/* We are only going to use the global interrupt bit, so set the peripheral
|
| 637 |
|
|
bit to true. */
|
| 638 |
|
|
INTCONbits.GIEL = portBIT_SET;
|
| 639 |
|
|
|
| 640 |
|
|
/* Provided library function for setting up the timer that will produce the
|
| 641 |
|
|
tick. */
|
| 642 |
|
|
OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
|
| 643 |
|
|
}
|
| 644 |
|
|
|
