OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [exec/] [itron/] [src/] [itronintr.c] - Blame information for rev 296

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*
2
 *  COPYRIGHT (c) 1989-1999.
3
 *  On-Line Applications Research Corporation (OAR).
4
 *
5
 *  The license and distribution terms for this file may be
6
 *  found in the file LICENSE in this distribution or at
7
 *  http://www.OARcorp.com/rtems/license.html.
8
 *
9
 *  $Id: itronintr.c,v 1.2 2001-09-27 11:59:13 chris Exp $
10
 */
11
 
12
#include <itron.h>
13
 
14
#include <rtems/itron/intr.h>
15
 
16
/*
17
 *  def_int - Define Interrupt Handler
18
 */
19
 
20
ER def_int(
21
  UINT    dintno,
22
  T_DINT *pk_dint
23
)
24
{
25
  return E_OK;
26
}
27
 
28
/*
29
 *  ret_int - Return from Interrupt Handler
30
 */
31
 
32
void ret_int( void )
33
{
34
}
35
 
36
/*
37
 *  ret_wup - Return and Wakeup Task
38
 */
39
 
40
void ret_wup(
41
  ID tskid
42
)
43
{
44
}
45
 
46
/*
47
 *  loc_cpu - Lock CPU
48
 */
49
 
50
ER loc_cpu( void )
51
{
52
  return E_OK;
53
}
54
 
55
/*
56
 *  unl_cpu - Unlock CPU
57
 */
58
 
59
ER unl_cpu( void )
60
{
61
  return E_OK;
62
}
63
 
64
/*
65
 *  dis_int - Disable Interrupt
66
 */
67
 
68
ER dis_int(
69
  UINT eintno
70
)
71
{
72
  return E_OK;
73
}
74
 
75
/*
76
 *  ena_int - Enable Interrupt
77
 */
78
 
79
ER ena_int(
80
  UINT eintno
81
)
82
{
83
  return E_OK;
84
}
85
 
86
/*
87
 *  chg_iXX - Change Interrupt Mask(Level or Priority)
88
 */
89
 
90
ER chg_iXX(
91
  UINT iXXXX
92
)
93
{
94
  return E_OK;
95
}
96
 
97
/*
98
 *  ref_iXX - Reference Interrupt Mask(Level or Priority)
99
 */
100
 
101
ER ref_iXX(
102
  UINT *p_iXXXX
103
)
104
{
105
  return E_OK;
106
}
107
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.