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/*  cpu.h
 *
 *  This include file contains information pertaining to the HP
 *  PA-RISC processor (Level 1.1).
 *
 *  COPYRIGHT (c) 1994 by Division Incorporated
 *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.OARcorp.com/rtems/license.html.
 *
 * Note:
 *      This file is included by both C and assembler code ( -DASM )
 *
 *  $Id: cpu.h,v 1.2 2001-09-27 11:59:24 chris Exp $
 */
 
#ifndef __CPU_h
#define __CPU_h
 
#ifdef __cplusplus
extern "C" {
#endif
 
#include <rtems/score/hppa.h>              /* pick up machine definitions */
#ifndef ASM
#include <rtems/score/hppatypes.h>
#endif
 
/* conditional compilation parameters */
 
#define CPU_INLINE_ENABLE_DISPATCH       FALSE
#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
 
/*
 *  RTEMS manages an interrupt stack in software for the HPPA.
 */
 
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
 
/*
 *  Does the RTEMS invoke the user's ISR with the vector number and
 *  a pointer to the saved interrupt frame (1) or just the vector
 *  number (0)?
 */
 
#define CPU_ISR_PASSES_FRAME_POINTER 0
 
/*
 *  HPPA has hardware FP, it is assumed to exist by GCC so all tasks
 *  may implicitly use it (especially for integer multiplies).  Because
 *  the FP context is technically part of the basic integer context
 *  on this CPU, we cannot use the deferred FP context switch algorithm.
 */
 
#define CPU_HARDWARE_FP                  TRUE
#define CPU_ALL_TASKS_ARE_FP             TRUE
#define CPU_IDLE_TASK_IS_FP              FALSE
#define CPU_USE_DEFERRED_FP_SWITCH       FALSE
 
#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
#define CPU_STACK_GROWS_UP               TRUE
#define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((__aligned__ (32)))
 
/*
 *  Define what is required to specify how the network to host conversion
 *  routines are handled.
 */
 
#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
#define CPU_BIG_ENDIAN                           TRUE
#define CPU_LITTLE_ENDIAN                        FALSE
 
/* constants */
 
#define CPU_MODES_INTERRUPT_LEVEL  0x00000001 /* interrupt level in mode */
#define CPU_MODES_INTERRUPT_MASK   0x00000001 /* interrupt level in mode */
 
/*
 * PSW contstants
 */
 
#define CPU_PSW_BASE (HPPA_PSW_C | HPPA_PSW_Q | HPPA_PSW_P | HPPA_PSW_D)
#define CPU_PSW_INTERRUPTS_ON    (CPU_PSW_BASE | HPPA_PSW_I)
#define CPU_PSW_INTERRUPTS_OFF   (CPU_PSW_BASE)
 
#define CPU_PSW_DEFAULT     CPU_PSW_BASE
 
 
#ifndef ASM
 
/*
 * Contexts
 *
 *  This means we have the following context items:
 *    1. task level context stuff::  Context_Control
 *    2. floating point task stuff:: Context_Control_fp
 *
 *  The PA-RISC is very fast so the expense of saving an extra register
 *  or two is not of great concern at the present.  So we are not making
 *  a distinction between what is saved during a task switch and what is
 *  saved at each interrupt.  Plus saving the entire context should make
 *  it easier to make gdb aware of RTEMS tasks.
 */
 
typedef struct {
    unsigned32 flags;      /* whatever */
    unsigned32 gr1;        /* scratch -- caller saves */
    unsigned32 gr2;        /* RP -- return pointer */
    unsigned32 gr3;        /* scratch -- callee saves */
    unsigned32 gr4;        /* scratch -- callee saves */
    unsigned32 gr5;        /* scratch -- callee saves */
    unsigned32 gr6;        /* scratch -- callee saves */
    unsigned32 gr7;        /* scratch -- callee saves */
    unsigned32 gr8;        /* scratch -- callee saves */
    unsigned32 gr9;        /* scratch -- callee saves */
    unsigned32 gr10;       /* scratch -- callee saves */
    unsigned32 gr11;       /* scratch -- callee saves */
    unsigned32 gr12;       /* scratch -- callee saves */
    unsigned32 gr13;       /* scratch -- callee saves */
    unsigned32 gr14;       /* scratch -- callee saves */
    unsigned32 gr15;       /* scratch -- callee saves */
    unsigned32 gr16;       /* scratch -- callee saves */
    unsigned32 gr17;       /* scratch -- callee saves */
    unsigned32 gr18;       /* scratch -- callee saves */
    unsigned32 gr19;       /* scratch -- caller saves */
    unsigned32 gr20;       /* scratch -- caller saves */
    unsigned32 gr21;       /* scratch -- caller saves */
    unsigned32 gr22;       /* scratch -- caller saves */
    unsigned32 gr23;       /* argument 3 */
    unsigned32 gr24;       /* argument 2 */
    unsigned32 gr25;       /* argument 1 */
    unsigned32 gr26;       /* argument 0 */
    unsigned32 gr27;       /* DP -- global data pointer */
    unsigned32 gr28;       /* return values -- caller saves */
    unsigned32 gr29;       /* return values -- caller saves */
    unsigned32 sp;         /* gr30 */
    unsigned32 gr31;
 
    /* Various control registers */
 
    unsigned32 sar;         /* cr11 */
    unsigned32 ipsw;        /* cr22; full 32 bits of psw */
    unsigned32 iir;         /* cr19; interrupt instruction register */
    unsigned32 ior;         /* cr21; interrupt offset register */
    unsigned32 isr;         /* cr20; interrupt space register (not used) */
    unsigned32 pcoqfront;   /* cr18; front que offset */
    unsigned32 pcoqback;    /* cr18; back que offset */
    unsigned32 pcsqfront;   /* cr17; front que space (not used) */
    unsigned32 pcsqback;    /* cr17; back que space (not used) */
    unsigned32 itimer;      /* cr16; itimer value */
 
} Context_Control;
 
 
/* Must be double word aligned.
 * This will be ok since our allocator returns 8 byte aligned chunks
 */
 
typedef struct {
    double      fr0;        /* status */
    double      fr1;        /* exception information */
    double      fr2;        /* exception information */
    double      fr3;        /* exception information */
    double      fr4;        /* argument */
    double      fr5;        /* argument */
    double      fr6;        /* argument */
    double      fr7;        /* argument */
    double      fr8;        /* scratch -- caller saves */
    double      fr9;        /* scratch -- caller saves */
    double      fr10;       /* scratch -- caller saves */
    double      fr11;       /* scratch -- caller saves */
    double      fr12;       /* callee saves -- (PA-RISC 1.1 CPUs) */
    double      fr13;       /* callee saves -- (PA-RISC 1.1 CPUs) */
    double      fr14;       /* callee saves -- (PA-RISC 1.1 CPUs) */
    double      fr15;       /* callee saves -- (PA-RISC 1.1 CPUs) */
    double      fr16;       /* callee saves -- (PA-RISC 1.1 CPUs) */
    double      fr17;       /* callee saves -- (PA-RISC 1.1 CPUs) */
    double      fr18;       /* callee saves -- (PA-RISC 1.1 CPUs) */
    double      fr19;       /* callee saves -- (PA-RISC 1.1 CPUs) */
    double      fr20;       /* callee saves -- (PA-RISC 1.1 CPUs) */
    double      fr21;       /* callee saves -- (PA-RISC 1.1 CPUs) */
    double      fr22;       /* caller saves -- (PA-RISC 1.1 CPUs) */
    double      fr23;       /* caller saves -- (PA-RISC 1.1 CPUs) */
    double      fr24;       /* caller saves -- (PA-RISC 1.1 CPUs) */
    double      fr25;       /* caller saves -- (PA-RISC 1.1 CPUs) */
    double      fr26;       /* caller saves -- (PA-RISC 1.1 CPUs) */
    double      fr27;       /* caller saves -- (PA-RISC 1.1 CPUs) */
    double      fr28;       /* caller saves -- (PA-RISC 1.1 CPUs) */
    double      fr29;       /* caller saves -- (PA-RISC 1.1 CPUs) */
    double      fr30;       /* caller saves -- (PA-RISC 1.1 CPUs) */
    double      fr31;       /* caller saves -- (PA-RISC 1.1 CPUs) */
} Context_Control_fp;
 
/*
 *  The following structure defines the set of information saved
 *  on the current stack by RTEMS upon receipt of each interrupt.
 */
 
typedef struct {
  Context_Control             Integer;
  Context_Control_fp          Floating_Point;
} CPU_Interrupt_frame;
 
/*
 * Our interrupt handlers take a 2nd argument:
 *   a pointer to a CPU_Interrupt_frame
 * So we use our own prototype instead of rtems_isr_entry
 */
 
typedef void ( *hppa_rtems_isr_entry )(
    unsigned32,
    CPU_Interrupt_frame *
 );
 
/*
 * The following table contains the information required to configure
 * the HPPA specific parameters.
 */
 
typedef struct {
  void       (*pretasking_hook)( void );
  void       (*predriver_hook)( void );
  void       (*postdriver_hook)( void );
  void       (*idle_task)( void );
  boolean      do_zero_of_workspace;
  unsigned32   idle_task_stack_size;
  unsigned32   interrupt_stack_size;
  unsigned32   extra_mpci_receive_server_stack;
  void *     (*stack_allocate_hook)( unsigned32 );
  void       (*stack_free_hook)( void * );
  /* end of fields required on all CPUs */
 
  hppa_rtems_isr_entry spurious_handler;
 
  unsigned32   itimer_clicks_per_microsecond; /* for use by Clock driver */
}   rtems_cpu_table;
 
/*
 *  Macros to access required entires in the CPU Table are in
 *  the file rtems/system.h.
 */
 
/*
 *  Macros to access HPPA specific additions to the CPU Table
 */
 
#define rtems_cpu_configuration_get_spurious_handler() \
   (_CPU_Table.spurious_handler)
 
#define rtems_cpu_configuration_get_itimer_clicks_per_microsecond() \
   (_CPU_Table.itimer_clicks_per_microsecond)
 
/* variables */
 
SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
SCORE_EXTERN unsigned32          _CPU_Default_gr27;
SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
 
#endif          /* ! ASM */
 
/*
 *  context sizes
 */
 
#ifndef ASM
#define CPU_CONTEXT_SIZE     sizeof( Context_Control )
#define CPU_CONTEXT_FP_SIZE  sizeof( Context_Control_fp )
#endif
 
/*
 *  size of a frame on the stack
 */
 
#define CPU_FRAME_SIZE (16 * 4)
 
/*
 * (Optional) # of bytes for libmisc/stackchk to check
 * If not specifed, then it defaults to something reasonable
 * for most architectures.
 */
 
#define CPU_STACK_CHECK_SIZE    (CPU_FRAME_SIZE * 2)
 
/*
 *  extra stack required by the MPCI receive server thread
 */
 
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
 
/*
 * HPPA has 32 traps, then 32 external interrupts
 * Rtems (_ISR_Vector_Table) is aware ONLY of the first 32
 * The BSP is aware of the external interrupts and possibly more.
 *
 */
 
#define CPU_INTERRUPT_NUMBER_OF_VECTORS      (HPPA_INTERNAL_TRAPS)
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
 
/*
 * Don't be chintzy here; we don't want to debug these problems
 * Some of the tests eat almost 4k.
 * Plus, the HPPA always allocates chunks of 64 bytes for stack
 *       growth.
 */
 
#define CPU_STACK_MINIMUM_SIZE          (8 * 1024)
 
/*
 * HPPA double's must be on 8 byte boundary
 */
 
#define CPU_ALIGNMENT              8
 
/*
 * just follow the basic HPPA alignment for the heap and partition
 */
 
#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
 
/*
 * HPPA stack is best when 64 byte aligned.
 */
 
#define CPU_STACK_ALIGNMENT        64
 
#ifndef ASM
 
/* macros */
 
/*
 *  ISR handler macros
 *
 *  These macros perform the following functions:
 *     + disable all maskable CPU interrupts
 *     + restore previous interrupt level (enable)
 *     + temporarily restore interrupts (flash)
 *     + set a particular level
 */
 
/* Disable interrupts; returning previous psw bits in _isr_level */
#define _CPU_ISR_Disable( _isr_level ) \
  do { \
         HPPA_ASM_RSM(HPPA_PSW_I, _isr_level);         \
         if (_isr_level & HPPA_PSW_I) _isr_level = 0;  \
         else                          _isr_level = 1; \
  } while(0)
 
/* Enable interrupts to previous level from _CPU_ISR_Disable
 * does not change 'level' */
#define _CPU_ISR_Enable( _isr_level )  \
  { \
        register int _ignore; \
        if (_isr_level == 0) HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \
        else                 HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \
  }
 
/* restore, then disable interrupts; does not change level */
#define _CPU_ISR_Flash( _isr_level ) \
  { \
        if (_isr_level == 0) \
        { \
              register int _ignore;  \
              HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \
              HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \
        } \
  }
 
/*
 * Interrupt task levels
 *
 * Future scheme proposal
 *      level will be an index into a array.
 *      Each entry of array will be the interrupt bits
 *        enabled for that level.  There will be 32 bits of external
 *        interrupts (to be placed in EIEM) and some (optional) bsp
 *        specific bits
 *
 * For pixel flow this *may* mean something like:
 *      level 0:   all interrupts enabled (external + rhino)
 *      level 1:   rhino disabled
 *      level 2:   all io interrupts disabled (timer still enabled)
 *      level 7:   *ALL* disabled (timer disabled)
 */
 
/* set interrupts on or off; does not return new level */
#define _CPU_ISR_Set_level( new_level ) \
  { \
        volatile int ignore; \
        if ( new_level )  HPPA_ASM_RSM(HPPA_PSW_I, ignore); \
        else              HPPA_ASM_SSM(HPPA_PSW_I, ignore); \
  }
 
/* return current level */
unsigned32 _CPU_ISR_Get_level( void );
 
/* end of ISR handler macros */
 
/*
 *  Context handler macros
 *
 *  These macros perform the following functions:
 *     + initialize a context area
 *     + restart the current thread
 *     + calculate the initial pointer into a FP context area
 *     + initialize an FP context area
 *
 *  HPPA port adds two macros which hide the "indirectness" of the
 *  pointer passed the save/restore FP context assembly routines.
 */
 
#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
                                  _new_level, _entry_point, _is_fp ) \
  do { \
    unsigned32 _stack; \
    \
    (_the_context)->flags = 0xfeedf00d; \
    (_the_context)->pcoqfront = (unsigned32)(_entry_point); \
    (_the_context)->pcoqback  = (unsigned32)(_entry_point) + 4; \
    (_the_context)->pcsqfront = 0; \
    (_the_context)->pcsqback  = 0; \
    if ( (_new_level) ) \
        (_the_context)->ipsw = CPU_PSW_INTERRUPTS_OFF; \
    else \
        (_the_context)->ipsw = CPU_PSW_INTERRUPTS_ON; \
    \
    _stack = ((unsigned32)(_stack_base) + (CPU_STACK_ALIGNMENT - 1)); \
    _stack &= ~(CPU_STACK_ALIGNMENT - 1); \
    if ((_stack - (unsigned32) (_stack_base)) < CPU_FRAME_SIZE) \
       _stack += CPU_FRAME_SIZE; \
    \
    (_the_context)->sp = (_stack); \
    (_the_context)->gr27 = _CPU_Default_gr27; \
  } while (0)
 
#define _CPU_Context_Restart_self( _the_context ) \
    do { \
         _CPU_Context_restore( (_the_context) ); \
    } while (0)
 
#define _CPU_Context_Fp_start( _base, _offset ) \
   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
 
#define _CPU_Context_Initialize_fp( _destination ) \
  do { \
    *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context;\
  } while(0)
 
#define _CPU_Context_save_fp( _fp_context ) \
   _CPU_Save_float_context( *(Context_Control_fp **)(_fp_context) )
 
#define _CPU_Context_restore_fp( _fp_context ) \
   _CPU_Restore_float_context( *(Context_Control_fp **)(_fp_context) )
 
/* end of Context handler macros */
 
/*
 *  Fatal Error manager macros
 *
 *  These macros perform the following functions:
 *    + disable interrupts and halt the CPU
 */
 
void    hppa_cpu_halt(unsigned32 the_error);
#define _CPU_Fatal_halt( _error ) \
    hppa_cpu_halt(_error)
 
/* end of Fatal Error manager macros */
 
/*
 *  Bitfield handler macros
 *
 *  These macros perform the following functions:
 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
 *
 *  NOTE:
 *
 *  The HPPA does not have a scan instruction.  This functionality
 *  is implemented in software.
 */
 
#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
 
int hppa_rtems_ffs(unsigned int value);
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
    _output = hppa_rtems_ffs(_value)
 
/* end of Bitfield handler macros */
 
/*
 *  Priority handler macros
 *
 *  These macros perform the following functions:
 *    + return a mask with the bit for this major/minor portion of
 *      of thread priority set.
 *    + translate the bit number returned by "Bitfield_find_first_bit"
 *      into an index into the thread ready chain bit maps
 *
 *  Note: 255 is the lowest priority
 */
 
#define _CPU_Priority_Mask( _bit_number ) \
  ( 1 << (_bit_number) )
 
#define _CPU_Priority_bits_index( _priority ) \
  (_priority)
 
/* end of Priority handler macros */
 
/* functions */
 
/*
 *  _CPU_Initialize
 *
 *  This routine performs CPU dependent initialization.
 */
 
void _CPU_Initialize(
  rtems_cpu_table  *cpu_table,
  void      (*thread_dispatch)
);
 
/*
 *  _CPU_ISR_install_raw_handler
 *
 *  This routine installs a "raw" interrupt handler directly into the
 *  processor's vector table.
 */
 
void _CPU_ISR_install_raw_handler(
  unsigned32  vector,
  proc_ptr    new_handler,
  proc_ptr   *old_handler
);
 
/*
 *  _CPU_ISR_install_vector
 *
 *  This routine installs an interrupt vector.
 */
 
void _CPU_ISR_install_vector(
  unsigned32  vector,
  proc_ptr    new_handler,
  proc_ptr   *old_handler
);
 
/*
 *  _CPU_Context_switch
 *
 *  This routine switches from the run context to the heir context.
 */
 
void _CPU_Context_switch(
  Context_Control  *run,
  Context_Control  *heir
);
 
/*
 *  _CPU_Context_restore
 *
 *  This routine is generally used only to restart self in an
 *  efficient manner and avoid stack conflicts.
 */
 
void _CPU_Context_restore(
  Context_Control *new_context
);
 
/*
 *  _CPU_Save_float_context
 *
 *  This routine saves the floating point context passed to it.
 *
 *  NOTE:  _CPU_Context_save_fp is implemented as a macro on the HPPA
 *         which dereferences the pointer before calling this.
 */
 
void _CPU_Save_float_context(
  Context_Control_fp *fp_context
);
 
/*
 *  _CPU_Restore_float_context
 *
 *  This routine restores the floating point context passed to it.
 *
 *  NOTE:  _CPU_Context_save_fp is implemented as a macro on the HPPA
 *         which dereferences the pointer before calling this.
 */
 
void _CPU_Restore_float_context(
  Context_Control_fp *fp_context
);
 
 
/*
 * The raw interrupt handler for external interrupts
 */
 
extern void _Generic_ISR_Handler(
    void
);
 
 
/*  The following routine swaps the endian format of an unsigned int.
 *  It must be static so it can be referenced indirectly.
 */
 
static inline unsigned int
CPU_swap_u32(unsigned32 value)
{
  unsigned32 swapped;
 
  HPPA_ASM_SWAPBYTES(value, swapped);
 
  return( swapped );
}
 
#define CPU_swap_u16( value ) \
  (((value&0xff) << 8) | ((value >> 8)&0xff))
 
#endif   /* ! ASM */
 
#ifdef __cplusplus
}
#endif
 
#endif   /* ! __CPU_h */

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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [hppa1.1/] [rtems/] [score/] [cpu.h] - Blame information for rev 173

Line No.	Rev	Author	Line
1	30	unneback	`/* cpu.h`
2			`*`
3			`* This include file contains information pertaining to the HP`
4			`* PA-RISC processor (Level 1.1).`
5			`*`
6			`* COPYRIGHT (c) 1994 by Division Incorporated`
7			`*`
8			`* The license and distribution terms for this file may be`
9			`* found in the file LICENSE in this distribution or at`
10			`* http://www.OARcorp.com/rtems/license.html.`
11			`*`
12			`* Note:`
13			`* This file is included by both C and assembler code ( -DASM )`
14			`*`
15			`* $Id: cpu.h,v 1.2 2001-09-27 11:59:24 chris Exp $`
16			`*/`
17
18			`#ifndef __CPU_h`
19			`#define __CPU_h`
20
21			`#ifdef __cplusplus`
22			`extern "C" {`
23			`#endif`
24
25			`#include <rtems/score/hppa.h> /* pick up machine definitions */`
26			`#ifndef ASM`
27			`#include <rtems/score/hppatypes.h>`
28			`#endif`
29
30			`/* conditional compilation parameters */`
31
32			`#define CPU_INLINE_ENABLE_DISPATCH FALSE`
33			`#define CPU_UNROLL_ENQUEUE_PRIORITY TRUE`
34
35			`/*`
36			`* RTEMS manages an interrupt stack in software for the HPPA.`
37			`*/`
38
39			`#define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE`
40			`#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE`
41			`#define CPU_ALLOCATE_INTERRUPT_STACK TRUE`
42
43			`/*`
44			`* Does the RTEMS invoke the user's ISR with the vector number and`
45			`* a pointer to the saved interrupt frame (1) or just the vector`
46			`* number (0)?`
47			`*/`
48
49			`#define CPU_ISR_PASSES_FRAME_POINTER 0`
50
51			`/*`
52			`* HPPA has hardware FP, it is assumed to exist by GCC so all tasks`
53			`* may implicitly use it (especially for integer multiplies). Because`
54			`* the FP context is technically part of the basic integer context`
55			`* on this CPU, we cannot use the deferred FP context switch algorithm.`
56			`*/`
57
58			`#define CPU_HARDWARE_FP TRUE`
59			`#define CPU_ALL_TASKS_ARE_FP TRUE`
60			`#define CPU_IDLE_TASK_IS_FP FALSE`
61			`#define CPU_USE_DEFERRED_FP_SWITCH FALSE`
62
63			`#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE`
64			`#define CPU_STACK_GROWS_UP TRUE`
65			`#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((__aligned__ (32)))`
66
67			`/*`
68			`* Define what is required to specify how the network to host conversion`
69			`* routines are handled.`
70			`*/`
71
72			`#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE`
73			`#define CPU_BIG_ENDIAN TRUE`
74			`#define CPU_LITTLE_ENDIAN FALSE`
75
76			`/* constants */`
77
78			`#define CPU_MODES_INTERRUPT_LEVEL 0x00000001 /* interrupt level in mode */`
79			`#define CPU_MODES_INTERRUPT_MASK 0x00000001 /* interrupt level in mode */`
80
81			`/*`
82			`* PSW contstants`
83			`*/`
84
85			`#define CPU_PSW_BASE (HPPA_PSW_C \| HPPA_PSW_Q \| HPPA_PSW_P \| HPPA_PSW_D)`
86			`#define CPU_PSW_INTERRUPTS_ON (CPU_PSW_BASE \| HPPA_PSW_I)`
87			`#define CPU_PSW_INTERRUPTS_OFF (CPU_PSW_BASE)`
88
89			`#define CPU_PSW_DEFAULT CPU_PSW_BASE`
90
91
92			`#ifndef ASM`
93
94			`/*`
95			`* Contexts`
96			`*`
97			`* This means we have the following context items:`
98			`* 1. task level context stuff:: Context_Control`
99			`* 2. floating point task stuff:: Context_Control_fp`
100			`*`
101			`* The PA-RISC is very fast so the expense of saving an extra register`
102			`* or two is not of great concern at the present. So we are not making`
103			`* a distinction between what is saved during a task switch and what is`
104			`* saved at each interrupt. Plus saving the entire context should make`
105			`* it easier to make gdb aware of RTEMS tasks.`
106			`*/`
107
108			`typedef struct {`
109			`unsigned32 flags; /* whatever */`
110			`unsigned32 gr1; /* scratch -- caller saves */`
111			`unsigned32 gr2; /* RP -- return pointer */`
112			`unsigned32 gr3; /* scratch -- callee saves */`
113			`unsigned32 gr4; /* scratch -- callee saves */`
114			`unsigned32 gr5; /* scratch -- callee saves */`
115			`unsigned32 gr6; /* scratch -- callee saves */`
116			`unsigned32 gr7; /* scratch -- callee saves */`
117			`unsigned32 gr8; /* scratch -- callee saves */`
118			`unsigned32 gr9; /* scratch -- callee saves */`
119			`unsigned32 gr10; /* scratch -- callee saves */`
120			`unsigned32 gr11; /* scratch -- callee saves */`
121			`unsigned32 gr12; /* scratch -- callee saves */`
122			`unsigned32 gr13; /* scratch -- callee saves */`
123			`unsigned32 gr14; /* scratch -- callee saves */`
124			`unsigned32 gr15; /* scratch -- callee saves */`
125			`unsigned32 gr16; /* scratch -- callee saves */`
126			`unsigned32 gr17; /* scratch -- callee saves */`
127			`unsigned32 gr18; /* scratch -- callee saves */`
128			`unsigned32 gr19; /* scratch -- caller saves */`
129			`unsigned32 gr20; /* scratch -- caller saves */`
130			`unsigned32 gr21; /* scratch -- caller saves */`
131			`unsigned32 gr22; /* scratch -- caller saves */`
132			`unsigned32 gr23; /* argument 3 */`
133			`unsigned32 gr24; /* argument 2 */`
134			`unsigned32 gr25; /* argument 1 */`
135			`unsigned32 gr26; /* argument 0 */`
136			`unsigned32 gr27; /* DP -- global data pointer */`
137			`unsigned32 gr28; /* return values -- caller saves */`
138			`unsigned32 gr29; /* return values -- caller saves */`
139			`unsigned32 sp; /* gr30 */`
140			`unsigned32 gr31;`
141
142			`/* Various control registers */`
143
144			`unsigned32 sar; /* cr11 */`
145			`unsigned32 ipsw; /* cr22; full 32 bits of psw */`
146			`unsigned32 iir; /* cr19; interrupt instruction register */`
147			`unsigned32 ior; /* cr21; interrupt offset register */`
148			`unsigned32 isr; /* cr20; interrupt space register (not used) */`
149			`unsigned32 pcoqfront; /* cr18; front que offset */`
150			`unsigned32 pcoqback; /* cr18; back que offset */`
151			`unsigned32 pcsqfront; /* cr17; front que space (not used) */`
152			`unsigned32 pcsqback; /* cr17; back que space (not used) */`
153			`unsigned32 itimer; /* cr16; itimer value */`
154
155			`} Context_Control;`
156
157
158			`/* Must be double word aligned.`
159			`* This will be ok since our allocator returns 8 byte aligned chunks`
160			`*/`
161
162			`typedef struct {`
163			`double fr0; /* status */`
164			`double fr1; /* exception information */`
165			`double fr2; /* exception information */`
166			`double fr3; /* exception information */`
167			`double fr4; /* argument */`
168			`double fr5; /* argument */`
169			`double fr6; /* argument */`
170			`double fr7; /* argument */`
171			`double fr8; /* scratch -- caller saves */`
172			`double fr9; /* scratch -- caller saves */`
173			`double fr10; /* scratch -- caller saves */`
174			`double fr11; /* scratch -- caller saves */`
175			`double fr12; /* callee saves -- (PA-RISC 1.1 CPUs) */`
176			`double fr13; /* callee saves -- (PA-RISC 1.1 CPUs) */`
177			`double fr14; /* callee saves -- (PA-RISC 1.1 CPUs) */`
178			`double fr15; /* callee saves -- (PA-RISC 1.1 CPUs) */`
179			`double fr16; /* callee saves -- (PA-RISC 1.1 CPUs) */`
180			`double fr17; /* callee saves -- (PA-RISC 1.1 CPUs) */`
181			`double fr18; /* callee saves -- (PA-RISC 1.1 CPUs) */`
182			`double fr19; /* callee saves -- (PA-RISC 1.1 CPUs) */`
183			`double fr20; /* callee saves -- (PA-RISC 1.1 CPUs) */`
184			`double fr21; /* callee saves -- (PA-RISC 1.1 CPUs) */`
185			`double fr22; /* caller saves -- (PA-RISC 1.1 CPUs) */`
186			`double fr23; /* caller saves -- (PA-RISC 1.1 CPUs) */`
187			`double fr24; /* caller saves -- (PA-RISC 1.1 CPUs) */`
188			`double fr25; /* caller saves -- (PA-RISC 1.1 CPUs) */`
189			`double fr26; /* caller saves -- (PA-RISC 1.1 CPUs) */`
190			`double fr27; /* caller saves -- (PA-RISC 1.1 CPUs) */`
191			`double fr28; /* caller saves -- (PA-RISC 1.1 CPUs) */`
192			`double fr29; /* caller saves -- (PA-RISC 1.1 CPUs) */`
193			`double fr30; /* caller saves -- (PA-RISC 1.1 CPUs) */`
194			`double fr31; /* caller saves -- (PA-RISC 1.1 CPUs) */`
195			`} Context_Control_fp;`
196
197			`/*`
198			`* The following structure defines the set of information saved`
199			`* on the current stack by RTEMS upon receipt of each interrupt.`
200			`*/`
201
202			`typedef struct {`
203			`Context_Control Integer;`
204			`Context_Control_fp Floating_Point;`
205			`} CPU_Interrupt_frame;`
206
207			`/*`
208			`* Our interrupt handlers take a 2nd argument:`
209			`* a pointer to a CPU_Interrupt_frame`
210			`* So we use our own prototype instead of rtems_isr_entry`
211			`*/`
212
213			`typedef void ( *hppa_rtems_isr_entry )(`
214			`unsigned32,`
215			`CPU_Interrupt_frame *`
216			`);`
217
218			`/*`
219			`* The following table contains the information required to configure`
220			`* the HPPA specific parameters.`
221			`*/`
222
223			`typedef struct {`
224			`void (*pretasking_hook)( void );`
225			`void (*predriver_hook)( void );`
226			`void (*postdriver_hook)( void );`
227			`void (*idle_task)( void );`
228			`boolean do_zero_of_workspace;`
229			`unsigned32 idle_task_stack_size;`
230			`unsigned32 interrupt_stack_size;`
231			`unsigned32 extra_mpci_receive_server_stack;`
232			`void * (*stack_allocate_hook)( unsigned32 );`
233			`void (stack_free_hook)( void );`
234			`/* end of fields required on all CPUs */`
235
236			`hppa_rtems_isr_entry spurious_handler;`
237
238			`unsigned32 itimer_clicks_per_microsecond; /* for use by Clock driver */`
239			`} rtems_cpu_table;`
240
241			`/*`
242			`* Macros to access required entires in the CPU Table are in`
243			`* the file rtems/system.h.`
244			`*/`
245
246			`/*`
247			`* Macros to access HPPA specific additions to the CPU Table`
248			`*/`
249
250			`#define rtems_cpu_configuration_get_spurious_handler() \`
251			`(_CPU_Table.spurious_handler)`
252
253			`#define rtems_cpu_configuration_get_itimer_clicks_per_microsecond() \`
254			`(_CPU_Table.itimer_clicks_per_microsecond)`
255
256			`/* variables */`
257
258			`SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context;`
259			`SCORE_EXTERN unsigned32 _CPU_Default_gr27;`
260			`SCORE_EXTERN void *_CPU_Interrupt_stack_low;`
261			`SCORE_EXTERN void *_CPU_Interrupt_stack_high;`
262
263			`#endif /* ! ASM */`
264
265			`/*`
266			`* context sizes`
267			`*/`
268
269			`#ifndef ASM`
270			`#define CPU_CONTEXT_SIZE sizeof( Context_Control )`
271			`#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )`
272			`#endif`
273
274			`/*`
275			`* size of a frame on the stack`
276			`*/`
277
278			`#define CPU_FRAME_SIZE (16 * 4)`
279
280			`/*`
281			`* (Optional) # of bytes for libmisc/stackchk to check`
282			`* If not specifed, then it defaults to something reasonable`
283			`* for most architectures.`
284			`*/`
285
286			`#define CPU_STACK_CHECK_SIZE (CPU_FRAME_SIZE * 2)`
287
288			`/*`
289			`* extra stack required by the MPCI receive server thread`
290			`*/`
291
292			`#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0`
293
294			`/*`
295			`* HPPA has 32 traps, then 32 external interrupts`
296			`* Rtems (_ISR_Vector_Table) is aware ONLY of the first 32`
297			`* The BSP is aware of the external interrupts and possibly more.`
298			`*`
299			`*/`
300
301			`#define CPU_INTERRUPT_NUMBER_OF_VECTORS (HPPA_INTERNAL_TRAPS)`
302			`#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)`
303
304			`/*`
305			`* Don't be chintzy here; we don't want to debug these problems`
306			`* Some of the tests eat almost 4k.`
307			`* Plus, the HPPA always allocates chunks of 64 bytes for stack`
308			`* growth.`
309			`*/`
310
311			`#define CPU_STACK_MINIMUM_SIZE (8 * 1024)`
312
313			`/*`
314			`* HPPA double's must be on 8 byte boundary`
315			`*/`
316
317			`#define CPU_ALIGNMENT 8`
318
319			`/*`
320			`* just follow the basic HPPA alignment for the heap and partition`
321			`*/`
322
323			`#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT`
324			`#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT`
325
326			`/*`
327			`* HPPA stack is best when 64 byte aligned.`
328			`*/`
329
330			`#define CPU_STACK_ALIGNMENT 64`
331
332			`#ifndef ASM`
333
334			`/* macros */`
335
336			`/*`
337			`* ISR handler macros`
338			`*`
339			`* These macros perform the following functions:`
340			`* + disable all maskable CPU interrupts`
341			`* + restore previous interrupt level (enable)`
342			`* + temporarily restore interrupts (flash)`
343			`* + set a particular level`
344			`*/`
345
346			`/* Disable interrupts; returning previous psw bits in _isr_level */`
347			`#define _CPU_ISR_Disable( _isr_level ) \`
348			`do { \`
349			`HPPA_ASM_RSM(HPPA_PSW_I, _isr_level); \`
350			`if (_isr_level & HPPA_PSW_I) _isr_level = 0; \`
351			`else _isr_level = 1; \`
352			`} while(0)`
353
354			`/* Enable interrupts to previous level from _CPU_ISR_Disable`
355			`* does not change 'level' */`
356			`#define _CPU_ISR_Enable( _isr_level ) \`
357			`{ \`
358			`register int _ignore; \`
359			`if (_isr_level == 0) HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \`
360			`else HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \`
361			`}`
362
363			`/* restore, then disable interrupts; does not change level */`
364			`#define _CPU_ISR_Flash( _isr_level ) \`
365			`{ \`
366			`if (_isr_level == 0) \`
367			`{ \`
368			`register int _ignore; \`
369			`HPPA_ASM_SSM(HPPA_PSW_I, _ignore); \`
370			`HPPA_ASM_RSM(HPPA_PSW_I, _ignore); \`
371			`} \`
372			`}`
373
374			`/*`
375			`* Interrupt task levels`
376			`*`
377			`* Future scheme proposal`
378			`* level will be an index into a array.`
379			`* Each entry of array will be the interrupt bits`
380			`* enabled for that level. There will be 32 bits of external`
381			`* interrupts (to be placed in EIEM) and some (optional) bsp`
382			`* specific bits`
383			`*`
384			`* For pixel flow this may mean something like:`
385			`* level 0: all interrupts enabled (external + rhino)`
386			`* level 1: rhino disabled`
387			`* level 2: all io interrupts disabled (timer still enabled)`
388			`* level 7: ALL disabled (timer disabled)`
389			`*/`
390
391			`/* set interrupts on or off; does not return new level */`
392			`#define _CPU_ISR_Set_level( new_level ) \`
393			`{ \`
394			`volatile int ignore; \`
395			`if ( new_level ) HPPA_ASM_RSM(HPPA_PSW_I, ignore); \`
396			`else HPPA_ASM_SSM(HPPA_PSW_I, ignore); \`
397			`}`
398
399			`/* return current level */`
400			`unsigned32 _CPU_ISR_Get_level( void );`
401
402			`/* end of ISR handler macros */`
403
404			`/*`
405			`* Context handler macros`
406			`*`
407			`* These macros perform the following functions:`
408			`* + initialize a context area`
409			`* + restart the current thread`
410			`* + calculate the initial pointer into a FP context area`
411			`* + initialize an FP context area`
412			`*`
413			`* HPPA port adds two macros which hide the "indirectness" of the`
414			`* pointer passed the save/restore FP context assembly routines.`
415			`*/`
416
417			`#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \`
418			`_new_level, _entry_point, _is_fp ) \`
419			`do { \`
420			`unsigned32 _stack; \`
421			`\`
422			`(_the_context)->flags = 0xfeedf00d; \`
423			`(_the_context)->pcoqfront = (unsigned32)(_entry_point); \`
424			`(_the_context)->pcoqback = (unsigned32)(_entry_point) + 4; \`
425			`(_the_context)->pcsqfront = 0; \`
426			`(_the_context)->pcsqback = 0; \`
427			`if ( (_new_level) ) \`
428			`(_the_context)->ipsw = CPU_PSW_INTERRUPTS_OFF; \`
429			`else \`
430			`(_the_context)->ipsw = CPU_PSW_INTERRUPTS_ON; \`
431			`\`
432			`_stack = ((unsigned32)(_stack_base) + (CPU_STACK_ALIGNMENT - 1)); \`
433			`_stack &= ~(CPU_STACK_ALIGNMENT - 1); \`
434			`if ((_stack - (unsigned32) (_stack_base)) < CPU_FRAME_SIZE) \`
435			`_stack += CPU_FRAME_SIZE; \`
436			`\`
437			`(_the_context)->sp = (_stack); \`
438			`(_the_context)->gr27 = _CPU_Default_gr27; \`
439			`} while (0)`
440
441			`#define _CPU_Context_Restart_self( _the_context ) \`
442			`do { \`
443			`_CPU_Context_restore( (_the_context) ); \`
444			`} while (0)`
445
446			`#define _CPU_Context_Fp_start( _base, _offset ) \`
447			`( (void *) _Addresses_Add_offset( (_base), (_offset) ) )`
448
449			`#define _CPU_Context_Initialize_fp( _destination ) \`
450			`do { \`
451			`((Context_Control_fp ) ((void *) _destination)) = _CPU_Null_fp_context;\`
452			`} while(0)`
453
454			`#define _CPU_Context_save_fp( _fp_context ) \`
455			`_CPU_Save_float_context( (Context_Control_fp *)(_fp_context) )`
456
457			`#define _CPU_Context_restore_fp( _fp_context ) \`
458			`_CPU_Restore_float_context( (Context_Control_fp *)(_fp_context) )`
459
460			`/* end of Context handler macros */`
461
462			`/*`
463			`* Fatal Error manager macros`
464			`*`
465			`* These macros perform the following functions:`
466			`* + disable interrupts and halt the CPU`
467			`*/`
468
469			`void hppa_cpu_halt(unsigned32 the_error);`
470			`#define _CPU_Fatal_halt( _error ) \`
471			`hppa_cpu_halt(_error)`
472
473			`/* end of Fatal Error manager macros */`
474
475			`/*`
476			`* Bitfield handler macros`
477			`*`
478			`* These macros perform the following functions:`
479			`* + scan for the highest numbered (MSB) set in a 16 bit bitfield`
480			`*`
481			`* NOTE:`
482			`*`
483			`* The HPPA does not have a scan instruction. This functionality`
484			`* is implemented in software.`
485			`*/`
486
487			`#define CPU_USE_GENERIC_BITFIELD_CODE FALSE`
488			`#define CPU_USE_GENERIC_BITFIELD_DATA FALSE`
489
490			`int hppa_rtems_ffs(unsigned int value);`
491			`#define _CPU_Bitfield_Find_first_bit( _value, _output ) \`
492			`_output = hppa_rtems_ffs(_value)`
493
494			`/* end of Bitfield handler macros */`
495
496			`/*`
497			`* Priority handler macros`
498			`*`
499			`* These macros perform the following functions:`
500			`* + return a mask with the bit for this major/minor portion of`
501			`* of thread priority set.`
502			`* + translate the bit number returned by "Bitfield_find_first_bit"`
503			`* into an index into the thread ready chain bit maps`
504			`*`
505			`* Note: 255 is the lowest priority`
506			`*/`
507
508			`#define _CPU_Priority_Mask( _bit_number ) \`
509			`( 1 << (_bit_number) )`
510
511			`#define _CPU_Priority_bits_index( _priority ) \`
512			`(_priority)`
513
514			`/* end of Priority handler macros */`
515
516			`/* functions */`
517
518			`/*`
519			`* _CPU_Initialize`
520			`*`
521			`* This routine performs CPU dependent initialization.`
522			`*/`
523
524			`void _CPU_Initialize(`
525			`rtems_cpu_table *cpu_table,`
526			`void (*thread_dispatch)`
527			`);`
528
529			`/*`
530			`* _CPU_ISR_install_raw_handler`
531			`*`
532			`* This routine installs a "raw" interrupt handler directly into the`
533			`* processor's vector table.`
534			`*/`
535
536			`void _CPU_ISR_install_raw_handler(`
537			`unsigned32 vector,`
538			`proc_ptr new_handler,`
539			`proc_ptr *old_handler`
540			`);`
541
542			`/*`
543			`* _CPU_ISR_install_vector`
544			`*`
545			`* This routine installs an interrupt vector.`
546			`*/`
547
548			`void _CPU_ISR_install_vector(`
549			`unsigned32 vector,`
550			`proc_ptr new_handler,`
551			`proc_ptr *old_handler`
552			`);`
553
554			`/*`
555			`* _CPU_Context_switch`
556			`*`
557			`* This routine switches from the run context to the heir context.`
558			`*/`
559
560			`void _CPU_Context_switch(`
561			`Context_Control *run,`
562			`Context_Control *heir`
563			`);`
564
565			`/*`
566			`* _CPU_Context_restore`
567			`*`
568			`* This routine is generally used only to restart self in an`
569			`* efficient manner and avoid stack conflicts.`
570			`*/`
571
572			`void _CPU_Context_restore(`
573			`Context_Control *new_context`
574			`);`
575
576			`/*`
577			`* _CPU_Save_float_context`
578			`*`
579			`* This routine saves the floating point context passed to it.`
580			`*`
581			`* NOTE: _CPU_Context_save_fp is implemented as a macro on the HPPA`
582			`* which dereferences the pointer before calling this.`
583			`*/`
584
585			`void _CPU_Save_float_context(`
586			`Context_Control_fp *fp_context`
587			`);`
588
589			`/*`
590			`* _CPU_Restore_float_context`
591			`*`
592			`* This routine restores the floating point context passed to it.`
593			`*`
594			`* NOTE: _CPU_Context_save_fp is implemented as a macro on the HPPA`
595			`* which dereferences the pointer before calling this.`
596			`*/`
597
598			`void _CPU_Restore_float_context(`
599			`Context_Control_fp *fp_context`
600			`);`
601
602
603			`/*`
604			`* The raw interrupt handler for external interrupts`
605			`*/`
606
607			`extern void _Generic_ISR_Handler(`
608			`void`
609			`);`
610
611
612			`/* The following routine swaps the endian format of an unsigned int.`
613			`* It must be static so it can be referenced indirectly.`
614			`*/`
615
616			`static inline unsigned int`
617			`CPU_swap_u32(unsigned32 value)`
618			`{`
619			`unsigned32 swapped;`
620
621			`HPPA_ASM_SWAPBYTES(value, swapped);`
622
623			`return( swapped );`
624			`}`
625
626			`#define CPU_swap_u16( value ) \`
627			`(((value&0xff) << 8) \| ((value >> 8)&0xff))`
628
629			`#endif /* ! ASM */`
630
631			`#ifdef __cplusplus`
632			`}`
633			`#endif`
634
635			`#endif /* ! __CPU_h */`