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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [hppa1.1/] [rtems/] [score/] [cpu_asm.h] - Blame information for rev 593

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1 30 unneback
/*
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 * Copyright (c) 1990,1991 The University of Utah and
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 * the Center for Software Science (CSS).  All rights reserved.
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 *
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 * Permission to use, copy, modify and distribute this software is hereby
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 * granted provided that (1) source code retains these copyright, permission,
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 * and disclaimer notices, and (2) redistributions including binaries
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 * reproduce the notices in supporting documentation, and (3) all advertising
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 * materials mentioning features or use of this software display the following
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 * acknowledgement: ``This product includes software developed by the Center
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 * for Software Science at the University of Utah.''
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 *
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 * THE UNIVERSITY OF UTAH AND CSS ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
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 * IS" CONDITION.  THE UNIVERSITY OF UTAH AND CSS DISCLAIM ANY LIABILITY OF
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 * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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 *
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 * CSS requests users of this software to return to css-dist@cs.utah.edu any
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 * improvements that they make and grant CSS redistribution rights.
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 *
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 *      Utah $Hdr: asm.h 1.6 91/12/03$
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 *
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 *  $Id: cpu_asm.h,v 1.2 2001-09-27 11:59:24 chris Exp $
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 */
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/*
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 * Hardware Space Registers
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 */
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sr0     .reg    %sr0
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sr1     .reg    %sr1
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sr2     .reg    %sr2
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sr3     .reg    %sr3
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sr4     .reg    %sr4
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sr5     .reg    %sr5
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sr6     .reg    %sr6
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sr7     .reg    %sr7
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/*
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 * Control register aliases
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 */
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rctr    .reg    %cr0
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pidr1   .reg    %cr8
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pidr2   .reg    %cr9
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ccr     .reg    %cr10
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sar     .reg    %cr11
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pidr3   .reg    %cr12
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pidr4   .reg    %cr13
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iva     .reg    %cr14
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eiem    .reg    %cr15
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itmr    .reg    %cr16
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pcsq    .reg    %cr17
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pcoq    .reg    %cr18
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iir     .reg    %cr19
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isr     .reg    %cr20
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ior     .reg    %cr21
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ipsw    .reg    %cr22
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eirr    .reg    %cr23
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/*
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 * Calling Convention
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 */
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rp      .reg    %r2
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arg3    .reg    %r23
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arg2    .reg    %r24
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arg1    .reg    %r25
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arg0    .reg    %r26
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dp      .reg    %r27
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ret0    .reg    %r28
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ret1    .reg    %r29
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sl      .reg    %r29
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sp      .reg    %r30
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