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/*
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* Description:
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*
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* Definitions for HP PA Risc
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* ref: PA RISC 1.1 Architecture and Instruction Set Reference Manual
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*
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* COPYRIGHT (c) 1994 by Division Incorporated
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* Note:
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* This file is included by both C and assembler code ( -DASM )
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*
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* $Id: hppa.h,v 1.2 2001-09-27 11:59:24 chris Exp $
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*/
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#ifndef _INCLUDE_HPPA_H
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#define _INCLUDE_HPPA_H
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#ifdef ASM
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#include <rtems/score/targopts.h>
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#endif
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*
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* This section contains the information required to build
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* RTEMS for a particular member of the Hewlett Packard
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* PA-RISC family. It does this by setting variables to
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* indicate which implementation dependent features are
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* present in a particular member of the family.
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*/
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#if defined(rtems_multilib)
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/*
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* Figure out all CPU Model Feature Flags based upon compiler
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* predefines.
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*/
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#define CPU_MODEL_NAME "rtems_multilib"
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#elif defined(hppa7100)
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#define CPU_MODEL_NAME "hppa 7100"
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#elif defined(hppa7200)
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#define CPU_MODEL_NAME "hppa 7200"
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#else
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#error "Unsupported CPU Model"
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#endif
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/*
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* Define the name of the CPU family.
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*/
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#if !defined(CPU_NAME)
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#define CPU_NAME "HP PA-RISC 1.1"
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#endif
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/*
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* Processor Status Word (PSW) Masks
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*/
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#define HPPA_PSW_Y 0x80000000 /* Data Debug Trap Disable */
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#define HPPA_PSW_Z 0x40000000 /* Instruction Debug Trap Disable */
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#define HPPA_PSW_r2 0x20000000 /* reserved */
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#define HPPA_PSW_r3 0x10000000 /* reserved */
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#define HPPA_PSW_r4 0x08000000 /* reserved */
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#define HPPA_PSW_E 0x04000000 /* Little Endian on Memory References */
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#define HPPA_PSW_S 0x02000000 /* Secure Interval Timer */
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#define HPPA_PSW_T 0x01000000 /* Taken Branch Trap Enable */
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#define HPPA_PSW_H 0x00800000 /* Higher-Privilege Transfer Trap Enable*/
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#define HPPA_PSW_L 0x00400000 /* Lower-Privilege Transfer Trap Enable */
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#define HPPA_PSW_N 0x00200000 /* PC Queue Front Instruction Nullified */
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#define HPPA_PSW_X 0x00100000 /* Data Memory Break Disable */
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#define HPPA_PSW_B 0x00080000 /* Taken Branch in Previous Cycle */
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#define HPPA_PSW_C 0x00040000 /* Code Address Translation Enable */
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#define HPPA_PSW_V 0x00020000 /* Divide Step Correction */
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#define HPPA_PSW_M 0x00010000 /* High-Priority Machine Check Disable */
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#define HPPA_PSW_CB 0x0000ff00 /* Carry/Borrow Bits */
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#define HPPA_PSW_r24 0x00000080 /* reserved */
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#define HPPA_PSW_G 0x00000040 /* Debug trap Enable */
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#define HPPA_PSW_F 0x00000020 /* Performance monitor interrupt unmask */
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#define HPPA_PSW_R 0x00000010 /* Recovery Counter Enable */
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#define HPPA_PSW_Q 0x00000008 /* Interruption State Collection Enable */
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#define HPPA_PSW_P 0x00000004 /* Protection ID Validation Enable */
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#define HPPA_PSW_D 0x00000002 /* Data Address Translation Enable */
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#define HPPA_PSW_I 0x00000001 /* External, Power Failure, */
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/* Low-Priority Machine Check */
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/* Interruption Enable */
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/*
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* HPPA traps and interrupts
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* basic layout. Note numbers do not denote priority
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*
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* 0-31 basic traps and interrupts defined by HPPA architecture
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* 0-31 32 external interrupts
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* 32-... bsp defined
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*/
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#define HPPA_TRAP_NON_EXISTENT 0
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/* group 1 */
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#define HPPA_TRAP_HIGH_PRIORITY_MACHINE_CHECK 1
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/* group 2 */
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#define HPPA_TRAP_POWER_FAIL 2
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#define HPPA_TRAP_RECOVERY_COUNTER 3
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#define HPPA_TRAP_EXTERNAL_INTERRUPT 4
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#define HPPA_TRAP_LOW_PRIORITY_MACHINE_CHECK 5
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#define HPPA_TRAP_PERFORMANCE_MONITOR 29
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/* group 3 */
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#define HPPA_TRAP_INSTRUCTION_TLB_MISS 6
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#define HPPA_TRAP_INSTRUCTION_MEMORY_PROTECTION 7
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#define HPPA_TRAP_INSTRUCTION_DEBUG 30
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#define HPPA_TRAP_ILLEGAL_INSTRUCTION 8
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#define HPPA_TRAP_BREAK_INSTRUCTION 9
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#define HPPA_TRAP_PRIVILEGED_OPERATION 10
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#define HPPA_TRAP_PRIVILEGED_REGISTER 11
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#define HPPA_TRAP_OVERFLOW 12
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#define HPPA_TRAP_CONDITIONAL 13
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#define HPPA_TRAP_ASSIST_EXCEPTION 14
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#define HPPA_TRAP_DATA_TLB_MISS 15
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#define HPPA_TRAP_NON_ACCESS_INSTRUCTION_TLB_MISS 16
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#define HPPA_TRAP_NON_ACCESS_DATA_TLB_MISS 17
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#define HPPA_TRAP_DATA_MEMORY_ACCESS_RIGHTS 26
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#define HPPA_TRAP_DATA_MEMORY_PROTECTION_ID 27
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#define HPPA_TRAP_UNALIGNED_DATA_REFERENCE 28
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#define HPPA_TRAP_DATA_MEMORY_PROTECTION 18
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#define HPPA_TRAP_DATA_MEMORY_BREAK 19
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#define HPPA_TRAP_TLB_DIRTY_BIT 20
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#define HPPA_TRAP_PAGE_REFERENCE 21
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#define HPPA_TRAP_DATA_DEBUG 31
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#define HPPA_TRAP_ASSIST_EMULATION 22
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/* group 4 */
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#define HPPA_TRAP_HIGHER_PRIVILEGE_TRANSFER 23
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#define HPPA_TRAP_LOWER_PRIVILEGE_TRANSFER 24
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#define HPPA_TRAP_TAKEN_BRANCH 25
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#define HPPA_INTERNAL_TRAPS 32
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/* External Interrupts via interrupt 4 */
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#define HPPA_INTERRUPT_EXTERNAL_0 0
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#define HPPA_INTERRUPT_EXTERNAL_1 1
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#define HPPA_INTERRUPT_EXTERNAL_2 2
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#define HPPA_INTERRUPT_EXTERNAL_3 3
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#define HPPA_INTERRUPT_EXTERNAL_4 4
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#define HPPA_INTERRUPT_EXTERNAL_5 5
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#define HPPA_INTERRUPT_EXTERNAL_6 6
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#define HPPA_INTERRUPT_EXTERNAL_7 7
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#define HPPA_INTERRUPT_EXTERNAL_8 8
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#define HPPA_INTERRUPT_EXTERNAL_9 9
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#define HPPA_INTERRUPT_EXTERNAL_10 10
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#define HPPA_INTERRUPT_EXTERNAL_11 11
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#define HPPA_INTERRUPT_EXTERNAL_12 12
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#define HPPA_INTERRUPT_EXTERNAL_13 13
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#define HPPA_INTERRUPT_EXTERNAL_14 14
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#define HPPA_INTERRUPT_EXTERNAL_15 15
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#define HPPA_INTERRUPT_EXTERNAL_16 16
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#define HPPA_INTERRUPT_EXTERNAL_17 17
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#define HPPA_INTERRUPT_EXTERNAL_18 18
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#define HPPA_INTERRUPT_EXTERNAL_19 19
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#define HPPA_INTERRUPT_EXTERNAL_20 20
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#define HPPA_INTERRUPT_EXTERNAL_21 21
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#define HPPA_INTERRUPT_EXTERNAL_22 22
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#define HPPA_INTERRUPT_EXTERNAL_23 23
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#define HPPA_INTERRUPT_EXTERNAL_24 24
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#define HPPA_INTERRUPT_EXTERNAL_25 25
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#define HPPA_INTERRUPT_EXTERNAL_26 26
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#define HPPA_INTERRUPT_EXTERNAL_27 27
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#define HPPA_INTERRUPT_EXTERNAL_28 28
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#define HPPA_INTERRUPT_EXTERNAL_29 29
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#define HPPA_INTERRUPT_EXTERNAL_30 30
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#define HPPA_INTERRUPT_EXTERNAL_31 31
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#define HPPA_INTERRUPT_EXTERNAL_INTERVAL_TIMER HPPA_INTERRUPT_EXTERNAL_0
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#define HPPA_EXTERNAL_INTERRUPTS 32
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/* BSP defined interrupts begin here */
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#define HPPA_INTERRUPT_MAX 32
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/*
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* Cache characteristics
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*/
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#define HPPA_CACHELINE_SIZE 32
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#define HPPA_CACHELINE_MASK (HPPA_CACHELINE_SIZE - 1)
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/*
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* page size characteristics
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*/
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#define HPPA_PAGE_SIZE 4096
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#define HPPA_PAGE_MASK (0xfffff000)
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/*
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* TLB characteristics
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*
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* Flags and Access Control layout for using TLB protection insertion
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*
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* 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
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* 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* |?|?|T|D|B|type |PL1|Pl2|U| access id |?|
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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*/
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/*
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* Access rights (type + PL1 + PL2)
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*/
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#define HPPA_PROT_R 0x00c00000 /* Read Only, no Write, no Execute */
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#define HPPA_PROT_RW 0x01c00000 /* Read & Write Only, no Execute */
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#define HPPA_PROT_RX 0x02c00000 /* Read & Execute Only, no Write */
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#define HPPA_PROT_RWX 0x03c00000 /* Read, Write, Execute */
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#define HPPA_PROT_X0 0x04c00000 /* Execute Only, Promote to Level 0 */
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#define HPPA_PROT_X1 0x05c00000 /* Execute Only, Promote to Level 1 */
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#define HPPA_PROT_X2 0x06c00000 /* Execute Only, Promote to Level 2 */
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#define HPPA_PROT_X3 0x07c00000 /* Execute Only, Promote to Level 3 */
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/*
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* Floating point status register definitions
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*/
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#define HPPA_FPSTATUS_ENABLE_I 0x00000001 /* inexact operation */
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#define HPPA_FPSTATUS_ENABLE_U 0x00000002 /* underflow */
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#define HPPA_FPSTATUS_ENABLE_O 0x00000004 /* overflow */
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#define HPPA_FPSTATUS_ENABLE_Z 0x00000008 /* division by zero */
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#define HPPA_FPSTATUS_ENABLE_V 0x00000010 /* invalid operation */
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#define HPPA_FPSTATUS_D 0x00000020 /* denormalize as zero */
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#define HPPA_FPSTATUS_T 0x00000040 /* delayed trap */
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#define HPPA_FPSTATUS_RM_MASK 0x00000600 /* rounding mode */
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#define HPPA_FPSTATUS_RM_SHIFT 9
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#define HPPA_FPSTATUS_CQ_MASK 0x001FFC00 /* compare queue */
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#define HPPA_FPSTATUS_CQ_SHIFT 13
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#define HPPA_FPSTATUS_C 0x04000000 /* most recent ompare bit */
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#define HPPA_FPSTATUS_FLAG_I 0x08000000 /* inexact */
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#define HPPA_FPSTATUS_FLAG_U 0x10000000 /* underflow */
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#define HPPA_FPSTATUS_FLAG_O 0x20000000 /* overflow */
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#define HPPA_FPSTATUS_FLAG_Z 0x40000000 /* division by zero */
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#define HPPA_FPSTATUS_FLAG_V 0x80000000 /* invalid operation */
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/*
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* Inline macros for misc. interesting opcodes
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*/
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/* generate a global label */
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#define HPPA_ASM_LABEL(label) \
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asm(".export " label ", ! .label " label);
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/* Return From Interrupt RFI */
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#define HPPA_ASM_RFI() asm volatile ("rfi")
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/* Set System Mask SSM i,t */
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#define HPPA_ASM_SSM(i,gr) asm volatile ("ssm %1, %0" \
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: "=r" (gr) \
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: "i" (i))
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/* Reset System Mask RSM i,t */
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#define HPPA_ASM_RSM(i,gr) asm volatile ("rsm %1, %0" \
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: "=r" (gr) \
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: "i" (i))
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/* Move To System Mask MTSM r */
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#define HPPA_ASM_MTSM(gr) asm volatile ("mtsm %0" \
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: : "r" (gr))
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/* Load Space Identifier LDSID (s,b),t */
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#define HPPA_ASM_LDSID(sr,grb,grt) asm volatile ("ldsid (%1,%2),%0" \
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: "=r" (grt) \
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: "i" (sr), \
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"r" (grb))
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/*
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* Gcc extended asm doesn't really allow for treatment of space registers
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* as "registers", so we have to use "i" format.
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* Unfortunately this means that the "=" constraint is not available.
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*/
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/* Move To Space Register MTSP r,sr */
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#define HPPA_ASM_MTSP(gr,sr) asm volatile ("mtsp %1,%0" \
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: : "i" (sr), \
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"r" (gr))
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| 294 |
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/* Move From Space Register MFSP sr,t */
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#define HPPA_ASM_MFSP(sr,gr) asm volatile ("mfsp %1,%0" \
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: "=r" (gr) \
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: "i" (sr))
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| 299 |
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/* Move To Control register MTCTL r,t */
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| 300 |
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#define HPPA_ASM_MTCTL(gr,cr) asm volatile ("mtctl %1,%0" \
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: : "i" (cr), \
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"r" (gr))
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/* Move From Control register MFCTL r,t */
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|
|
#define HPPA_ASM_MFCTL(cr,gr) asm volatile ("mfctl %1,%0" \
|
| 306 |
|
|
: "=r" (gr) \
|
| 307 |
|
|
: "i" (cr))
|
| 308 |
|
|
|
| 309 |
|
|
/* Synchronize caches SYNC */
|
| 310 |
|
|
#define HPPA_ASM_SYNC() asm volatile ("sync")
|
| 311 |
|
|
|
| 312 |
|
|
/* Probe Read Access PROBER (s,b),r,t */
|
| 313 |
|
|
#define HPPA_ASM_PROBER(sr,groff,gracc,grt) \
|
| 314 |
|
|
asm volatile ("prober (%1,%2),%3,%0" \
|
| 315 |
|
|
: "=r" (grt) \
|
| 316 |
|
|
: "i" (sr), \
|
| 317 |
|
|
"r" (groff), \
|
| 318 |
|
|
"r" (gracc))
|
| 319 |
|
|
|
| 320 |
|
|
/* Probe Read Access Immediate PROBERI (s,b),i,t*/
|
| 321 |
|
|
#define HPPA_ASM_PROBERI(sr,groff,iacc,grt) \
|
| 322 |
|
|
asm volatile ("proberi (%1,%2),%3,%0" \
|
| 323 |
|
|
: "=r" (grt) \
|
| 324 |
|
|
: "i" (sr), \
|
| 325 |
|
|
"r" (groff), \
|
| 326 |
|
|
"i" (iacc))
|
| 327 |
|
|
|
| 328 |
|
|
/* Probe Write Access PROBEW (s,b),r,t */
|
| 329 |
|
|
#define HPPA_ASM_PROBEW(sr,groff,gracc,grt) \
|
| 330 |
|
|
asm volatile ("probew (%1,%2),%3,%0" \
|
| 331 |
|
|
: "=r" (grt) \
|
| 332 |
|
|
: "i" (sr), \
|
| 333 |
|
|
"r" (groff), \
|
| 334 |
|
|
"r" (gracc))
|
| 335 |
|
|
|
| 336 |
|
|
/* Probe Write Access Immediate PROBEWI (s,b),i,t */
|
| 337 |
|
|
#define HPPA_ASM_PROBEWI(sr,groff,iacc,grt) \
|
| 338 |
|
|
asm volatile ("probewi (%1,%2),%3,%0" \
|
| 339 |
|
|
: "=r" (grt) \
|
| 340 |
|
|
: "i" (sr), \
|
| 341 |
|
|
"r" (groff), \
|
| 342 |
|
|
"i" (iacc))
|
| 343 |
|
|
|
| 344 |
|
|
/* Load Physical Address LPA x(s,b),t */
|
| 345 |
|
|
#define HPPA_ASM_LPA(sr,grb,grt) asm volatile ("lpa %%r0(%1,%2),%0" \
|
| 346 |
|
|
: "=r" (grt) \
|
| 347 |
|
|
: "i" (sr), \
|
| 348 |
|
|
"r" (grb))
|
| 349 |
|
|
|
| 350 |
|
|
/* Load Coherence Index LCI x(s,b),t */
|
| 351 |
|
|
/* AKA: Load Hash Address LHA x(s,b),t */
|
| 352 |
|
|
#define HPPA_ASM_LCI(grx,sr,grb,grt) asm volatile ("lha %1(%2,%3),%0" \
|
| 353 |
|
|
: "=r" (grt) \
|
| 354 |
|
|
: "r" (grx),\
|
| 355 |
|
|
"i" (sr), \
|
| 356 |
|
|
"r" (grb))
|
| 357 |
|
|
#define HPPA_ASM_LHA(grx,sr,grb,grt) HPPA_ASM_LCI(grx,sr,grb,grt)
|
| 358 |
|
|
|
| 359 |
|
|
/* Purge Data Tlb PDTLB x(s,b) */
|
| 360 |
|
|
#define HPPA_ASM_PDTLB(grx,sr,grb) asm volatile ("pdtlb %0(%1,%2)" \
|
| 361 |
|
|
: : "r" (grx), \
|
| 362 |
|
|
"i" (sr), \
|
| 363 |
|
|
"r" (grb))
|
| 364 |
|
|
|
| 365 |
|
|
/* Purge Instruction Tlb PITLB x(s,b) */
|
| 366 |
|
|
#define HPPA_ASM_PITLB(grx,sr,grb) asm volatile ("pitlb %0(%1,%2)" \
|
| 367 |
|
|
: : "r" (grx), \
|
| 368 |
|
|
"i" (sr), \
|
| 369 |
|
|
"r" (grb))
|
| 370 |
|
|
|
| 371 |
|
|
/* Purge Data Tlb Entry PDTLBE x(s,b) */
|
| 372 |
|
|
#define HPPA_ASM_PDTLBE(grx,sr,grb) asm volatile ("pdtlbe %0(%1,%2)" \
|
| 373 |
|
|
: : "r" (grx), \
|
| 374 |
|
|
"i" (sr), \
|
| 375 |
|
|
"r" (grb))
|
| 376 |
|
|
|
| 377 |
|
|
/* Purge Instruction Tlb Entry PITLBE x(s,b) */
|
| 378 |
|
|
#define HPPA_ASM_PITLBE(grx,sr,grb) asm volatile ("pitlbe %0(%1,%2)" \
|
| 379 |
|
|
: : "r" (grx), \
|
| 380 |
|
|
"i" (sr), \
|
| 381 |
|
|
"r" (grb))
|
| 382 |
|
|
|
| 383 |
|
|
|
| 384 |
|
|
/* Insert Data TLB Address IDTLBA r,(s,b) */
|
| 385 |
|
|
#define HPPA_ASM_IDTLBA(gr,sr,grb) asm volatile ("idtlba %0,(%1,%2)" \
|
| 386 |
|
|
: : "r" (gr), \
|
| 387 |
|
|
"i" (sr), \
|
| 388 |
|
|
"r" (grb))
|
| 389 |
|
|
|
| 390 |
|
|
/* Insert Instruction TLB Address IITLBA r,(s,b) */
|
| 391 |
|
|
#define HPPA_ASM_IITLBA(gr,sr,grb) asm volatile ("iitlba %0,(%1,%2)" \
|
| 392 |
|
|
: : "r" (gr), \
|
| 393 |
|
|
"i" (sr), \
|
| 394 |
|
|
"r" (grb))
|
| 395 |
|
|
|
| 396 |
|
|
/* Insert Data TLB Protection IDTLBP r,(s,b) */
|
| 397 |
|
|
#define HPPA_ASM_IDTLBP(gr,sr,grb) asm volatile ("idtlbp %0,(%1,%2)" \
|
| 398 |
|
|
: : "r" (gr), \
|
| 399 |
|
|
"i" (sr), \
|
| 400 |
|
|
"r" (grb))
|
| 401 |
|
|
|
| 402 |
|
|
/* Insert Instruction TLB Protection IITLBP r,(s,b) */
|
| 403 |
|
|
#define HPPA_ASM_IITLBP(gr,sr,grb) asm volatile ("iitlbp %0,(%1,%2)" \
|
| 404 |
|
|
: : "r" (gr), \
|
| 405 |
|
|
"i" (sr), \
|
| 406 |
|
|
"r" (grb))
|
| 407 |
|
|
|
| 408 |
|
|
/* Purge Data Cache PDC x(s,b) */
|
| 409 |
|
|
#define HPPA_ASM_PDC(grx,sr,grb) asm volatile ("pdc %0(%1,%2)" \
|
| 410 |
|
|
: : "r" (grx), \
|
| 411 |
|
|
"i" (sr), \
|
| 412 |
|
|
"r" (grb))
|
| 413 |
|
|
|
| 414 |
|
|
/* Flush Data Cache FDC x(s,b) */
|
| 415 |
|
|
#define HPPA_ASM_FDC(grx,sr,grb) asm volatile ("fdc %0(%1,%2)" \
|
| 416 |
|
|
: : "r" (grx), \
|
| 417 |
|
|
"i" (sr), \
|
| 418 |
|
|
"r" (grb))
|
| 419 |
|
|
|
| 420 |
|
|
/* Flush Instruction Cache FDC x(s,b) */
|
| 421 |
|
|
#define HPPA_ASM_FIC(grx,sr,grb) asm volatile ("fic %0(%1,%2)" \
|
| 422 |
|
|
: : "r" (grx), \
|
| 423 |
|
|
"i" (sr), \
|
| 424 |
|
|
"r" (grb))
|
| 425 |
|
|
|
| 426 |
|
|
/* Flush Data Cache Entry FDCE x(s,b) */
|
| 427 |
|
|
#define HPPA_ASM_FDCE(grx,sr,grb) asm volatile ("fdce %0(%1,%2)" \
|
| 428 |
|
|
: : "r" (grx), \
|
| 429 |
|
|
"i" (sr), \
|
| 430 |
|
|
"r" (grb))
|
| 431 |
|
|
|
| 432 |
|
|
/* Flush Instruction Cache Entry FICE x(s,b) */
|
| 433 |
|
|
#define HPPA_ASM_FICE(grx,sr,grb) asm volatile ("fice %0(%1,%2)" \
|
| 434 |
|
|
: : "r" (grx), \
|
| 435 |
|
|
"i" (sr), \
|
| 436 |
|
|
"r" (grb))
|
| 437 |
|
|
|
| 438 |
|
|
/* Break BREAK i5,i13 */
|
| 439 |
|
|
#define HPPA_ASM_BREAK(i5,i13) asm volatile ("break %0,%1" \
|
| 440 |
|
|
: : "i" (i5), \
|
| 441 |
|
|
"i" (i13))
|
| 442 |
|
|
|
| 443 |
|
|
/* Load and Clear Word Short LDCWS d(s,b),t */
|
| 444 |
|
|
#define HPPA_ASM_LDCWS(i,sr,grb,grt) asm volatile ("ldcws %1(%2,%3),%0" \
|
| 445 |
|
|
: "=r" (grt) \
|
| 446 |
|
|
: "i" (i), \
|
| 447 |
|
|
"i" (sr), \
|
| 448 |
|
|
"r" (grb))
|
| 449 |
|
|
|
| 450 |
|
|
/* Load and Clear Word Indexed LDCWX x(s,b),t */
|
| 451 |
|
|
#define HPPA_ASM_LDCWX(grx,sr,grb,grt) asm volatile ("ldcwx %1(%2,%3),%0" \
|
| 452 |
|
|
: "=r" (grt) \
|
| 453 |
|
|
: "r" (grx), \
|
| 454 |
|
|
"i" (sr), \
|
| 455 |
|
|
"r" (grb))
|
| 456 |
|
|
|
| 457 |
|
|
/* Load Word Absolute Short LDWAS d(b),t */
|
| 458 |
|
|
/* NOTE: "short" here means "short displacement" */
|
| 459 |
|
|
#define HPPA_ASM_LDWAS(disp,grbase,gr) asm volatile("ldwas %1(%2),%0" \
|
| 460 |
|
|
: "=r" (gr) \
|
| 461 |
|
|
: "i" (disp), \
|
| 462 |
|
|
"r" (grbase))
|
| 463 |
|
|
|
| 464 |
|
|
/* Store Word Absolute Short STWAS r,d(b) */
|
| 465 |
|
|
/* NOTE: "short" here means "short displacement" */
|
| 466 |
|
|
#define HPPA_ASM_STWAS(gr,disp,grbase) asm volatile("stwas %0,%1(%2)" \
|
| 467 |
|
|
: : "r" (gr), \
|
| 468 |
|
|
"i" (disp), \
|
| 469 |
|
|
"r" (grbase))
|
| 470 |
|
|
|
| 471 |
|
|
/*
|
| 472 |
|
|
* Swap bytes
|
| 473 |
|
|
* REFERENCE: PA72000 TRM -- Appendix C
|
| 474 |
|
|
*/
|
| 475 |
|
|
#define HPPA_ASM_SWAPBYTES(value, swapped) asm volatile( \
|
| 476 |
|
|
" shd %1,%1,16,%0 \n\
|
| 477 |
|
|
dep %0,15,8,%0 \n\
|
| 478 |
|
|
shd %1,%0,8,%0" \
|
| 479 |
|
|
: "=r" (swapped) \
|
| 480 |
|
|
: "r" (value) \
|
| 481 |
|
|
)
|
| 482 |
|
|
|
| 483 |
|
|
|
| 484 |
|
|
/* 72000 Diagnose instructions follow
|
| 485 |
|
|
* These macros assume gas knows about these instructions.
|
| 486 |
|
|
* gas2.2.u1 did not.
|
| 487 |
|
|
* I added them to my copy and installed it locally.
|
| 488 |
|
|
*
|
| 489 |
|
|
* There are *very* special requirements for these guys
|
| 490 |
|
|
* ref: TRM 6.1.3 Programming Constraints
|
| 491 |
|
|
*
|
| 492 |
|
|
* The macros below handle the following rules
|
| 493 |
|
|
*
|
| 494 |
|
|
* Except for WIT, WDT, WDD, WIDO, WIDE, all DIAGNOSE must be doubled.
|
| 495 |
|
|
* Must never be nullified (hence the leading nop)
|
| 496 |
|
|
* NOP must preced every RDD,RDT,WDD,WDT,RDTLB
|
| 497 |
|
|
* Instruction preceeding GR_SHDW must not set any of the GR's saved
|
| 498 |
|
|
*
|
| 499 |
|
|
* The macros do *NOT* deal with the following problems
|
| 500 |
|
|
* doubled DIAGNOSE instructions must not straddle a page boundary
|
| 501 |
|
|
* if code translation enabled. (since 2nd could trap on ITLB)
|
| 502 |
|
|
* If you care about DHIT and DPE bits of DR0, then
|
| 503 |
|
|
* No store instruction in the 2 insn window before RDD
|
| 504 |
|
|
*/
|
| 505 |
|
|
|
| 506 |
|
|
|
| 507 |
|
|
/* Move To CPU/DIAG register MTCPU r,t */
|
| 508 |
|
|
#define HPPA_ASM_MTCPU(gr,dr) asm volatile (" nop \n" \
|
| 509 |
|
|
" mtcpu %1,%0 \n" \
|
| 510 |
|
|
" mtcpu %1,%0" \
|
| 511 |
|
|
: : "i" (dr), \
|
| 512 |
|
|
"r" (gr))
|
| 513 |
|
|
|
| 514 |
|
|
/* Move From CPU/DIAG register MFCPU r,t */
|
| 515 |
|
|
#define HPPA_ASM_MFCPU(dr,gr) asm volatile (" nop \n" \
|
| 516 |
|
|
" mfcpu %1,%0\n" \
|
| 517 |
|
|
" mfcpu %1,%0" \
|
| 518 |
|
|
: "=r" (gr) \
|
| 519 |
|
|
: "i" (dr))
|
| 520 |
|
|
|
| 521 |
|
|
/* Transfer of Control Enable TOC_EN */
|
| 522 |
|
|
#define HPPA_ASM_TOC_EN() asm volatile (" tocen \n" \
|
| 523 |
|
|
" tocen")
|
| 524 |
|
|
|
| 525 |
|
|
/* Transfer of Control Disable TOC_DIS */
|
| 526 |
|
|
#define HPPA_ASM_TOC_DIS() asm volatile (" tocdis \n" \
|
| 527 |
|
|
" tocdis")
|
| 528 |
|
|
|
| 529 |
|
|
/* Shadow Registers to General Register SHDW_GR */
|
| 530 |
|
|
#define HPPA_ASM_SHDW_GR() asm volatile (" shdwgr \n" \
|
| 531 |
|
|
" shdwgr" \
|
| 532 |
|
|
::: "r1" "r8" "r9" "r16" \
|
| 533 |
|
|
"r17" "r24" "r25")
|
| 534 |
|
|
|
| 535 |
|
|
/* General Registers to Shadow Register GR_SHDW */
|
| 536 |
|
|
#define HPPA_ASM_GR_SHDW() asm volatile (" nop \n" \
|
| 537 |
|
|
" grshdw \n" \
|
| 538 |
|
|
" grshdw")
|
| 539 |
|
|
|
| 540 |
|
|
/*
|
| 541 |
|
|
* Definitions of special registers for use by the above macros.
|
| 542 |
|
|
*/
|
| 543 |
|
|
|
| 544 |
|
|
/* Hardware Space Registers */
|
| 545 |
|
|
#define HPPA_SR0 0
|
| 546 |
|
|
#define HPPA_SR1 1
|
| 547 |
|
|
#define HPPA_SR2 2
|
| 548 |
|
|
#define HPPA_SR3 3
|
| 549 |
|
|
#define HPPA_SR4 4
|
| 550 |
|
|
#define HPPA_SR5 5
|
| 551 |
|
|
#define HPPA_SR6 6
|
| 552 |
|
|
#define HPPA_SR7 7
|
| 553 |
|
|
|
| 554 |
|
|
/* Hardware Control Registers */
|
| 555 |
|
|
#define HPPA_CR0 0
|
| 556 |
|
|
#define HPPA_RCTR 0 /* Recovery Counter Register */
|
| 557 |
|
|
|
| 558 |
|
|
#define HPPA_CR8 8 /* Protection ID 1 */
|
| 559 |
|
|
#define HPPA_PIDR1 8
|
| 560 |
|
|
|
| 561 |
|
|
#define HPPA_CR9 9 /* Protection ID 2 */
|
| 562 |
|
|
#define HPPA_PIDR2 9
|
| 563 |
|
|
|
| 564 |
|
|
#define HPPA_CR10 10
|
| 565 |
|
|
#define HPPA_CCR 10 /* Coprocessor Confiquration Register */
|
| 566 |
|
|
|
| 567 |
|
|
#define HPPA_CR11 11
|
| 568 |
|
|
#define HPPA_SAR 11 /* Shift Amount Register */
|
| 569 |
|
|
|
| 570 |
|
|
#define HPPA_CR12 12
|
| 571 |
|
|
#define HPPA_PIDR3 12 /* Protection ID 3 */
|
| 572 |
|
|
|
| 573 |
|
|
#define HPPA_CR13 13
|
| 574 |
|
|
#define HPPA_PIDR4 13 /* Protection ID 4 */
|
| 575 |
|
|
|
| 576 |
|
|
#define HPPA_CR14 14
|
| 577 |
|
|
#define HPPA_IVA 14 /* Interrupt Vector Address */
|
| 578 |
|
|
|
| 579 |
|
|
#define HPPA_CR15 15
|
| 580 |
|
|
#define HPPA_EIEM 15 /* External Interrupt Enable Mask */
|
| 581 |
|
|
|
| 582 |
|
|
#define HPPA_CR16 16
|
| 583 |
|
|
#define HPPA_ITMR 16 /* Interval Timer */
|
| 584 |
|
|
|
| 585 |
|
|
#define HPPA_CR17 17
|
| 586 |
|
|
#define HPPA_PCSQ 17 /* Program Counter Space queue */
|
| 587 |
|
|
|
| 588 |
|
|
#define HPPA_CR18 18
|
| 589 |
|
|
#define HPPA_PCOQ 18 /* Program Counter Offset queue */
|
| 590 |
|
|
|
| 591 |
|
|
#define HPPA_CR19 19
|
| 592 |
|
|
#define HPPA_IIR 19 /* Interruption Instruction Register */
|
| 593 |
|
|
|
| 594 |
|
|
#define HPPA_CR20 20
|
| 595 |
|
|
#define HPPA_ISR 20 /* Interruption Space Register */
|
| 596 |
|
|
|
| 597 |
|
|
#define HPPA_CR21 21
|
| 598 |
|
|
#define HPPA_IOR 21 /* Interruption Offset Register */
|
| 599 |
|
|
|
| 600 |
|
|
#define HPPA_CR22 22
|
| 601 |
|
|
#define HPPA_IPSW 22 /* Interrpution Processor Status Word */
|
| 602 |
|
|
|
| 603 |
|
|
#define HPPA_CR23 23
|
| 604 |
|
|
#define HPPA_EIRR 23 /* External Interrupt Request */
|
| 605 |
|
|
|
| 606 |
|
|
#define HPPA_CR24 24
|
| 607 |
|
|
#define HPPA_PPDA 24 /* Physcial Page Directory Address */
|
| 608 |
|
|
#define HPPA_TR0 24 /* Temporary register 0 */
|
| 609 |
|
|
|
| 610 |
|
|
#define HPPA_CR25 25
|
| 611 |
|
|
#define HPPA_HTA 25 /* Hash Table Address */
|
| 612 |
|
|
#define HPPA_TR1 25 /* Temporary register 1 */
|
| 613 |
|
|
|
| 614 |
|
|
#define HPPA_CR26 26
|
| 615 |
|
|
#define HPPA_TR2 26 /* Temporary register 2 */
|
| 616 |
|
|
|
| 617 |
|
|
#define HPPA_CR27 27
|
| 618 |
|
|
#define HPPA_TR3 27 /* Temporary register 3 */
|
| 619 |
|
|
|
| 620 |
|
|
#define HPPA_CR28 28
|
| 621 |
|
|
#define HPPA_TR4 28 /* Temporary register 4 */
|
| 622 |
|
|
|
| 623 |
|
|
#define HPPA_CR29 29
|
| 624 |
|
|
#define HPPA_TR5 29 /* Temporary register 5 */
|
| 625 |
|
|
|
| 626 |
|
|
#define HPPA_CR30 30
|
| 627 |
|
|
#define HPPA_TR6 30 /* Temporary register 6 */
|
| 628 |
|
|
|
| 629 |
|
|
#define HPPA_CR31 31
|
| 630 |
|
|
#define HPPA_CPUID 31 /* MP identifier */
|
| 631 |
|
|
|
| 632 |
|
|
/*
|
| 633 |
|
|
* Diagnose registers
|
| 634 |
|
|
*/
|
| 635 |
|
|
|
| 636 |
|
|
#define HPPA_DR0 0
|
| 637 |
|
|
#define HPPA_DR1 1
|
| 638 |
|
|
#define HPPA_DR8 8
|
| 639 |
|
|
#define HPPA_DR24 24
|
| 640 |
|
|
#define HPPA_DR25 25
|
| 641 |
|
|
|
| 642 |
|
|
/*
|
| 643 |
|
|
* Tear apart a break instruction to find its type.
|
| 644 |
|
|
*/
|
| 645 |
|
|
#define HPPA_BREAK5(x) ((x) & 0x1F)
|
| 646 |
|
|
#define HPPA_BREAK13(x) (((x) >> 13) & 0x1FFF)
|
| 647 |
|
|
|
| 648 |
|
|
/* assemble a break instruction */
|
| 649 |
|
|
#define HPPA_BREAK(i5,i13) (((i5) & 0x1F) | (((i13) & 0x1FFF) << 13))
|
| 650 |
|
|
|
| 651 |
|
|
|
| 652 |
|
|
/*
|
| 653 |
|
|
* this won't work in ASM or non-GNU compilers
|
| 654 |
|
|
*/
|
| 655 |
|
|
|
| 656 |
|
|
#if !defined(ASM) && defined(__GNUC__)
|
| 657 |
|
|
|
| 658 |
|
|
/*
|
| 659 |
|
|
* static inline utility functions to get at control registers
|
| 660 |
|
|
*/
|
| 661 |
|
|
|
| 662 |
|
|
#define EMIT_GET_CONTROL(name, reg) \
|
| 663 |
|
|
static __inline__ unsigned int \
|
| 664 |
|
|
get_ ## name (void) \
|
| 665 |
|
|
{ \
|
| 666 |
|
|
unsigned int value; \
|
| 667 |
|
|
HPPA_ASM_MFCTL(reg, value); \
|
| 668 |
|
|
return value; \
|
| 669 |
|
|
}
|
| 670 |
|
|
|
| 671 |
|
|
#define EMIT_SET_CONTROL(name, reg) \
|
| 672 |
|
|
static __inline__ void \
|
| 673 |
|
|
set_ ## name (unsigned int new_value) \
|
| 674 |
|
|
{ \
|
| 675 |
|
|
HPPA_ASM_MTCTL(new_value, reg); \
|
| 676 |
|
|
}
|
| 677 |
|
|
|
| 678 |
|
|
#define EMIT_CONTROLS(name, reg) \
|
| 679 |
|
|
EMIT_GET_CONTROL(name, reg) \
|
| 680 |
|
|
EMIT_SET_CONTROL(name, reg)
|
| 681 |
|
|
|
| 682 |
|
|
EMIT_CONTROLS(recovery, HPPA_RCTR); /* CR0 */
|
| 683 |
|
|
EMIT_CONTROLS(pid1, HPPA_PIDR1); /* CR8 */
|
| 684 |
|
|
EMIT_CONTROLS(pid2, HPPA_PIDR2); /* CR9 */
|
| 685 |
|
|
EMIT_CONTROLS(ccr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
|
| 686 |
|
|
EMIT_CONTROLS(scr, HPPA_CCR); /* CR10; CCR and SCR share CR10 */
|
| 687 |
|
|
EMIT_CONTROLS(sar, HPPA_SAR); /* CR11 */
|
| 688 |
|
|
EMIT_CONTROLS(pid3, HPPA_PIDR3); /* CR12 */
|
| 689 |
|
|
EMIT_CONTROLS(pid4, HPPA_PIDR4); /* CR13 */
|
| 690 |
|
|
EMIT_CONTROLS(iva, HPPA_IVA); /* CR14 */
|
| 691 |
|
|
EMIT_CONTROLS(eiem, HPPA_EIEM); /* CR15 */
|
| 692 |
|
|
EMIT_CONTROLS(itimer, HPPA_ITMR); /* CR16 */
|
| 693 |
|
|
EMIT_CONTROLS(pcsq, HPPA_PCSQ); /* CR17 */
|
| 694 |
|
|
EMIT_CONTROLS(pcoq, HPPA_PCOQ); /* CR18 */
|
| 695 |
|
|
EMIT_CONTROLS(iir, HPPA_IIR); /* CR19 */
|
| 696 |
|
|
EMIT_CONTROLS(isr, HPPA_ISR); /* CR20 */
|
| 697 |
|
|
EMIT_CONTROLS(ior, HPPA_IOR); /* CR21 */
|
| 698 |
|
|
EMIT_CONTROLS(ipsw, HPPA_IPSW); /* CR22 */
|
| 699 |
|
|
EMIT_CONTROLS(eirr, HPPA_EIRR); /* CR23 */
|
| 700 |
|
|
EMIT_CONTROLS(tr0, HPPA_TR0); /* CR24 */
|
| 701 |
|
|
EMIT_CONTROLS(tr1, HPPA_TR1); /* CR25 */
|
| 702 |
|
|
EMIT_CONTROLS(tr2, HPPA_TR2); /* CR26 */
|
| 703 |
|
|
EMIT_CONTROLS(tr3, HPPA_TR3); /* CR27 */
|
| 704 |
|
|
EMIT_CONTROLS(tr4, HPPA_TR4); /* CR28 */
|
| 705 |
|
|
EMIT_CONTROLS(tr5, HPPA_TR5); /* CR29 */
|
| 706 |
|
|
EMIT_CONTROLS(tr6, HPPA_TR6); /* CR30 */
|
| 707 |
|
|
EMIT_CONTROLS(tr7, HPPA_CR31); /* CR31 */
|
| 708 |
|
|
|
| 709 |
|
|
#endif /* ASM and GNU */
|
| 710 |
|
|
|
| 711 |
|
|
/*
|
| 712 |
|
|
* If and How to invoke the debugger (a ROM debugger generally)
|
| 713 |
|
|
*/
|
| 714 |
|
|
#define CPU_INVOKE_DEBUGGER \
|
| 715 |
|
|
do { \
|
| 716 |
|
|
HPPA_ASM_BREAK(1,1); \
|
| 717 |
|
|
} while (0)
|
| 718 |
|
|
|
| 719 |
|
|
#ifdef __cplusplus
|
| 720 |
|
|
}
|
| 721 |
|
|
#endif
|
| 722 |
|
|
|
| 723 |
|
|
#endif /* ! _INCLUDE_HPPA_H */
|
| 724 |
|
|
|
