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/*  cpu.h
 *
 *  This include file contains information pertaining to the Intel
 *  i960 processor family.
 *
 *  COPYRIGHT (c) 1989-1999.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.OARcorp.com/rtems/license.html.
 *
 *  $Id: cpu.h,v 1.2 2001-09-27 11:59:28 chris Exp $
 */
 
#ifndef __CPU_h
#define __CPU_h
 
#ifdef __cplusplus
extern "C" {
#endif
 
#if 0
#pragma align 4            /* for GNU C structure alignment */
#endif
 
#include <rtems/score/i960.h>              /* pick up machine definitions */
#ifndef ASM
#include <rtems/score/i960types.h>
#endif
 
#define CPU_INLINE_ENABLE_DISPATCH       FALSE
#define CPU_UNROLL_ENQUEUE_PRIORITY      FALSE
 
/*
 *  Use the i960's hardware interrupt stack support and have the
 *  interrupt manager allocate the memory for it.
 */
 
#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
#define CPU_ALLOCATE_INTERRUPT_STACK     TRUE
 
/*
 *  Does the RTEMS invoke the user's ISR with the vector number and
 *  a pointer to the saved interrupt frame (1) or just the vector
 *  number (0)?
 */
 
#define CPU_ISR_PASSES_FRAME_POINTER 0
 
/*
 *  Some family members have no FP (SA/KA/CA/CF), others have it built in
 *  (KB/MC/MX).  There does not appear to be an external coprocessor
 *  for this family.
 */
 
#if ( I960_HAS_FPU == 1 )
#define CPU_HARDWARE_FP     TRUE
#error "Floating point support for i960 family has been implemented!!!"
#else
#define CPU_HARDWARE_FP     FALSE
#endif
 
#define CPU_ALL_TASKS_ARE_FP             FALSE
#define CPU_IDLE_TASK_IS_FP              FALSE
#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
 
#define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
#define CPU_STACK_GROWS_UP               TRUE
#define CPU_STRUCTURE_ALIGNMENT          /* __attribute__ ((aligned (16))) */
 
/*
 *  Define what is required to specify how the network to host conversion
 *  routines are handled.
 */
 
#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES     FALSE
#define CPU_BIG_ENDIAN                           TRUE
#define CPU_LITTLE_ENDIAN                        FALSE
 
 
/* structures */
 
/*
 *  Basic integer context for the i960 family.
 */
 
typedef struct {
  void       *r0_pfp;                 /* (r0)  Previous Frame Pointer */
  void       *r1_sp;                  /* (r1)  Stack Pointer */
  unsigned32  pc;                     /* (pc)  Processor Control */
  void       *g8;                     /* (g8)  Global Register 8 */
  void       *g9;                     /* (g9)  Global Register 9 */
  void       *g10;                    /* (g10) Global Register 10 */
  void       *g11;                    /* (g11) Global Register 11 */
  void       *g12;                    /* (g12) Global Register 12 */
  void       *g13;                    /* (g13) Global Register 13 */
  unsigned32  g14;                    /* (g14) Global Register 14 */
  void       *g15_fp;                 /* (g15) Frame Pointer */
}   Context_Control;
 
/*
 *  FP context save area for the i960 Numeric Extension
 */
 
typedef struct {
   unsigned32  fp0_1;                 /* (fp0) first word  */
   unsigned32  fp0_2;                 /* (fp0) second word */
   unsigned32  fp0_3;                 /* (fp0) third word  */
   unsigned32  fp1_1;                 /* (fp1) first word  */
   unsigned32  fp1_2;                 /* (fp1) second word */
   unsigned32  fp1_3;                 /* (fp1) third word  */
   unsigned32  fp2_1;                 /* (fp2) first word  */
   unsigned32  fp2_2;                 /* (fp2) second word */
   unsigned32  fp2_3;                 /* (fp2) third word  */
   unsigned32  fp3_1;                 /* (fp3) first word  */
   unsigned32  fp3_2;                 /* (fp3) second word */
   unsigned32  fp3_3;                 /* (fp3) third word  */
} Context_Control_fp;
 
/*
 *  The following structure defines the set of information saved
 *  on the current stack by RTEMS upon receipt of each interrupt.
 */
 
typedef struct {
  unsigned32   TBD;   /* XXX Fix for this CPU */
} CPU_Interrupt_frame;
 
/*
 *  Call frame for the i960 family.
 */
 
typedef struct {
  void       *r0_pfp;                 /* (r0)  Previous Frame Pointer */
  void       *r1_sp;                  /* (r1)  Stack Pointer */
  void       *r2_rip;                 /* (r2)  Return Instruction Pointer */
  void       *r3;                     /* (r3)  Local Register 3 */
  void       *r4;                     /* (r4)  Local Register 4 */
  void       *r5;                     /* (r5)  Local Register 5 */
  void       *r6;                     /* (r6)  Local Register 6 */
  void       *r7;                     /* (r7)  Local Register 7 */
  void       *r8;                     /* (r8)  Local Register 8 */
  void       *r9;                     /* (r9)  Local Register 9 */
  void       *r10;                    /* (r10) Local Register 10 */
  void       *r11;                    /* (r11) Local Register 11 */
  void       *r12;                    /* (r12) Local Register 12 */
  void       *r13;                    /* (r13) Local Register 13 */
  void       *r14;                    /* (r14) Local Register 14 */
  void       *r15;                    /* (r15) Local Register 15 */
  /* XXX Looks like sometimes there is FP stuff here (MC manual)? */
}   CPU_Call_frame;
 
/*
 *  The following table contains the information required to configure
 *  the i960 specific parameters.
 */
 
typedef struct {
  void       (*pretasking_hook)( void );
  void       (*predriver_hook)( void );
  void       (*postdriver_hook)( void );
  void       (*idle_task)( void );
  boolean      do_zero_of_workspace;
  unsigned32   idle_task_stack_size;
  unsigned32   interrupt_stack_size;
  unsigned32   extra_mpci_receive_server_stack;
  void *     (*stack_allocate_hook)( unsigned32 );
  void       (*stack_free_hook)( void* );
  /* end of fields required on all CPUs */
 
  i960_PRCB *Prcb;
}   rtems_cpu_table;
 
/*
 *  Macros to access required entires in the CPU Table are in
 *  the file rtems/system.h.
 */
 
/*
 *  Macros to access i960 specific additions to the CPU Table
 */
 
#define rtems_cpu_configuration_get_prcb() \
   (_CPU_Table.Prcb)
 
/* variables */
 
SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
 
/* constants */
 
/*
 *  This defines the number of levels and the mask used to pick those
 *  bits out of a thread mode.
 */
 
#define CPU_MODES_INTERRUPT_LEVEL  0x0000001f  /* interrupt level in mode */
#define CPU_MODES_INTERRUPT_MASK   0x0000001f  /* interrupt level in mode */
 
/*
 *  context size area for floating point
 */
 
#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
 
/*
 *  extra stack required by the MPCI receive server thread
 */
 
#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK (CPU_STACK_MINIMUM_SIZE)
 
/*
 *  i960 family supports 256 distinct vectors.
 */
 
#define CPU_INTERRUPT_NUMBER_OF_VECTORS      256
#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
 
/*
 *  Minimum size of a thread's stack.
 *
 *  NOTE:  See CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK
 */
 
#define CPU_STACK_MINIMUM_SIZE          2048
 
/*
 *  i960 is pretty tolerant of alignment but some CPU models do
 *  better with different default aligments so we use what the
 *  CPU model selected in rtems/score/i960.h.
 */
 
#define CPU_ALIGNMENT                   I960_CPU_ALIGNMENT
#define CPU_HEAP_ALIGNMENT              CPU_ALIGNMENT
#define CPU_PARTITION_ALIGNMENT         CPU_ALIGNMENT
 
/*
 * i960ca stack requires 16 byte alignment
 *
 *  NOTE:  This factor may need to be family member dependent.
 */
 
#define CPU_STACK_ALIGNMENT        16
 
/* macros */
 
/*
 *  ISR handler macros
 *
 *  These macros perform the following functions:
 *     + disable all maskable CPU interrupts
 *     + restore previous interrupt level (enable)
 *     + temporarily restore interrupts (flash)
 *     + set a particular level
 */
 
#define _CPU_ISR_Disable( _level ) i960_disable_interrupts( _level )
#define _CPU_ISR_Enable( _level )  i960_enable_interrupts( _level )
#define _CPU_ISR_Flash( _level )   i960_flash_interrupts( _level )
 
#define _CPU_ISR_Set_level( newlevel ) \
  { \
    unsigned32 _mask = 0; \
    unsigned32 _level = (newlevel); \
    \
    __asm__ volatile ( "ldconst 0x1f0000,%0; \
                    modpc   0,%0,%1"     : "=d" (_mask), "=d" (_level) \
                                         : "0"  (_mask), "1" (_level) \
    ); \
  }
 
unsigned32 _CPU_ISR_Get_level( void );
 
/* ISR handler section macros */
 
/*
 *  Context handler macros
 *
 *  These macros perform the following functions:
 *     + initialize a context area
 *     + restart the current thread
 *     + calculate the initial pointer into a FP context area
 *     + initialize an FP context area
 */
 
#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
                                  _isr, _entry, _is_fp ) \
 { CPU_Call_frame *_texit_frame; \
   unsigned32 _mask; \
   unsigned32 _base_pc; \
   unsigned32  _stack_tmp; \
   void       *_stack; \
   \
  _stack_tmp = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT; \
  _stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \
  _stack = (void *) _stack_tmp; \
   \
   __asm__ volatile ( "flushreg" : : );   /* flush register cache */ \
   \
   (_the_context)->r0_pfp = _stack; \
   (_the_context)->g15_fp = _stack + (1 * sizeof(CPU_Call_frame)); \
   (_the_context)->r1_sp  = _stack + (2 * sizeof(CPU_Call_frame)); \
   __asm__ volatile ( "ldconst 0x1f0000,%0 ; " \
                  "modpc   0,0,%1 ; " \
                  "andnot  %0,%1,%1 ; " \
                  : "=d" (_mask), "=d" (_base_pc) : ); \
   (_the_context)->pc     = _base_pc | ((_isr) << 16); \
   (_the_context)->g14    = 0; \
   \
   _texit_frame         = (CPU_Call_frame *)_stack; \
   _texit_frame->r0_pfp = NULL; \
   _texit_frame->r1_sp  = (_the_context)->g15_fp; \
   _texit_frame->r2_rip = (_entry); \
 }
 
#define _CPU_Context_Restart_self( _the_context ) \
   _CPU_Context_restore( (_the_context) );
 
#define _CPU_Context_Fp_start( _base, _offset )         NULL
 
#define _CPU_Context_Initialize_fp( _fp_area )
 
/* end of Context handler macros */
 
/*
 *  Fatal Error manager macros
 *
 *  These macros perform the following functions:
 *    + disable interrupts and halt the CPU
 */
 
#define _CPU_Fatal_halt( _errorcode ) \
  { unsigned32 _mask, _level; \
    unsigned32 _error = (_errorcode); \
    \
    __asm__ volatile ( "ldconst 0x1f0000,%0 ; \
                    mov     %0,%1 ; \
                    modpc   0,%0,%1 ; \
                    mov     %2,g0 ; \
            self:   b       self " \
                    : "=d" (_mask), "=d" (_level), "=d" (_error) : ); \
  }
 
/* end of Fatal Error Manager macros */
 
/*
 *  Bitfield handler macros
 *
 *  These macros perform the following functions:
 *     + scan for the highest numbered (MSB) set in a 16 bit bitfield
 */
 
#if defined(i960gdbsim)
 
#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
#else
#define CPU_USE_GENERIC_BITFIELD_CODE FALSE
#define CPU_USE_GENERIC_BITFIELD_DATA FALSE
 
#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
  { unsigned32 _search = (_value); \
    \
    (_output) = 0; /* to prevent warnings */ \
    __asm__ volatile ( "scanbit   %0,%1  " \
                    : "=d" (_search), "=d" (_output) \
                    : "0"  (_search), "1"  (_output) ); \
  }
 
/* end of Bitfield handler macros */
 
/*
 *  Priority handler macros
 *
 *  These macros perform the following functions:
 *    + return a mask with the bit for this major/minor portion of
 *      of thread priority set.
 *    + translate the bit number returned by "Bitfield_find_first_bit"
 *      into an index into the thread ready chain bit maps
 */
 
#define _CPU_Priority_Mask( _bit_number ) \
   ( 0x8000 >> (_bit_number) )
 
#define _CPU_Priority_bits_index( _priority ) \
   ( 15 - (_priority) )
 
/* end of Priority handler macros */
#endif
 
/* functions */
 
/*
 *  _CPU_Initialize
 *
 *  This routine performs CPU dependent initialization.
 */
 
void _CPU_Initialize(
  rtems_cpu_table  *cpu_table,
  void      (*thread_dispatch)
);
 
/*
 *  _CPU_ISR_install_raw_handler
 *
 *  This routine installs a "raw" interrupt handler directly into the
 *  processor's vector table.
 */
 
void _CPU_ISR_install_raw_handler(
  unsigned32  vector,
  proc_ptr    new_handler,
  proc_ptr   *old_handler
);
 
/*
 *  _CPU_ISR_install_vector
 *
 *  This routine installs an interrupt vector.
 */
 
void _CPU_ISR_install_vector(
  unsigned32  vector,
  proc_ptr    new_handler,
  proc_ptr   *old_handler
);
 
/*
 *  _CPU_Install_interrupt_stack
 *
 *  This routine installs the hardware interrupt stack pointer.
 */
 
void _CPU_Install_interrupt_stack( void );
 
/*
 *  _CPU_Context_switch
 *
 *  This routine switches from the run context to the heir context.
 */
 
void _CPU_Context_switch(
  Context_Control  *run,
  Context_Control  *heir
);
 
/*
 *  _CPU_Context_restore
 *
 *  This routine is generally used only to restart self in an
 *  efficient manner and avoid stack conflicts.
 */
 
void _CPU_Context_restore(
  Context_Control *new_context
);
 
/*
 *  _CPU_Context_save_fp
 *
 *  This routine saves the floating point context passed to it.
 */
 
void _CPU_Context_save_fp(
  void        **fp_context_ptr
);
 
/*
 *  _CPU_Context_restore_fp
 *
 *  This routine restores the floating point context passed to it.
 */
 
void _CPU_Context_restore_fp(
  void        **fp_context_ptr
);
 
#ifdef __cplusplus
}
#endif
 
#endif
/* end of include file */

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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [i960/] [rtems/] [score/] [cpu.h] - Blame information for rev 173

Line No.	Rev	Author	Line
1	30	unneback	`/* cpu.h`
2			`*`
3			`* This include file contains information pertaining to the Intel`
4			`* i960 processor family.`
5			`*`
6			`* COPYRIGHT (c) 1989-1999.`
7			`* On-Line Applications Research Corporation (OAR).`
8			`*`
9			`* The license and distribution terms for this file may be`
10			`* found in the file LICENSE in this distribution or at`
11			`* http://www.OARcorp.com/rtems/license.html.`
12			`*`
13			`* $Id: cpu.h,v 1.2 2001-09-27 11:59:28 chris Exp $`
14			`*/`
15
16			`#ifndef __CPU_h`
17			`#define __CPU_h`
18
19			`#ifdef __cplusplus`
20			`extern "C" {`
21			`#endif`
22
23			`#if 0`
24			`#pragma align 4 /* for GNU C structure alignment */`
25			`#endif`
26
27			`#include <rtems/score/i960.h> /* pick up machine definitions */`
28			`#ifndef ASM`
29			`#include <rtems/score/i960types.h>`
30			`#endif`
31
32			`#define CPU_INLINE_ENABLE_DISPATCH FALSE`
33			`#define CPU_UNROLL_ENQUEUE_PRIORITY FALSE`
34
35			`/*`
36			`* Use the i960's hardware interrupt stack support and have the`
37			`* interrupt manager allocate the memory for it.`
38			`*/`
39
40			`#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE`
41			`#define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE`
42			`#define CPU_ALLOCATE_INTERRUPT_STACK TRUE`
43
44			`/*`
45			`* Does the RTEMS invoke the user's ISR with the vector number and`
46			`* a pointer to the saved interrupt frame (1) or just the vector`
47			`* number (0)?`
48			`*/`
49
50			`#define CPU_ISR_PASSES_FRAME_POINTER 0`
51
52			`/*`
53			`* Some family members have no FP (SA/KA/CA/CF), others have it built in`
54			`* (KB/MC/MX). There does not appear to be an external coprocessor`
55			`* for this family.`
56			`*/`
57
58			`#if ( I960_HAS_FPU == 1 )`
59			`#define CPU_HARDWARE_FP TRUE`
60			`#error "Floating point support for i960 family has been implemented!!!"`
61			`#else`
62			`#define CPU_HARDWARE_FP FALSE`
63			`#endif`
64
65			`#define CPU_ALL_TASKS_ARE_FP FALSE`
66			`#define CPU_IDLE_TASK_IS_FP FALSE`
67			`#define CPU_USE_DEFERRED_FP_SWITCH TRUE`
68
69			`#define CPU_PROVIDES_IDLE_THREAD_BODY FALSE`
70			`#define CPU_STACK_GROWS_UP TRUE`
71			`#define CPU_STRUCTURE_ALIGNMENT /* __attribute__ ((aligned (16))) */`
72
73			`/*`
74			`* Define what is required to specify how the network to host conversion`
75			`* routines are handled.`
76			`*/`
77
78			`#define CPU_HAS_OWN_HOST_TO_NETWORK_ROUTINES FALSE`
79			`#define CPU_BIG_ENDIAN TRUE`
80			`#define CPU_LITTLE_ENDIAN FALSE`
81
82
83			`/* structures */`
84
85			`/*`
86			`* Basic integer context for the i960 family.`
87			`*/`
88
89			`typedef struct {`
90			`void r0_pfp; / (r0) Previous Frame Pointer */`
91			`void r1_sp; / (r1) Stack Pointer */`
92			`unsigned32 pc; /* (pc) Processor Control */`
93			`void g8; / (g8) Global Register 8 */`
94			`void g9; / (g9) Global Register 9 */`
95			`void g10; / (g10) Global Register 10 */`
96			`void g11; / (g11) Global Register 11 */`
97			`void g12; / (g12) Global Register 12 */`
98			`void g13; / (g13) Global Register 13 */`
99			`unsigned32 g14; /* (g14) Global Register 14 */`
100			`void g15_fp; / (g15) Frame Pointer */`
101			`} Context_Control;`
102
103			`/*`
104			`* FP context save area for the i960 Numeric Extension`
105			`*/`
106
107			`typedef struct {`
108			`unsigned32 fp0_1; /* (fp0) first word */`
109			`unsigned32 fp0_2; /* (fp0) second word */`
110			`unsigned32 fp0_3; /* (fp0) third word */`
111			`unsigned32 fp1_1; /* (fp1) first word */`
112			`unsigned32 fp1_2; /* (fp1) second word */`
113			`unsigned32 fp1_3; /* (fp1) third word */`
114			`unsigned32 fp2_1; /* (fp2) first word */`
115			`unsigned32 fp2_2; /* (fp2) second word */`
116			`unsigned32 fp2_3; /* (fp2) third word */`
117			`unsigned32 fp3_1; /* (fp3) first word */`
118			`unsigned32 fp3_2; /* (fp3) second word */`
119			`unsigned32 fp3_3; /* (fp3) third word */`
120			`} Context_Control_fp;`
121
122			`/*`
123			`* The following structure defines the set of information saved`
124			`* on the current stack by RTEMS upon receipt of each interrupt.`
125			`*/`
126
127			`typedef struct {`
128			`unsigned32 TBD; /* XXX Fix for this CPU */`
129			`} CPU_Interrupt_frame;`
130
131			`/*`
132			`* Call frame for the i960 family.`
133			`*/`
134
135			`typedef struct {`
136			`void r0_pfp; / (r0) Previous Frame Pointer */`
137			`void r1_sp; / (r1) Stack Pointer */`
138			`void r2_rip; / (r2) Return Instruction Pointer */`
139			`void r3; / (r3) Local Register 3 */`
140			`void r4; / (r4) Local Register 4 */`
141			`void r5; / (r5) Local Register 5 */`
142			`void r6; / (r6) Local Register 6 */`
143			`void r7; / (r7) Local Register 7 */`
144			`void r8; / (r8) Local Register 8 */`
145			`void r9; / (r9) Local Register 9 */`
146			`void r10; / (r10) Local Register 10 */`
147			`void r11; / (r11) Local Register 11 */`
148			`void r12; / (r12) Local Register 12 */`
149			`void r13; / (r13) Local Register 13 */`
150			`void r14; / (r14) Local Register 14 */`
151			`void r15; / (r15) Local Register 15 */`
152			`/* XXX Looks like sometimes there is FP stuff here (MC manual)? */`
153			`} CPU_Call_frame;`
154
155			`/*`
156			`* The following table contains the information required to configure`
157			`* the i960 specific parameters.`
158			`*/`
159
160			`typedef struct {`
161			`void (*pretasking_hook)( void );`
162			`void (*predriver_hook)( void );`
163			`void (*postdriver_hook)( void );`
164			`void (*idle_task)( void );`
165			`boolean do_zero_of_workspace;`
166			`unsigned32 idle_task_stack_size;`
167			`unsigned32 interrupt_stack_size;`
168			`unsigned32 extra_mpci_receive_server_stack;`
169			`void * (*stack_allocate_hook)( unsigned32 );`
170			`void (stack_free_hook)( void );`
171			`/* end of fields required on all CPUs */`
172
173			`i960_PRCB *Prcb;`
174			`} rtems_cpu_table;`
175
176			`/*`
177			`* Macros to access required entires in the CPU Table are in`
178			`* the file rtems/system.h.`
179			`*/`
180
181			`/*`
182			`* Macros to access i960 specific additions to the CPU Table`
183			`*/`
184
185			`#define rtems_cpu_configuration_get_prcb() \`
186			`(_CPU_Table.Prcb)`
187
188			`/* variables */`
189
190			`SCORE_EXTERN void *_CPU_Interrupt_stack_low;`
191			`SCORE_EXTERN void *_CPU_Interrupt_stack_high;`
192
193			`/* constants */`
194
195			`/*`
196			`* This defines the number of levels and the mask used to pick those`
197			`* bits out of a thread mode.`
198			`*/`
199
200			`#define CPU_MODES_INTERRUPT_LEVEL 0x0000001f /* interrupt level in mode */`
201			`#define CPU_MODES_INTERRUPT_MASK 0x0000001f /* interrupt level in mode */`
202
203			`/*`
204			`* context size area for floating point`
205			`*/`
206
207			`#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )`
208
209			`/*`
210			`* extra stack required by the MPCI receive server thread`
211			`*/`
212
213			`#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK (CPU_STACK_MINIMUM_SIZE)`
214
215			`/*`
216			`* i960 family supports 256 distinct vectors.`
217			`*/`
218
219			`#define CPU_INTERRUPT_NUMBER_OF_VECTORS 256`
220			`#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)`
221
222			`/*`
223			`* Minimum size of a thread's stack.`
224			`*`
225			`* NOTE: See CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK`
226			`*/`
227
228			`#define CPU_STACK_MINIMUM_SIZE 2048`
229
230			`/*`
231			`* i960 is pretty tolerant of alignment but some CPU models do`
232			`* better with different default aligments so we use what the`
233			`* CPU model selected in rtems/score/i960.h.`
234			`*/`
235
236			`#define CPU_ALIGNMENT I960_CPU_ALIGNMENT`
237			`#define CPU_HEAP_ALIGNMENT CPU_ALIGNMENT`
238			`#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT`
239
240			`/*`
241			`* i960ca stack requires 16 byte alignment`
242			`*`
243			`* NOTE: This factor may need to be family member dependent.`
244			`*/`
245
246			`#define CPU_STACK_ALIGNMENT 16`
247
248			`/* macros */`
249
250			`/*`
251			`* ISR handler macros`
252			`*`
253			`* These macros perform the following functions:`
254			`* + disable all maskable CPU interrupts`
255			`* + restore previous interrupt level (enable)`
256			`* + temporarily restore interrupts (flash)`
257			`* + set a particular level`
258			`*/`
259
260			`#define _CPU_ISR_Disable( _level ) i960_disable_interrupts( _level )`
261			`#define _CPU_ISR_Enable( _level ) i960_enable_interrupts( _level )`
262			`#define _CPU_ISR_Flash( _level ) i960_flash_interrupts( _level )`
263
264			`#define _CPU_ISR_Set_level( newlevel ) \`
265			`{ \`
266			`unsigned32 _mask = 0; \`
267			`unsigned32 _level = (newlevel); \`
268			`\`
269			`__asm__ volatile ( "ldconst 0x1f0000,%0; \`
270			`modpc 0,%0,%1" : "=d" (_mask), "=d" (_level) \`
271			`: "0" (_mask), "1" (_level) \`
272			`); \`
273			`}`
274
275			`unsigned32 _CPU_ISR_Get_level( void );`
276
277			`/* ISR handler section macros */`
278
279			`/*`
280			`* Context handler macros`
281			`*`
282			`* These macros perform the following functions:`
283			`* + initialize a context area`
284			`* + restart the current thread`
285			`* + calculate the initial pointer into a FP context area`
286			`* + initialize an FP context area`
287			`*/`
288
289			`#define _CPU_Context_Initialize( _the_context, _stack_base, _size, \`
290			`_isr, _entry, _is_fp ) \`
291			`{ CPU_Call_frame *_texit_frame; \`
292			`unsigned32 _mask; \`
293			`unsigned32 _base_pc; \`
294			`unsigned32 _stack_tmp; \`
295			`void *_stack; \`
296			`\`
297			`_stack_tmp = (unsigned32)(_stack_base) + CPU_STACK_ALIGNMENT; \`
298			`_stack_tmp &= ~(CPU_STACK_ALIGNMENT - 1); \`
299			`_stack = (void *) _stack_tmp; \`
300			`\`
301			`__asm__ volatile ( "flushreg" : : ); /* flush register cache */ \`
302			`\`
303			`(_the_context)->r0_pfp = _stack; \`
304			`(_the_context)->g15_fp = _stack + (1 * sizeof(CPU_Call_frame)); \`
305			`(_the_context)->r1_sp = _stack + (2 * sizeof(CPU_Call_frame)); \`
306			`__asm__ volatile ( "ldconst 0x1f0000,%0 ; " \`
307			`"modpc 0,0,%1 ; " \`
308			`"andnot %0,%1,%1 ; " \`
309			`: "=d" (_mask), "=d" (_base_pc) : ); \`
310			`(_the_context)->pc = _base_pc \| ((_isr) << 16); \`
311			`(_the_context)->g14 = 0; \`
312			`\`
313			`_texit_frame = (CPU_Call_frame *)_stack; \`
314			`_texit_frame->r0_pfp = NULL; \`
315			`_texit_frame->r1_sp = (_the_context)->g15_fp; \`
316			`_texit_frame->r2_rip = (_entry); \`
317			`}`
318
319			`#define _CPU_Context_Restart_self( _the_context ) \`
320			`_CPU_Context_restore( (_the_context) );`
321
322			`#define _CPU_Context_Fp_start( _base, _offset ) NULL`
323
324			`#define _CPU_Context_Initialize_fp( _fp_area )`
325
326			`/* end of Context handler macros */`
327
328			`/*`
329			`* Fatal Error manager macros`
330			`*`
331			`* These macros perform the following functions:`
332			`* + disable interrupts and halt the CPU`
333			`*/`
334
335			`#define _CPU_Fatal_halt( _errorcode ) \`
336			`{ unsigned32 _mask, _level; \`
337			`unsigned32 _error = (_errorcode); \`
338			`\`
339			`__asm__ volatile ( "ldconst 0x1f0000,%0 ; \`
340			`mov %0,%1 ; \`
341			`modpc 0,%0,%1 ; \`
342			`mov %2,g0 ; \`
343			`self: b self " \`
344			`: "=d" (_mask), "=d" (_level), "=d" (_error) : ); \`
345			`}`
346
347			`/* end of Fatal Error Manager macros */`
348
349			`/*`
350			`* Bitfield handler macros`
351			`*`
352			`* These macros perform the following functions:`
353			`* + scan for the highest numbered (MSB) set in a 16 bit bitfield`
354			`*/`
355
356			`#if defined(i960gdbsim)`
357
358			`#define CPU_USE_GENERIC_BITFIELD_CODE TRUE`
359			`#define CPU_USE_GENERIC_BITFIELD_DATA TRUE`
360			`#else`
361			`#define CPU_USE_GENERIC_BITFIELD_CODE FALSE`
362			`#define CPU_USE_GENERIC_BITFIELD_DATA FALSE`
363
364			`#define _CPU_Bitfield_Find_first_bit( _value, _output ) \`
365			`{ unsigned32 _search = (_value); \`
366			`\`
367			`(_output) = 0; /* to prevent warnings */ \`
368			`__asm__ volatile ( "scanbit %0,%1 " \`
369			`: "=d" (_search), "=d" (_output) \`
370			`: "0" (_search), "1" (_output) ); \`
371			`}`
372
373			`/* end of Bitfield handler macros */`
374
375			`/*`
376			`* Priority handler macros`
377			`*`
378			`* These macros perform the following functions:`
379			`* + return a mask with the bit for this major/minor portion of`
380			`* of thread priority set.`
381			`* + translate the bit number returned by "Bitfield_find_first_bit"`
382			`* into an index into the thread ready chain bit maps`
383			`*/`
384
385			`#define _CPU_Priority_Mask( _bit_number ) \`
386			`( 0x8000 >> (_bit_number) )`
387
388			`#define _CPU_Priority_bits_index( _priority ) \`
389			`( 15 - (_priority) )`
390
391			`/* end of Priority handler macros */`
392			`#endif`
393
394			`/* functions */`
395
396			`/*`
397			`* _CPU_Initialize`
398			`*`
399			`* This routine performs CPU dependent initialization.`
400			`*/`
401
402			`void _CPU_Initialize(`
403			`rtems_cpu_table *cpu_table,`
404			`void (*thread_dispatch)`
405			`);`
406
407			`/*`
408			`* _CPU_ISR_install_raw_handler`
409			`*`
410			`* This routine installs a "raw" interrupt handler directly into the`
411			`* processor's vector table.`
412			`*/`
413
414			`void _CPU_ISR_install_raw_handler(`
415			`unsigned32 vector,`
416			`proc_ptr new_handler,`
417			`proc_ptr *old_handler`
418			`);`
419
420			`/*`
421			`* _CPU_ISR_install_vector`
422			`*`
423			`* This routine installs an interrupt vector.`
424			`*/`
425
426			`void _CPU_ISR_install_vector(`
427			`unsigned32 vector,`
428			`proc_ptr new_handler,`
429			`proc_ptr *old_handler`
430			`);`
431
432			`/*`
433			`* _CPU_Install_interrupt_stack`
434			`*`
435			`* This routine installs the hardware interrupt stack pointer.`
436			`*/`
437
438			`void _CPU_Install_interrupt_stack( void );`
439
440			`/*`
441			`* _CPU_Context_switch`
442			`*`
443			`* This routine switches from the run context to the heir context.`
444			`*/`
445
446			`void _CPU_Context_switch(`
447			`Context_Control *run,`
448			`Context_Control *heir`
449			`);`
450
451			`/*`
452			`* _CPU_Context_restore`
453			`*`
454			`* This routine is generally used only to restart self in an`
455			`* efficient manner and avoid stack conflicts.`
456			`*/`
457
458			`void _CPU_Context_restore(`
459			`Context_Control *new_context`
460			`);`
461
462			`/*`
463			`* _CPU_Context_save_fp`
464			`*`
465			`* This routine saves the floating point context passed to it.`
466			`*/`
467
468			`void _CPU_Context_save_fp(`
469			`void **fp_context_ptr`
470			`);`
471
472			`/*`
473			`* _CPU_Context_restore_fp`
474			`*`
475			`* This routine restores the floating point context passed to it.`
476			`*/`
477
478			`void _CPU_Context_restore_fp(`
479			`void **fp_context_ptr`
480			`);`
481
482			`#ifdef __cplusplus`
483			`}`
484			`#endif`
485
486			`#endif`
487			`/* end of include file */`