URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [i960/] [rtems/] [score/] [i960.h] - Blame information for rev 738

Go to most recent revision | Details | Compare with Previous | View Log


/*  i960.h
 *
 *  This include file contains information pertaining to the Intel
 *  i960 processor family.
 *
 *  COPYRIGHT (c) 1989-1999.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.OARcorp.com/rtems/license.html.
 *
 *  $Id: i960.h,v 1.2 2001-09-27 11:59:28 chris Exp $
 */
 
#ifndef __i960_h
#define __i960_h
 
#ifdef __cplusplus
extern "C" {
#endif
 
/*
 *  This file contains the information required to build
 *  RTEMS for a particular member of the Intel i960
 *  family.  It does this by setting variables to indicate
 *  which implementation dependent features are present
 *  in a particular member of the family.
 *
 *  NOTE: For now i960 support is for models without an FPU.
 *        The stubs for FP routines are in  place so only need to be filled in.
 *
 *  NOTE: RTEMS defines a canonical name for each cpu model.
 */
 
#if defined(i960gdbsim)
 
#define CPU_MODEL_NAME  "i960gdbsim"
#define __RTEMS_I960KA__
 
#elif defined(__i960KA__) || defined(__i960_KA__) || defined(__i960KA)
 
#define CPU_MODEL_NAME  "i960ka"
#define __RTEMS_I960KA__
 
#elif defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA)
 
#define CPU_MODEL_NAME  "i960ca"
#define __RTEMS_I960CA__
 
#elif defined(__i960HA__) || defined(__i960_HA__) || defined(__i960HA)
 
#define CPU_MODEL_NAME  "i960ha"
#define __RTEMS_I960HA__
 
#elif defined(__i960RP__)
 
#include <i960RP.h>
#define CPU_MODEL_NAME  "i960rp"
#define __RTEMS_I960RP__
#define I960_CPU_ALIGNMENT 8
#define I960_SOFT_RESET_COMMAND 0x300
 
#else
 
#error "Unsupported CPU Model"
 
#endif
 
/*
 *  Now default some CPU model variation parameters
 */
 
#ifndef I960_HAS_FPU
#define I960_HAS_FPU 0
#endif
 
#ifndef I960_CPU_ALIGNMENT
#define I960_CPU_ALIGNMENT 4
#endif
 
#ifndef I960_SOFT_RESET_COMMAND
#define I960_SOFT_RESET_COMMAND 0x30000
#endif
 
/*
 *  Define the name of the CPU family.
 */
 
#define CPU_NAME "Intel i960"
 
#ifndef ASM
 
/*
 * XXX    should have an ifdef here and have stuff for the other
 * XXX    family members...
 */
 
#if defined(__RTEMS_I960CA__)
/*
 *  Now default some CPU model variation parameters
 */
 
#ifndef I960_HAS_FPU
#define I960_HAS_FPU 0
#endif
 
#ifndef I960_CPU_ALIGNMENT
#define I960_CPU_ALIGNMENT 4
#endif
 
 
/* i960CA control structures */
 
/* Intel i960CA Control Table */
 
typedef struct {
                            /* Control Group 0 */
  unsigned int ipb0;              /* IP breakpoint 0 */
  unsigned int ipb1;              /* IP breakpoint 1 */
  unsigned int dab0;              /* data address breakpoint 0 */
  unsigned int dab1;              /* data address breakpoint 1 */
                            /* Control Group 1 */
  unsigned int imap0;             /* interrupt map 0 */
  unsigned int imap1;             /* interrupt map 1 */
  unsigned int imap2;             /* interrupt map 2 */
  unsigned int icon;              /* interrupt control */
                            /* Control Group 2 */
  unsigned int mcon0;             /* memory region 0 configuration */
  unsigned int mcon1;             /* memory region 1 configuration */
  unsigned int mcon2;             /* memory region 2 configuration */
  unsigned int mcon3;             /* memory region 3 configuration */
                            /* Control Group 3 */
  unsigned int mcon4;             /* memory region 4 configuration */
  unsigned int mcon5;             /* memory region 5 configuration */
  unsigned int mcon6;             /* memory region 6 configuration */
  unsigned int mcon7;             /* memory region 7 configuration */
                            /* Control Group 4 */
  unsigned int mcon8;             /* memory region 8 configuration */
  unsigned int mcon9;             /* memory region 9 configuration */
  unsigned int mcon10;            /* memory region 10 configuration */
  unsigned int mcon11;            /* memory region 11 configuration */
                            /* Control Group 5 */
  unsigned int mcon12;            /* memory region 12 configuration */
  unsigned int mcon13;            /* memory region 13 configuration */
  unsigned int mcon14;            /* memory region 14 configuration */
  unsigned int mcon15;            /* memory region 15 configuration */
                            /* Control Group 6 */
  unsigned int reserved;          /* reserved */
  unsigned int bpcon;             /* breakpoint control */
  unsigned int tc;                /* trace control */
  unsigned int bcon;              /* bus configuration control */
}   i960ca_control_table;
 
/* Intel i960CA Processor Control Block */
 
typedef struct {
  unsigned int    *fault_tbl;     /* fault table base address */
  i960ca_control_table
                  *control_tbl;   /* control table base address */
  unsigned int     initial_ac;    /* AC register initial value */
  unsigned int     fault_config;  /* fault configuration word */
  void           **intr_tbl;      /* interrupt table base address */
  void            *sys_proc_tbl;  /* system procedure table
                                     base address */
  unsigned int     reserved;      /* reserved */
  unsigned int    *intr_stack;    /* interrupt stack pointer */
  unsigned int     ins_cache_cfg; /* instruction cache
                                     configuration word */
  unsigned int     reg_cache_cfg; /* register cache configuration word */
}   i960ca_PRCB;
 
typedef i960ca_control_table i960_control_table;
typedef i960ca_PRCB i960_PRCB;
 
#elif defined(__RTEMS_I960HA__)
 
/* i960HA control structures */
 
/* Intel i960HA Control Table */
 
typedef struct {
                            /* Control Group 0 */
  unsigned int ipb0;              /* IP breakpoint 0 */
  unsigned int ipb1;              /* IP breakpoint 1 */
  unsigned int dab0;              /* data address breakpoint 0 */
  unsigned int dab1;              /* data address breakpoint 1 */
                            /* Control Group 1 */
  unsigned int imap0;             /* interrupt map 0 */
  unsigned int imap1;             /* interrupt map 1 */
  unsigned int imap2;             /* interrupt map 2 */
  unsigned int icon;              /* interrupt control */
                            /* Control Group 2 */
  unsigned int mcon0;             /* memory region 0 configuration */
  unsigned int mcon1;             /* memory region 1 configuration */
  unsigned int mcon2;             /* memory region 2 configuration */
  unsigned int mcon3;             /* memory region 3 configuration */
                            /* Control Group 3 */
  unsigned int mcon4;             /* memory region 4 configuration */
  unsigned int mcon5;             /* memory region 5 configuration */
  unsigned int mcon6;             /* memory region 6 configuration */
  unsigned int mcon7;             /* memory region 7 configuration */
                            /* Control Group 4 */
  unsigned int mcon8;             /* memory region 8 configuration */
  unsigned int mcon9;             /* memory region 9 configuration */
  unsigned int mcon10;            /* memory region 10 configuration */
  unsigned int mcon11;            /* memory region 11 configuration */
                            /* Control Group 5 */
  unsigned int mcon12;            /* memory region 12 configuration */
  unsigned int mcon13;            /* memory region 13 configuration */
  unsigned int mcon14;            /* memory region 14 configuration */
  unsigned int mcon15;            /* memory region 15 configuration */
                            /* Control Group 6 */
  unsigned int reserved;          /* reserved */
  unsigned int bpcon;             /* breakpoint control */
  unsigned int tc;                /* trace control */
  unsigned int bcon;              /* bus configuration control */
}   i960ha_control_table;
 
/* Intel i960HA Processor Control Block */
 
typedef struct {
  unsigned int    *fault_tbl;     /* fault table base address */
  i960ha_control_table
                  *control_tbl;   /* control table base address */
  unsigned int     initial_ac;    /* AC register initial value */
  unsigned int     fault_config;  /* fault configuration word */
  void           **intr_tbl;      /* interrupt table base address */
  void            *sys_proc_tbl;  /* system procedure table
                                     base address */
  unsigned int     reserved;      /* reserved */
  unsigned int    *intr_stack;    /* interrupt stack pointer */
  unsigned int     ins_cache_cfg; /* instruction cache
                                     configuration word */
  unsigned int     reg_cache_cfg; /* register cache configuration word */
}   i960ha_PRCB;
 
typedef i960ha_control_table i960_control_table;
typedef i960ha_PRCB i960_PRCB;
 
#elif defined(__RTEMS_I960RP__)
 
/* i960RP control structures */
 
/* Intel i960RP Control Table */
 
typedef struct {
                            /* Control Group 0 */
  unsigned int rsvd00;
  unsigned int rsvd01;
  unsigned int rsvd02;
  unsigned int rsvd03;
                            /* Control Group 1 */
  unsigned int imap0;             /* interrupt map 0 */
  unsigned int imap1;             /* interrupt map 1 */
  unsigned int imap2;             /* interrupt map 2 */
  unsigned int icon;              /* interrupt control */
                            /* Control Group 2 */
  unsigned int pmcon0;            /* memory region 0 configuration */
  unsigned int rsvd1;
  unsigned int pmcon2;            /* memory region 2 configuration */
  unsigned int rsvd2;
                            /* Control Group 3 */
  unsigned int pmcon4;            /* memory region 4 configuration */
  unsigned int rsvd3;
  unsigned int pmcon6;            /* memory region 6 configuration */
  unsigned int rsvd4;
                            /* Control Group 4 */
  unsigned int pmcon8;            /* memory region 8 configuration */
  unsigned int rsvd5;
  unsigned int pmcon10;           /* memory region 10 configuration */
  unsigned int rsvd6;
                            /* Control Group 5 */
  unsigned int pmcon12;           /* memory region 12 configuration */
  unsigned int rsvd7;
  unsigned int pmcon14;           /* memory region 14 configuration */
  unsigned int rsvd8;
                            /* Control Group 6 */
  unsigned int rsvd9;
  unsigned int rsvd10;
  unsigned int tc;                /* trace control */
  unsigned int bcon;              /* bus configuration control */
}   i960rp_control_table;
 
/* Intel i960RP Processor Control Block */
 
typedef struct {
  unsigned int    *fault_tbl;     /* fault table base address */
  i960rp_control_table
                  *control_tbl;   /* control table base address */
  unsigned int     initial_ac;    /* AC register initial value */
  unsigned int     fault_config;  /* fault configuration word */
  void           **intr_tbl;      /* interrupt table base address */
  void            *sys_proc_tbl;  /* system procedure table
                                     base address */
  unsigned int     reserved;      /* reserved */
  unsigned int    *intr_stack;    /* interrupt stack pointer */
  unsigned int     ins_cache_cfg; /* instruction cache
                                     configuration word */
  unsigned int     reg_cache_cfg; /* register cache configuration word */
}   i960rp_PRCB;
 
typedef i960rp_control_table i960_control_table;
typedef i960rp_PRCB i960_PRCB;
 
#elif defined(__RTEMS_I960KA__)
 
typedef struct {
  int fixme;
}   i960ka_control_table;
 
typedef struct {
  void           **intr_tbl;      /* interrupt table base address */
  unsigned int    *intr_stack;    /* interrupt stack pointer */
  int fixme;
}   i960ka_PRCB;
 
typedef i960ka_control_table i960_control_table;
typedef i960ka_PRCB i960_PRCB;
#else
#error "invalid processor selection!"
#endif
 
/*
 *  Miscellaneous Support Routines
 */
 
#define i960_reload_ctl_group( group ) \
 { register int _cmd = ((group)|0x400) ; \
   asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \
 }
 
#define i960_atomic_modify( mask, addr, prev ) \
 { register unsigned int  _mask = (mask); \
   register unsigned int *_addr = (unsigned int *)(addr); \
   asm volatile( "atmod  %0,%1,%1" \
                  : "=d" (_addr), "=d" (_mask) \
                  : "0"  (_addr), "1"  (_mask) ); \
   (prev) = _mask; \
 }
 
#define atomic_modify( _mask, _address, _previous ) \
  i960_atomic_modify( _mask, _address, _previous )
 
#define i960_enable_tracing() \
 { register unsigned int _pc = 0x1; \
   asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \
 }
 
/*
 *  Interrupt Level Routines
 */
 
#define i960_disable_interrupts( oldlevel ) \
  { (oldlevel) = 0x1f0000; \
    asm volatile ( "modpc   0,%1,%1" \
                       : "=d" ((oldlevel)) \
                       : "0"  ((oldlevel)) ); \
  }
 
#define i960_enable_interrupts( oldlevel ) \
  { unsigned int _mask = 0x1f0000; \
    asm volatile ( "modpc   0,%0,%1" \
                       : "=d" (_mask), "=d" ((oldlevel)) \
                       : "0"  (_mask), "1"  ((oldlevel)) ); \
  }
 
#define i960_flash_interrupts( oldlevel ) \
  { unsigned int _mask = 0x1f0000; \
    asm volatile ( "modpc   0,%0,%1 ; \
                    mov     %0,%1 ; \
                    modpc   0,%0,%1"  \
                       : "=d" (_mask), "=d" ((oldlevel)) \
                       : "0"  (_mask), "1"  ((oldlevel)) ); \
  }
 
#define i960_get_interrupt_level( _level ) \
  { \
    i960_disable_interrupts( _level ); \
    i960_enable_interrupts( _level ); \
    (_level) = ((_level) & 0x1f0000) >> 16; \
  } while ( 0 )
 
#define i960_cause_intr( intr ) \
 { register int _intr = (intr); \
   asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \
 }
 
/*
 *  Interrupt Masking Routines
 */
 
#if defined(__RTEMS_I960CA__) || defined(__RTEMS_I960HA__)
 
#define i960_unmask_intr( xint ) \
 { register unsigned int _mask= (1<<(xint)); \
   asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \
 }
 
#define i960_mask_intr( xint ) \
 { register unsigned int _mask= (1<<(xint)); \
   asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \
 }
 
#define i960_clear_intr( xint ) \
 { register unsigned int _xint=(xint); \
asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \
                  bbs    %0,sf0, loop_til_cleared" \
                  : "=d" (_xint) : "0" (_xint) ); \
 }
 
static inline unsigned int i960_pend_intrs()
{ register unsigned int _intr=0;
  asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) );
  return ( _intr );
}
 
static inline unsigned int i960_mask_intrs()
{ register unsigned int _intr=0;
  asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );
  return( _intr );
}
 
#elif defined(__RTEMS_I960RP__)
 
#define i960_unmask_intr( xint ) \
 { register unsigned int _mask= (1<<(xint)); \
   register unsigned int *_imsk = (int * ) IMSK_ADDR; \
   register unsigned int _val= *_imsk; \
   asm volatile( "or %0,%2,%0; \
                  st %0,(%1)" \
                    : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
                    : "0" (_val), "1" (_imsk), "2" (_mask) ); \
 }
 
#define i960_mask_intr( xint ) \
 { register unsigned int _mask= (1<<(xint)); \
   register unsigned int *_imsk = (int * ) IMSK_ADDR; \
   register unsigned int _val = *_imsk; \
   asm volatile( "andnot %2,%0,%0; \
                  st %0,(%1)" \
                    : "=d" (_val), "=d" (_imsk), "=d" (_mask) \
                    : "0" (_val), "1" (_imsk), "2" (_mask) ); \
 }
#define i960_clear_intr( xint ) \
 { register unsigned int _xint=xint; \
   register unsigned int _mask=(1<<(xint)); \
   register unsigned int *_ipnd = (int * ) IPND_ADDR; \
   register unsigned int          _rslt = 0; \
asm volatile( "loop_til_cleared: mov 0, %0; \
                  atmod %1, %2, %0; \
                  bbs    %3,%0, loop_til_cleared" \
                  : "=d" (_rslt), "=d" (_ipnd), "=d" (_mask), "=d" (_xint) \
                  : "0"  (_rslt), "1"  (_ipnd), "2"  (_mask), "3"  (_xint) ); \
 }
 
static inline unsigned int i960_pend_intrs()
{ register unsigned int _intr= *(unsigned int *) IPND_ADDR;
  /*register unsigned int *_ipnd = (int * ) IPND_ADDR; \
   asm volatile( "mov (%0),%1" \
                    : "=d" (_ipnd), "=d" (_mask) \
                    : "0" (_ipnd), "1" (_mask) ); \ */
  return ( _intr );
}
 
static inline unsigned int i960_mask_intrs()
{ register unsigned int _intr= *(unsigned int *) IMSK_ADDR;
  /*asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );*/
  return( _intr );
}
#endif
 
static inline unsigned int i960_get_fp()
{ register unsigned int _fp=0;
  asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) );
  return ( _fp );
}
 
/*
 *  Soft Reset
 */
 
#if defined(I960_SOFT_RESET_COMMAND)
 
#define i960_soft_reset( prcb ) \
 { register i960_PRCB    *_prcb = (prcb); \
   register unsigned int *_next=0; \
   register unsigned int  _cmd  = I960_SOFT_RESET_COMMAND; \
   asm volatile( "lda    next,%1; \
                  sysctl %0,%1,%2; \
            next: mov    g0,g0" \
                  : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \
                  : "0"  (_cmd), "1"  (_next), "2"  (_prcb) ); \
 }
 
#else
#warning "I960_SOFT_RESET_COMMAND is not defined"
#endif
 
/*
 *  The following routine swaps the endian format of an unsigned int.
 *  It must be static because it is referenced indirectly.
 *
 *  This version is based on code presented in Vol. 4, No. 4 of
 *  Insight 960.  It is certainly something you wouldn't think
 *  of on your own.
 */
 
static inline unsigned int CPU_swap_u32(
  unsigned int value
)
{
  register unsigned int to_swap = value;
  register unsigned int temp    = 0xFF00FF00;
  register unsigned int swapped = 0;
 
                                            /*  to_swap      swapped  */
  asm volatile ( "rotate  16,%0,%2 ;"       /* 0x12345678  0x56781234 */
                 "modify  %1,%0,%2 ;"       /* 0x12345678  0x12785634 */
                 "rotate  8,%2,%2"          /* 0x12345678  0x78563412 */
                 : "=r" (to_swap), "=r" (temp), "=r" (swapped)
                 : "0" (to_swap), "1" (temp), "2" (swapped)
               );
  return( swapped );
}
 
#define CPU_swap_u16( value ) \
  (((value&0xff) << 8) | ((value >> 8)&0xff))
 
#ifdef __cplusplus
}
#endif
 
#endif /* !ASM */
 
#endif
/* end of include file */

Browse

Tools

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [i960/] [rtems/] [score/] [i960.h] - Blame information for rev 738

Line No.	Rev	Author	Line
1	30	unneback	`/* i960.h`
2			`*`
3			`* This include file contains information pertaining to the Intel`
4			`* i960 processor family.`
5			`*`
6			`* COPYRIGHT (c) 1989-1999.`
7			`* On-Line Applications Research Corporation (OAR).`
8			`*`
9			`* The license and distribution terms for this file may be`
10			`* found in the file LICENSE in this distribution or at`
11			`* http://www.OARcorp.com/rtems/license.html.`
12			`*`
13			`* $Id: i960.h,v 1.2 2001-09-27 11:59:28 chris Exp $`
14			`*/`
15
16			`#ifndef __i960_h`
17			`#define __i960_h`
18
19			`#ifdef __cplusplus`
20			`extern "C" {`
21			`#endif`
22
23			`/*`
24			`* This file contains the information required to build`
25			`* RTEMS for a particular member of the Intel i960`
26			`* family. It does this by setting variables to indicate`
27			`* which implementation dependent features are present`
28			`* in a particular member of the family.`
29			`*`
30			`* NOTE: For now i960 support is for models without an FPU.`
31			`* The stubs for FP routines are in place so only need to be filled in.`
32			`*`
33			`* NOTE: RTEMS defines a canonical name for each cpu model.`
34			`*/`
35
36			`#if defined(i960gdbsim)`
37
38			`#define CPU_MODEL_NAME "i960gdbsim"`
39			`#define __RTEMS_I960KA__`
40
41			`#elif defined(__i960KA__) \|\| defined(__i960_KA__) \|\| defined(__i960KA)`
42
43			`#define CPU_MODEL_NAME "i960ka"`
44			`#define __RTEMS_I960KA__`
45
46			`#elif defined(__i960CA__) \|\| defined(__i960_CA__) \|\| defined(__i960CA)`
47
48			`#define CPU_MODEL_NAME "i960ca"`
49			`#define __RTEMS_I960CA__`
50
51			`#elif defined(__i960HA__) \|\| defined(__i960_HA__) \|\| defined(__i960HA)`
52
53			`#define CPU_MODEL_NAME "i960ha"`
54			`#define __RTEMS_I960HA__`
55
56			`#elif defined(__i960RP__)`
57
58			`#include <i960RP.h>`
59			`#define CPU_MODEL_NAME "i960rp"`
60			`#define __RTEMS_I960RP__`
61			`#define I960_CPU_ALIGNMENT 8`
62			`#define I960_SOFT_RESET_COMMAND 0x300`
63
64			`#else`
65
66			`#error "Unsupported CPU Model"`
67
68			`#endif`
69
70			`/*`
71			`* Now default some CPU model variation parameters`
72			`*/`
73
74			`#ifndef I960_HAS_FPU`
75			`#define I960_HAS_FPU 0`
76			`#endif`
77
78			`#ifndef I960_CPU_ALIGNMENT`
79			`#define I960_CPU_ALIGNMENT 4`
80			`#endif`
81
82			`#ifndef I960_SOFT_RESET_COMMAND`
83			`#define I960_SOFT_RESET_COMMAND 0x30000`
84			`#endif`
85
86			`/*`
87			`* Define the name of the CPU family.`
88			`*/`
89
90			`#define CPU_NAME "Intel i960"`
91
92			`#ifndef ASM`
93
94			`/*`
95			`* XXX should have an ifdef here and have stuff for the other`
96			`* XXX family members...`
97			`*/`
98
99			`#if defined(__RTEMS_I960CA__)`
100			`/*`
101			`* Now default some CPU model variation parameters`
102			`*/`
103
104			`#ifndef I960_HAS_FPU`
105			`#define I960_HAS_FPU 0`
106			`#endif`
107
108			`#ifndef I960_CPU_ALIGNMENT`
109			`#define I960_CPU_ALIGNMENT 4`
110			`#endif`
111
112
113			`/* i960CA control structures */`
114
115			`/* Intel i960CA Control Table */`
116
117			`typedef struct {`
118			`/* Control Group 0 */`
119			`unsigned int ipb0; /* IP breakpoint 0 */`
120			`unsigned int ipb1; /* IP breakpoint 1 */`
121			`unsigned int dab0; /* data address breakpoint 0 */`
122			`unsigned int dab1; /* data address breakpoint 1 */`
123			`/* Control Group 1 */`
124			`unsigned int imap0; /* interrupt map 0 */`
125			`unsigned int imap1; /* interrupt map 1 */`
126			`unsigned int imap2; /* interrupt map 2 */`
127			`unsigned int icon; /* interrupt control */`
128			`/* Control Group 2 */`
129			`unsigned int mcon0; /* memory region 0 configuration */`
130			`unsigned int mcon1; /* memory region 1 configuration */`
131			`unsigned int mcon2; /* memory region 2 configuration */`
132			`unsigned int mcon3; /* memory region 3 configuration */`
133			`/* Control Group 3 */`
134			`unsigned int mcon4; /* memory region 4 configuration */`
135			`unsigned int mcon5; /* memory region 5 configuration */`
136			`unsigned int mcon6; /* memory region 6 configuration */`
137			`unsigned int mcon7; /* memory region 7 configuration */`
138			`/* Control Group 4 */`
139			`unsigned int mcon8; /* memory region 8 configuration */`
140			`unsigned int mcon9; /* memory region 9 configuration */`
141			`unsigned int mcon10; /* memory region 10 configuration */`
142			`unsigned int mcon11; /* memory region 11 configuration */`
143			`/* Control Group 5 */`
144			`unsigned int mcon12; /* memory region 12 configuration */`
145			`unsigned int mcon13; /* memory region 13 configuration */`
146			`unsigned int mcon14; /* memory region 14 configuration */`
147			`unsigned int mcon15; /* memory region 15 configuration */`
148			`/* Control Group 6 */`
149			`unsigned int reserved; /* reserved */`
150			`unsigned int bpcon; /* breakpoint control */`
151			`unsigned int tc; /* trace control */`
152			`unsigned int bcon; /* bus configuration control */`
153			`} i960ca_control_table;`
154
155			`/* Intel i960CA Processor Control Block */`
156
157			`typedef struct {`
158			`unsigned int fault_tbl; / fault table base address */`
159			`i960ca_control_table`
160			`control_tbl; / control table base address */`
161			`unsigned int initial_ac; /* AC register initial value */`
162			`unsigned int fault_config; /* fault configuration word */`
163			`void *intr_tbl; / interrupt table base address */`
164			`void sys_proc_tbl; / system procedure table`
165			`base address */`
166			`unsigned int reserved; /* reserved */`
167			`unsigned int intr_stack; / interrupt stack pointer */`
168			`unsigned int ins_cache_cfg; /* instruction cache`
169			`configuration word */`
170			`unsigned int reg_cache_cfg; /* register cache configuration word */`
171			`} i960ca_PRCB;`
172
173			`typedef i960ca_control_table i960_control_table;`
174			`typedef i960ca_PRCB i960_PRCB;`
175
176			`#elif defined(__RTEMS_I960HA__)`
177
178			`/* i960HA control structures */`
179
180			`/* Intel i960HA Control Table */`
181
182			`typedef struct {`
183			`/* Control Group 0 */`
184			`unsigned int ipb0; /* IP breakpoint 0 */`
185			`unsigned int ipb1; /* IP breakpoint 1 */`
186			`unsigned int dab0; /* data address breakpoint 0 */`
187			`unsigned int dab1; /* data address breakpoint 1 */`
188			`/* Control Group 1 */`
189			`unsigned int imap0; /* interrupt map 0 */`
190			`unsigned int imap1; /* interrupt map 1 */`
191			`unsigned int imap2; /* interrupt map 2 */`
192			`unsigned int icon; /* interrupt control */`
193			`/* Control Group 2 */`
194			`unsigned int mcon0; /* memory region 0 configuration */`
195			`unsigned int mcon1; /* memory region 1 configuration */`
196			`unsigned int mcon2; /* memory region 2 configuration */`
197			`unsigned int mcon3; /* memory region 3 configuration */`
198			`/* Control Group 3 */`
199			`unsigned int mcon4; /* memory region 4 configuration */`
200			`unsigned int mcon5; /* memory region 5 configuration */`
201			`unsigned int mcon6; /* memory region 6 configuration */`
202			`unsigned int mcon7; /* memory region 7 configuration */`
203			`/* Control Group 4 */`
204			`unsigned int mcon8; /* memory region 8 configuration */`
205			`unsigned int mcon9; /* memory region 9 configuration */`
206			`unsigned int mcon10; /* memory region 10 configuration */`
207			`unsigned int mcon11; /* memory region 11 configuration */`
208			`/* Control Group 5 */`
209			`unsigned int mcon12; /* memory region 12 configuration */`
210			`unsigned int mcon13; /* memory region 13 configuration */`
211			`unsigned int mcon14; /* memory region 14 configuration */`
212			`unsigned int mcon15; /* memory region 15 configuration */`
213			`/* Control Group 6 */`
214			`unsigned int reserved; /* reserved */`
215			`unsigned int bpcon; /* breakpoint control */`
216			`unsigned int tc; /* trace control */`
217			`unsigned int bcon; /* bus configuration control */`
218			`} i960ha_control_table;`
219
220			`/* Intel i960HA Processor Control Block */`
221
222			`typedef struct {`
223			`unsigned int fault_tbl; / fault table base address */`
224			`i960ha_control_table`
225			`control_tbl; / control table base address */`
226			`unsigned int initial_ac; /* AC register initial value */`
227			`unsigned int fault_config; /* fault configuration word */`
228			`void *intr_tbl; / interrupt table base address */`
229			`void sys_proc_tbl; / system procedure table`
230			`base address */`
231			`unsigned int reserved; /* reserved */`
232			`unsigned int intr_stack; / interrupt stack pointer */`
233			`unsigned int ins_cache_cfg; /* instruction cache`
234			`configuration word */`
235			`unsigned int reg_cache_cfg; /* register cache configuration word */`
236			`} i960ha_PRCB;`
237
238			`typedef i960ha_control_table i960_control_table;`
239			`typedef i960ha_PRCB i960_PRCB;`
240
241			`#elif defined(__RTEMS_I960RP__)`
242
243			`/* i960RP control structures */`
244
245			`/* Intel i960RP Control Table */`
246
247			`typedef struct {`
248			`/* Control Group 0 */`
249			`unsigned int rsvd00;`
250			`unsigned int rsvd01;`
251			`unsigned int rsvd02;`
252			`unsigned int rsvd03;`
253			`/* Control Group 1 */`
254			`unsigned int imap0; /* interrupt map 0 */`
255			`unsigned int imap1; /* interrupt map 1 */`
256			`unsigned int imap2; /* interrupt map 2 */`
257			`unsigned int icon; /* interrupt control */`
258			`/* Control Group 2 */`
259			`unsigned int pmcon0; /* memory region 0 configuration */`
260			`unsigned int rsvd1;`
261			`unsigned int pmcon2; /* memory region 2 configuration */`
262			`unsigned int rsvd2;`
263			`/* Control Group 3 */`
264			`unsigned int pmcon4; /* memory region 4 configuration */`
265			`unsigned int rsvd3;`
266			`unsigned int pmcon6; /* memory region 6 configuration */`
267			`unsigned int rsvd4;`
268			`/* Control Group 4 */`
269			`unsigned int pmcon8; /* memory region 8 configuration */`
270			`unsigned int rsvd5;`
271			`unsigned int pmcon10; /* memory region 10 configuration */`
272			`unsigned int rsvd6;`
273			`/* Control Group 5 */`
274			`unsigned int pmcon12; /* memory region 12 configuration */`
275			`unsigned int rsvd7;`
276			`unsigned int pmcon14; /* memory region 14 configuration */`
277			`unsigned int rsvd8;`
278			`/* Control Group 6 */`
279			`unsigned int rsvd9;`
280			`unsigned int rsvd10;`
281			`unsigned int tc; /* trace control */`
282			`unsigned int bcon; /* bus configuration control */`
283			`} i960rp_control_table;`
284
285			`/* Intel i960RP Processor Control Block */`
286
287			`typedef struct {`
288			`unsigned int fault_tbl; / fault table base address */`
289			`i960rp_control_table`
290			`control_tbl; / control table base address */`
291			`unsigned int initial_ac; /* AC register initial value */`
292			`unsigned int fault_config; /* fault configuration word */`
293			`void *intr_tbl; / interrupt table base address */`
294			`void sys_proc_tbl; / system procedure table`
295			`base address */`
296			`unsigned int reserved; /* reserved */`
297			`unsigned int intr_stack; / interrupt stack pointer */`
298			`unsigned int ins_cache_cfg; /* instruction cache`
299			`configuration word */`
300			`unsigned int reg_cache_cfg; /* register cache configuration word */`
301			`} i960rp_PRCB;`
302
303			`typedef i960rp_control_table i960_control_table;`
304			`typedef i960rp_PRCB i960_PRCB;`
305
306			`#elif defined(__RTEMS_I960KA__)`
307
308			`typedef struct {`
309			`int fixme;`
310			`} i960ka_control_table;`
311
312			`typedef struct {`
313			`void *intr_tbl; / interrupt table base address */`
314			`unsigned int intr_stack; / interrupt stack pointer */`
315			`int fixme;`
316			`} i960ka_PRCB;`
317
318			`typedef i960ka_control_table i960_control_table;`
319			`typedef i960ka_PRCB i960_PRCB;`
320			`#else`
321			`#error "invalid processor selection!"`
322			`#endif`
323
324			`/*`
325			`* Miscellaneous Support Routines`
326			`*/`
327
328			`#define i960_reload_ctl_group( group ) \`
329			`{ register int _cmd = ((group)\|0x400) ; \`
330			`asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \`
331			`}`
332
333			`#define i960_atomic_modify( mask, addr, prev ) \`
334			`{ register unsigned int _mask = (mask); \`
335			`register unsigned int _addr = (unsigned int )(addr); \`
336			`asm volatile( "atmod %0,%1,%1" \`
337			`: "=d" (_addr), "=d" (_mask) \`
338			`: "0" (_addr), "1" (_mask) ); \`
339			`(prev) = _mask; \`
340			`}`
341
342			`#define atomic_modify( _mask, _address, _previous ) \`
343			`i960_atomic_modify( _mask, _address, _previous )`
344
345			`#define i960_enable_tracing() \`
346			`{ register unsigned int _pc = 0x1; \`
347			`asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \`
348			`}`
349
350			`/*`
351			`* Interrupt Level Routines`
352			`*/`
353
354			`#define i960_disable_interrupts( oldlevel ) \`
355			`{ (oldlevel) = 0x1f0000; \`
356			`asm volatile ( "modpc 0,%1,%1" \`
357			`: "=d" ((oldlevel)) \`
358			`: "0" ((oldlevel)) ); \`
359			`}`
360
361			`#define i960_enable_interrupts( oldlevel ) \`
362			`{ unsigned int _mask = 0x1f0000; \`
363			`asm volatile ( "modpc 0,%0,%1" \`
364			`: "=d" (_mask), "=d" ((oldlevel)) \`
365			`: "0" (_mask), "1" ((oldlevel)) ); \`
366			`}`
367
368			`#define i960_flash_interrupts( oldlevel ) \`
369			`{ unsigned int _mask = 0x1f0000; \`
370			`asm volatile ( "modpc 0,%0,%1 ; \`
371			`mov %0,%1 ; \`
372			`modpc 0,%0,%1" \`
373			`: "=d" (_mask), "=d" ((oldlevel)) \`
374			`: "0" (_mask), "1" ((oldlevel)) ); \`
375			`}`
376
377			`#define i960_get_interrupt_level( _level ) \`
378			`{ \`
379			`i960_disable_interrupts( _level ); \`
380			`i960_enable_interrupts( _level ); \`
381			`(_level) = ((_level) & 0x1f0000) >> 16; \`
382			`} while ( 0 )`
383
384			`#define i960_cause_intr( intr ) \`
385			`{ register int _intr = (intr); \`
386			`asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \`
387			`}`
388
389			`/*`
390			`* Interrupt Masking Routines`
391			`*/`
392
393			`#if defined(__RTEMS_I960CA__) \|\| defined(__RTEMS_I960HA__)`
394
395			`#define i960_unmask_intr( xint ) \`
396			`{ register unsigned int _mask= (1<<(xint)); \`
397			`asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \`
398			`}`
399
400			`#define i960_mask_intr( xint ) \`
401			`{ register unsigned int _mask= (1<<(xint)); \`
402			`asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \`
403			`}`
404
405			`#define i960_clear_intr( xint ) \`
406			`{ register unsigned int _xint=(xint); \`
407			`asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \`
408			`bbs %0,sf0, loop_til_cleared" \`
409			`: "=d" (_xint) : "0" (_xint) ); \`
410			`}`
411
412			`static inline unsigned int i960_pend_intrs()`
413			`{ register unsigned int _intr=0;`
414			`asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) );`
415			`return ( _intr );`
416			`}`
417
418			`static inline unsigned int i960_mask_intrs()`
419			`{ register unsigned int _intr=0;`
420			`asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );`
421			`return( _intr );`
422			`}`
423
424			`#elif defined(__RTEMS_I960RP__)`
425
426			`#define i960_unmask_intr( xint ) \`
427			`{ register unsigned int _mask= (1<<(xint)); \`
428			`register unsigned int _imsk = (int ) IMSK_ADDR; \`
429			`register unsigned int _val= *_imsk; \`
430			`asm volatile( "or %0,%2,%0; \`
431			`st %0,(%1)" \`
432			`: "=d" (_val), "=d" (_imsk), "=d" (_mask) \`
433			`: "0" (_val), "1" (_imsk), "2" (_mask) ); \`
434			`}`
435
436			`#define i960_mask_intr( xint ) \`
437			`{ register unsigned int _mask= (1<<(xint)); \`
438			`register unsigned int _imsk = (int ) IMSK_ADDR; \`
439			`register unsigned int _val = *_imsk; \`
440			`asm volatile( "andnot %2,%0,%0; \`
441			`st %0,(%1)" \`
442			`: "=d" (_val), "=d" (_imsk), "=d" (_mask) \`
443			`: "0" (_val), "1" (_imsk), "2" (_mask) ); \`
444			`}`
445			`#define i960_clear_intr( xint ) \`
446			`{ register unsigned int _xint=xint; \`
447			`register unsigned int _mask=(1<<(xint)); \`
448			`register unsigned int _ipnd = (int ) IPND_ADDR; \`
449			`register unsigned int _rslt = 0; \`
450			`asm volatile( "loop_til_cleared: mov 0, %0; \`
451			`atmod %1, %2, %0; \`
452			`bbs %3,%0, loop_til_cleared" \`
453			`: "=d" (_rslt), "=d" (_ipnd), "=d" (_mask), "=d" (_xint) \`
454			`: "0" (_rslt), "1" (_ipnd), "2" (_mask), "3" (_xint) ); \`
455			`}`
456
457			`static inline unsigned int i960_pend_intrs()`
458			`{ register unsigned int _intr= (unsigned int ) IPND_ADDR;`
459			`/register unsigned int _ipnd = (int * ) IPND_ADDR; \`
460			`asm volatile( "mov (%0),%1" \`
461			`: "=d" (_ipnd), "=d" (_mask) \`
462			`: "0" (_ipnd), "1" (_mask) ); \ */`
463			`return ( _intr );`
464			`}`
465
466			`static inline unsigned int i960_mask_intrs()`
467			`{ register unsigned int _intr= (unsigned int ) IMSK_ADDR;`
468			`/asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );/`
469			`return( _intr );`
470			`}`
471			`#endif`
472
473			`static inline unsigned int i960_get_fp()`
474			`{ register unsigned int _fp=0;`
475			`asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) );`
476			`return ( _fp );`
477			`}`
478
479			`/*`
480			`* Soft Reset`
481			`*/`
482
483			`#if defined(I960_SOFT_RESET_COMMAND)`
484
485			`#define i960_soft_reset( prcb ) \`
486			`{ register i960_PRCB *_prcb = (prcb); \`
487			`register unsigned int *_next=0; \`
488			`register unsigned int _cmd = I960_SOFT_RESET_COMMAND; \`
489			`asm volatile( "lda next,%1; \`
490			`sysctl %0,%1,%2; \`
491			`next: mov g0,g0" \`
492			`: "=d" (_cmd), "=d" (_next), "=d" (_prcb) \`
493			`: "0" (_cmd), "1" (_next), "2" (_prcb) ); \`
494			`}`
495
496			`#else`
497			`#warning "I960_SOFT_RESET_COMMAND is not defined"`
498			`#endif`
499
500			`/*`
501			`* The following routine swaps the endian format of an unsigned int.`
502			`* It must be static because it is referenced indirectly.`
503			`*`
504			`* This version is based on code presented in Vol. 4, No. 4 of`
505			`* Insight 960. It is certainly something you wouldn't think`
506			`* of on your own.`
507			`*/`
508
509			`static inline unsigned int CPU_swap_u32(`
510			`unsigned int value`
511			`)`
512			`{`
513			`register unsigned int to_swap = value;`
514			`register unsigned int temp = 0xFF00FF00;`
515			`register unsigned int swapped = 0;`
516
517			`/* to_swap swapped */`
518			`asm volatile ( "rotate 16,%0,%2 ;" /* 0x12345678 0x56781234 */`
519			`"modify %1,%0,%2 ;" /* 0x12345678 0x12785634 */`
520			`"rotate 8,%2,%2" /* 0x12345678 0x78563412 */`
521			`: "=r" (to_swap), "=r" (temp), "=r" (swapped)`
522			`: "0" (to_swap), "1" (temp), "2" (swapped)`
523			`);`
524			`return( swapped );`
525			`}`
526
527			`#define CPU_swap_u16( value ) \`
528			`(((value&0xff) << 8) \| ((value >> 8)&0xff))`
529
530			`#ifdef __cplusplus`
531			`}`
532			`#endif`
533
534			`#endif /* !ASM */`
535
536			`#endif`
537			`/* end of include file */`