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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [m68k/] [cpu.c] - Blame information for rev 173

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Line No. Rev Author Line
1 30 unneback
/*
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 *  Motorola MC68xxx Dependent Source
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 *
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 *  COPYRIGHT (c) 1989-1999.
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 *  On-Line Applications Research Corporation (OAR).
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 *
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 *  The license and distribution terms for this file may be
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 *  found in the file LICENSE in this distribution or at
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 *  http://www.OARcorp.com/rtems/license.html.
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 *
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 *  $Id: cpu.c,v 1.2 2001-09-27 11:59:28 chris Exp $
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 */
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#include <rtems/system.h>
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#include <rtems/score/isr.h>
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/*  _CPU_Initialize
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 *
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 *  This routine performs processor dependent initialization.
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 *
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 *  INPUT PARAMETERS:
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 *    cpu_table       - CPU table to initialize
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 *    thread_dispatch - entry pointer to thread dispatcher
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 *
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 *  OUTPUT PARAMETERS: NONE
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 */
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void _CPU_Initialize(
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  rtems_cpu_table  *cpu_table,
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  void      (*thread_dispatch)      /* ignored on this CPU */
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)
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{
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#if ( M68K_HAS_VBR == 0 )
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  /* fill the isr redirect table with the code to place the format/id
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     onto the stack */
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  unsigned32 slot;
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  for (slot = 0; slot < CPU_INTERRUPT_NUMBER_OF_VECTORS; slot++)
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  {
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    _CPU_ISR_jump_table[slot].move_a7 = M68K_MOVE_A7;
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    _CPU_ISR_jump_table[slot].format_id = slot << 2;
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    _CPU_ISR_jump_table[slot].jmp = M68K_JMP;
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    _CPU_ISR_jump_table[slot].isr_handler = (unsigned32) 0xDEADDEAD;
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  }
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#endif /* M68K_HAS_VBR */
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  _CPU_Table = *cpu_table;
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}
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/*PAGE
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 *
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 *  _CPU_ISR_Get_level
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 */
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unsigned32 _CPU_ISR_Get_level( void )
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{
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  unsigned32 level;
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  m68k_get_interrupt_level( level );
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  return level;
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}
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/*PAGE
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 *
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 *  _CPU_ISR_install_raw_handler
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 */
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void _CPU_ISR_install_raw_handler(
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  unsigned32  vector,
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  proc_ptr    new_handler,
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  proc_ptr   *old_handler
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)
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{
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  proc_ptr *interrupt_table = NULL;
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#if (M68K_HAS_FPSP_PACKAGE == 1)
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  /*
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   *  If this vector being installed is one related to FP, then the
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   *  FPSP will install the handler itself and handle it completely
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   *  with no intervention from RTEMS.
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   */
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  if (*_FPSP_install_raw_handler &&
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      (*_FPSP_install_raw_handler)(vector, new_handler, *old_handler))
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        return;
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#endif
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  /*
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   *  On CPU models without a VBR, it is necessary for there to be some
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   *  header code for each ISR which saves a register, loads the vector
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   *  number, and jumps to _ISR_Handler.
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   */
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  m68k_get_vbr( interrupt_table );
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  *old_handler = interrupt_table[ vector ];
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#if ( M68K_HAS_VBR == 1 )
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  interrupt_table[ vector ] = new_handler;
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#else
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  _CPU_ISR_jump_table[vector].isr_handler = (unsigned32) new_handler;
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  interrupt_table[ vector ] = (proc_ptr) &_CPU_ISR_jump_table[vector];
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#endif /* M68K_HAS_VBR */
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}
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/*PAGE
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 *
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 *  _CPU_ISR_install_vector
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 *
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 *  This kernel routine installs the RTEMS handler for the
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 *  specified vector.
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 *
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 *  Input parameters:
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 *    vector      - interrupt vector number
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 *    new_handler - replacement ISR for this vector number
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 *    old_handler - former ISR for this vector number
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 *
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 *  Output parameters:  NONE
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 */
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void _CPU_ISR_install_vector(
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  unsigned32  vector,
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  proc_ptr    new_handler,
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  proc_ptr   *old_handler
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)
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{
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  proc_ptr ignored;
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  *old_handler = _ISR_Vector_table[ vector ];
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  _CPU_ISR_install_raw_handler( vector, _ISR_Handler, &ignored );
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  _ISR_Vector_table[ vector ] = new_handler;
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}
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/*PAGE
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 *
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 *  _CPU_Install_interrupt_stack
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 */
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void _CPU_Install_interrupt_stack( void )
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{
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#if ( M68K_HAS_SEPARATE_STACKS == 1 )
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  void *isp = _CPU_Interrupt_stack_high;
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  asm volatile ( "movec %0,%%isp" : "=r" (isp) : "0" (isp) );
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#endif
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}
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#if ( M68K_HAS_BFFFO != 1 )
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/*
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 * Returns table for duplication of the BFFFO instruction (16 bits only)
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 */
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const unsigned char __BFFFOtable[256] = {
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    8, 7, 6, 6, 5, 5, 5, 5, 4, 4, 4, 4, 4, 4, 4, 4,
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    3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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    2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
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    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
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    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
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};
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#endif
175
 
176
/*PAGE
177
 *
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 *  The following code context switches the software FPU emulation
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 *  code provided with GCC.
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 */
181
 
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#if (CPU_SOFTWARE_FP == TRUE)
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extern Context_Control_fp _fpCCR;
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void CPU_Context_save_fp (void **fp_context_ptr)
186
{
187
  Context_Control_fp *fp;
188
 
189
  fp = (Context_Control_fp *) *fp_context_ptr;
190
 
191
  *fp = _fpCCR;
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}
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194
void CPU_Context_restore_fp (void **fp_context_ptr)
195
{
196
  Context_Control_fp *fp;
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198
  fp = (Context_Control_fp *) *fp_context_ptr;
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200
  _fpCCR = *fp;
201
}
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#endif
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