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/*  cpu_asm.s
 *
 *  This file contains all assembly code for the MC68020 implementation
 *  of RTEMS.
 *
 *  COPYRIGHT (c) 1989-1999.
 *  On-Line Applications Research Corporation (OAR).
 *
 *  The license and distribution terms for this file may be
 *  found in the file LICENSE in this distribution or at
 *  http://www.OARcorp.com/rtems/license.html.
 *
 *  $Id: cpu_asm.S,v 1.2 2001-09-27 11:59:28 chris Exp $
 */
 
 
#include 
 
        .text
 
/*  void _CPU_Context_switch( run_context, heir_context )
 *
 *  This routine performs a normal non-FP context.
 */
 
        .align  4
        .global SYM (_CPU_Context_switch)
 
.set RUNCONTEXT_ARG,   4                   | save context argument
.set HEIRCONTEXT_ARG,  8                   | restore context argument
 
SYM (_CPU_Context_switch):
          moval    a7@(RUNCONTEXT_ARG),a0| a0 = running thread context
          movw     sr,d1                 | d1 = status register
          movml    d1-d7/a2-a7,a0@       | save context
 
          moval    a7@(HEIRCONTEXT_ARG),a0| a0 = heir thread context
restore:  movml    a0@,d1-d7/a2-a7     | restore context
          movw     d1,sr                  | restore status register
          rts
 
/*PAGE
 *  void __CPU_Context_save_fp_context( &fp_context_ptr )
 *  void __CPU_Context_restore_fp_context( &fp_context_ptr )
 *
 *  These routines are used to context switch a MC68881 or MC68882.
 *
 *  NOTE:  Context save and restore code is based upon the code shown
 *         on page 6-38 of the MC68881/68882 Users Manual (rev 1).
 *
 *         CPU_FP_CONTEXT_SIZE is higher than expected to account for the
 *         -1 pushed at end of this sequence.
 *
 *         Neither of these entries is required if we have software FPU
 *         emulation.  But if we don't have an FPU or emulation, then
 *         we need the stub versions of these routines.
 */
 
#if (CPU_SOFTWARE_FP == FALSE)
 
.set FPCONTEXT_ARG,   4                    | save FP context argument
 
        .align  4
        .global SYM (_CPU_Context_save_fp)
SYM (_CPU_Context_save_fp):
#if ( M68K_HAS_FPU == 1 )
        moval    a7@(FPCONTEXT_ARG),a1    | a1 = &ptr to context area
        moval    a1@,a0                   | a0 = Save context area
        fsave    a0@-                     | save 68881/68882 state frame
        tstb     a0@                      | check for a null frame
        beq      nosv                     | Yes, skip save of user model
        fmovem   fp0-fp7,a0@-             | save data registers (fp0-fp7)
        fmovem   fpc/fps/fpi,a0@-         | and save control registers
        movl     #-1,a0@-                 | place not-null flag on stack
nosv:   movl     a0,a1@                   | save pointer to saved context
#endif
        rts
 
        .align  4
        .global SYM (_CPU_Context_restore_fp)
SYM (_CPU_Context_restore_fp):
#if ( M68K_HAS_FPU == 1 )
        moval    a7@(FPCONTEXT_ARG),a1    | a1 = &ptr to context area
        moval    a1@,a0                   | a0 = address of saved context
        tstb     a0@                      | Null context frame?
        beq      norst                    | Yes, skip fp restore
        addql    #4,a0                    | throwaway non-null flag
        fmovem   a0@+,fpc/fps/fpi         | restore control registers
        fmovem   a0@+,fp0-fp7             | restore data regs (fp0-fp7)
norst:  frestore a0@+                     | restore the fp state frame
        movl     a0,a1@                   | save pointer to saved context
#endif
        rts
#endif
 
/*PAGE
 *  void _ISR_Handler()
 *
 *  This routine provides the RTEMS interrupt management.
 *
 *  NOTE:
 *    Upon entry, the master stack will contain an interrupt stack frame
 *    back to the interrupted thread and the interrupt stack will contain
 *    a throwaway interrupt stack frame.  If dispatching is enabled, this
 *    is the outer most interrupt, and (a context switch is necessary or
 *    the current thread has signals), then set up the master stack to
 *    transfer control to the interrupt dispatcher.
 */
 
/*
 *  With this approach, lower priority interrupts may
 *  execute twice if a higher priority interrupt is
 *  acknowledged before _Thread_Dispatch_disable is
 *  incremented and the higher priority interrupt
 *  performs a context switch after executing. The lower
 *  priority interrupt will execute (1) at the end of the
 *  higher priority interrupt in the new context if
 *  permitted by the new interrupt level mask, and (2) when
 *  the original context regains the cpu.
 */
 
#if ( M68K_COLDFIRE_ARCH == 1 )
.set SR_OFFSET,    2                     | Status register offset
.set PC_OFFSET,    4                     | Program Counter offset
.set FVO_OFFSET,   0                     | Format/vector offset
#elif ( M68K_HAS_VBR == 1)
.set SR_OFFSET,    0                     | Status register offset
.set PC_OFFSET,    2                     | Program Counter offset
.set FVO_OFFSET,   6                     | Format/vector offset
#else
.set SR_OFFSET,    2                     | Status register offset
.set PC_OFFSET,    4                     | Program Counter offset
.set FVO_OFFSET,   0                     | Format/vector offset placed in the stack
#endif /* M68K_HAS_VBR */
 
.set SAVED,        16                    | space for saved registers
 
        .align  4
        .global SYM (_ISR_Handler)
 
SYM (_ISR_Handler):
        addql   #1,SYM (_Thread_Dispatch_disable_level) | disable multitasking
#if ( M68K_COLDFIRE_ARCH == 0 )
        moveml  d0-d1/a0-a1,a7@-         | save d0-d1,a0-a1
        movew   a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO
        andl    #0x0fff,d0               | d0 = vector offset in vbr
#else
        lea     a7@(-SAVED),a7
        movm.l  d0-d1/a0-a1,a7@          | save d0-d1,a0-a1
        movew   a7@(SAVED+FVO_OFFSET),d0 | d0 = F/VO
        andl    #0x0ffc,d0               | d0 = vector offset in vbr
#endif
 
 
#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
  #if ( M68K_COLDFIRE_ARCH == 0 )
        movew   sr,d1                   | Save status register
        oriw    #0x700,sr               | Disable interrupts
  #else
        move.l  d0,a7@-                 | Save d0 value
        move.l  #0x700,d0               | Load in disable ints value
        move.w  sr,d1                   | Grab SR
        or.l    d1,d0                   | Create new SR
        move.w  d0,sr                   | Disable interrupts
        move.l  a7@+,d0                 | Restore d0 value
  #endif
 
        tstl    SYM (_ISR_Nest_level)   | Interrupting an interrupt handler?
        bne     1f                      | Yes, just skip over stack switch code
        movel   SYM(_CPU_Interrupt_stack_high),a0       | End of interrupt stack
        movel   a7,a0@-                 | Save task stack pointer
        movel   a0,a7                   | Switch to interrupt stack
1:
        addql   #1,SYM(_ISR_Nest_level) | one nest level deeper
        movew   d1,sr                   | Restore status register
#else
        addql   #1,SYM (_ISR_Nest_level) | one nest level deeper
#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
 
#if ( M68K_HAS_PREINDEXING == 1 )
        movel   @( SYM (_ISR_Vector_table),d0:w:1),a0| fetch the ISR
#else
        movel   # SYM (_ISR_Vector_table),a0   | a0 = base of RTEMS table
        addal   d0,a0                    | a0 = address of vector
        movel   (a0),a0                  | a0 = address of user routine
#endif
 
        lsrl    #2,d0                    | d0 = vector number
        movel   d0,a7@-                  | push vector number
        jbsr    a0@                      | invoke the user ISR
        addql   #4,a7                    | remove vector number
 
#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )
  #if ( M68K_COLDFIRE_ARCH == 0 )
        movew   sr,d0                   | Save status register
        oriw    #0x700,sr               | Disable interrupts
  #else
        move.l  #0x700,d1               | Load in disable int value
        move.w  sr,d0                   | Grab SR
        or.l    d0,d1                   | Create new SR
        move.w  d1,sr                   | Load to disable interrupts
  #endif
 
        subql   #1,SYM(_ISR_Nest_level) | Reduce interrupt-nesting count
        bne     1f                      | Skip if return to interrupt
        movel   (a7),a7                 | Restore task stack pointer
1:
        movew   d0,sr                   | Restore status register
#else
        subql   #1,SYM (_ISR_Nest_level) | one less nest level
#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */
 
        subql   #1,SYM (_Thread_Dispatch_disable_level)
                                         | unnest multitasking
        bne     exit                     | If dispatch disabled, exit
 
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
        movew   #0xf000,d0               | isolate format nibble
        andw    a7@(SAVED+FVO_OFFSET),d0 | get F/VO
        cmpiw   #0x1000,d0               | is it a throwaway isf?
        bne     exit                     | NOT outer level, so branch
#endif
 
        tstl    SYM (_Context_Switch_necessary)
                                         | Is thread switch necessary?
        bne     bframe                   | Yes, invoke dispatcher
 
        tstl    SYM (_ISR_Signals_to_thread_executing)
                                         | signals sent to Run_thread
                                         |   while in interrupt handler?
        beq     exit                     | No, then exit
 
 
bframe: clrl    SYM (_ISR_Signals_to_thread_executing)
                                         | If sent, will be processed
#if ( M68K_HAS_SEPARATE_STACKS == 1 )
        movec   msp,a0                   | a0 = master stack pointer
        movew   #0,a0@-                  | push format word
        movel   #SYM(_ISR_Dispatch),a0@- | push return addr
        movew   a0@(6),a0@-              | push saved sr
        movec   a0,msp                   | set master stack pointer
#else
        jsr SYM (_Thread_Dispatch)       | Perform context switch
#endif
 
#if ( M68K_COLDFIRE_ARCH == 0 )
exit:   moveml  a7@+,d0-d1/a0-a1         | restore d0-d1,a0-a1
#else
exit:   moveml  a7@,d0-d1/a0-a1          | restore d0-d1,a0-a1
        lea     a7@(SAVED),a7
#endif
 
#if ( M68K_HAS_VBR == 0 )
        addql   #2,a7                    | pop format/id
#endif /* M68K_HAS_VBR */
        rte                              | return to thread
                                         |   OR _Isr_dispatch
 
/*PAGE
 *  void _ISR_Dispatch()
 *
 *  Entry point from the outermost interrupt service routine exit.
 *  The current stack is the supervisor mode stack if this processor
 *  has separate stacks.
 *
 *    1.  save all registers not preserved across C calls.
 *    2.  invoke the _Thread_Dispatch routine to switch tasks
 *        or a signal to the currently executing task.
 *    3.  restore all registers not preserved across C calls.
 *    4.  return from interrupt
 */
 
        .global SYM (_ISR_Dispatch)
SYM (_ISR_Dispatch):
#if ( M68K_COLDFIRE_ARCH == 0 )
        movml   d0-d1/a0-a1,a7@-
        jsr     SYM (_Thread_Dispatch)
        movml   a7@+,d0-d1/a0-a1
#else
        lea     a7@(-SAVED),a7
        movml   d0-d1/a0-a1,a7@
        jsr     SYM (_Thread_Dispatch)
        movml   a7@,d0-d1/a0-a1
        lea     a7@(SAVED),a7
#endif
 
#if ( M68K_HAS_VBR == 0 )
        addql   #2,a7                    | pop format/id
#endif /* M68K_HAS_VBR */
        rte

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[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [m68k/] [cpu_asm.S] - Blame information for rev 389

Line No.	Rev	Author	Line
1	30	unneback	`/* cpu_asm.s`
2			`*`
3			`* This file contains all assembly code for the MC68020 implementation`
4			`* of RTEMS.`
5			`*`
6			`* COPYRIGHT (c) 1989-1999.`
7			`* On-Line Applications Research Corporation (OAR).`
8			`*`
9			`* The license and distribution terms for this file may be`
10			`* found in the file LICENSE in this distribution or at`
11			`* http://www.OARcorp.com/rtems/license.html.`
12			`*`
13			`* $Id: cpu_asm.S,v 1.2 2001-09-27 11:59:28 chris Exp $`
14			`*/`
15
16
17			`#include`
18
19			`.text`
20
21			`/* void _CPU_Context_switch( run_context, heir_context )`
22			`*`
23			`* This routine performs a normal non-FP context.`
24			`*/`
25
26			`.align 4`
27			`.global SYM (_CPU_Context_switch)`
28
29			`.set RUNCONTEXT_ARG, 4 \| save context argument`
30			`.set HEIRCONTEXT_ARG, 8 \| restore context argument`
31
32			`SYM (_CPU_Context_switch):`
33			`moval a7@(RUNCONTEXT_ARG),a0\| a0 = running thread context`
34			`movw sr,d1 \| d1 = status register`
35			`movml d1-d7/a2-a7,a0@ \| save context`
36
37			`moval a7@(HEIRCONTEXT_ARG),a0\| a0 = heir thread context`
38			`restore: movml a0@,d1-d7/a2-a7 \| restore context`
39			`movw d1,sr \| restore status register`
40			`rts`
41
42			`/*PAGE`
43			`* void __CPU_Context_save_fp_context( &fp_context_ptr )`
44			`* void __CPU_Context_restore_fp_context( &fp_context_ptr )`
45			`*`
46			`* These routines are used to context switch a MC68881 or MC68882.`
47			`*`
48			`* NOTE: Context save and restore code is based upon the code shown`
49			`* on page 6-38 of the MC68881/68882 Users Manual (rev 1).`
50			`*`
51			`* CPU_FP_CONTEXT_SIZE is higher than expected to account for the`
52			`* -1 pushed at end of this sequence.`
53			`*`
54			`* Neither of these entries is required if we have software FPU`
55			`* emulation. But if we don't have an FPU or emulation, then`
56			`* we need the stub versions of these routines.`
57			`*/`
58
59			`#if (CPU_SOFTWARE_FP == FALSE)`
60
61			`.set FPCONTEXT_ARG, 4 \| save FP context argument`
62
63			`.align 4`
64			`.global SYM (_CPU_Context_save_fp)`
65			`SYM (_CPU_Context_save_fp):`
66			`#if ( M68K_HAS_FPU == 1 )`
67			`moval a7@(FPCONTEXT_ARG),a1 \| a1 = &ptr to context area`
68			`moval a1@,a0 \| a0 = Save context area`
69			`fsave a0@- \| save 68881/68882 state frame`
70			`tstb a0@ \| check for a null frame`
71			`beq nosv \| Yes, skip save of user model`
72			`fmovem fp0-fp7,a0@- \| save data registers (fp0-fp7)`
73			`fmovem fpc/fps/fpi,a0@- \| and save control registers`
74			`movl #-1,a0@- \| place not-null flag on stack`
75			`nosv: movl a0,a1@ \| save pointer to saved context`
76			`#endif`
77			`rts`
78
79			`.align 4`
80			`.global SYM (_CPU_Context_restore_fp)`
81			`SYM (_CPU_Context_restore_fp):`
82			`#if ( M68K_HAS_FPU == 1 )`
83			`moval a7@(FPCONTEXT_ARG),a1 \| a1 = &ptr to context area`
84			`moval a1@,a0 \| a0 = address of saved context`
85			`tstb a0@ \| Null context frame?`
86			`beq norst \| Yes, skip fp restore`
87			`addql #4,a0 \| throwaway non-null flag`
88			`fmovem a0@+,fpc/fps/fpi \| restore control registers`
89			`fmovem a0@+,fp0-fp7 \| restore data regs (fp0-fp7)`
90			`norst: frestore a0@+ \| restore the fp state frame`
91			`movl a0,a1@ \| save pointer to saved context`
92			`#endif`
93			`rts`
94			`#endif`
95
96			`/*PAGE`
97			`* void _ISR_Handler()`
98			`*`
99			`* This routine provides the RTEMS interrupt management.`
100			`*`
101			`* NOTE:`
102			`* Upon entry, the master stack will contain an interrupt stack frame`
103			`* back to the interrupted thread and the interrupt stack will contain`
104			`* a throwaway interrupt stack frame. If dispatching is enabled, this`
105			`* is the outer most interrupt, and (a context switch is necessary or`
106			`* the current thread has signals), then set up the master stack to`
107			`* transfer control to the interrupt dispatcher.`
108			`*/`
109
110			`/*`
111			`* With this approach, lower priority interrupts may`
112			`* execute twice if a higher priority interrupt is`
113			`* acknowledged before _Thread_Dispatch_disable is`
114			`* incremented and the higher priority interrupt`
115			`* performs a context switch after executing. The lower`
116			`* priority interrupt will execute (1) at the end of the`
117			`* higher priority interrupt in the new context if`
118			`* permitted by the new interrupt level mask, and (2) when`
119			`* the original context regains the cpu.`
120			`*/`
121
122			`#if ( M68K_COLDFIRE_ARCH == 1 )`
123			`.set SR_OFFSET, 2 \| Status register offset`
124			`.set PC_OFFSET, 4 \| Program Counter offset`
125			`.set FVO_OFFSET, 0 \| Format/vector offset`
126			`#elif ( M68K_HAS_VBR == 1)`
127			`.set SR_OFFSET, 0 \| Status register offset`
128			`.set PC_OFFSET, 2 \| Program Counter offset`
129			`.set FVO_OFFSET, 6 \| Format/vector offset`
130			`#else`
131			`.set SR_OFFSET, 2 \| Status register offset`
132			`.set PC_OFFSET, 4 \| Program Counter offset`
133			`.set FVO_OFFSET, 0 \| Format/vector offset placed in the stack`
134			`#endif /* M68K_HAS_VBR */`
135
136			`.set SAVED, 16 \| space for saved registers`
137
138			`.align 4`
139			`.global SYM (_ISR_Handler)`
140
141			`SYM (_ISR_Handler):`
142			`addql #1,SYM (_Thread_Dispatch_disable_level) \| disable multitasking`
143			`#if ( M68K_COLDFIRE_ARCH == 0 )`
144			`moveml d0-d1/a0-a1,a7@- \| save d0-d1,a0-a1`
145			`movew a7@(SAVED+FVO_OFFSET),d0 \| d0 = F/VO`
146			`andl #0x0fff,d0 \| d0 = vector offset in vbr`
147			`#else`
148			`lea a7@(-SAVED),a7`
149			`movm.l d0-d1/a0-a1,a7@ \| save d0-d1,a0-a1`
150			`movew a7@(SAVED+FVO_OFFSET),d0 \| d0 = F/VO`
151			`andl #0x0ffc,d0 \| d0 = vector offset in vbr`
152			`#endif`
153
154
155			`#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )`
156			`#if ( M68K_COLDFIRE_ARCH == 0 )`
157			`movew sr,d1 \| Save status register`
158			`oriw #0x700,sr \| Disable interrupts`
159			`#else`
160			`move.l d0,a7@- \| Save d0 value`
161			`move.l #0x700,d0 \| Load in disable ints value`
162			`move.w sr,d1 \| Grab SR`
163			`or.l d1,d0 \| Create new SR`
164			`move.w d0,sr \| Disable interrupts`
165			`move.l a7@+,d0 \| Restore d0 value`
166			`#endif`
167
168			`tstl SYM (_ISR_Nest_level) \| Interrupting an interrupt handler?`
169			`bne 1f \| Yes, just skip over stack switch code`
170			`movel SYM(_CPU_Interrupt_stack_high),a0 \| End of interrupt stack`
171			`movel a7,a0@- \| Save task stack pointer`
172			`movel a0,a7 \| Switch to interrupt stack`
173			`1:`
174			`addql #1,SYM(_ISR_Nest_level) \| one nest level deeper`
175			`movew d1,sr \| Restore status register`
176			`#else`
177			`addql #1,SYM (_ISR_Nest_level) \| one nest level deeper`
178			`#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */`
179
180			`#if ( M68K_HAS_PREINDEXING == 1 )`
181			`movel @( SYM (_ISR_Vector_table),d0:w:1),a0\| fetch the ISR`
182			`#else`
183			`movel # SYM (_ISR_Vector_table),a0 \| a0 = base of RTEMS table`
184			`addal d0,a0 \| a0 = address of vector`
185			`movel (a0),a0 \| a0 = address of user routine`
186			`#endif`
187
188			`lsrl #2,d0 \| d0 = vector number`
189			`movel d0,a7@- \| push vector number`
190			`jbsr a0@ \| invoke the user ISR`
191			`addql #4,a7 \| remove vector number`
192
193			`#if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 )`
194			`#if ( M68K_COLDFIRE_ARCH == 0 )`
195			`movew sr,d0 \| Save status register`
196			`oriw #0x700,sr \| Disable interrupts`
197			`#else`
198			`move.l #0x700,d1 \| Load in disable int value`
199			`move.w sr,d0 \| Grab SR`
200			`or.l d0,d1 \| Create new SR`
201			`move.w d1,sr \| Load to disable interrupts`
202			`#endif`
203
204			`subql #1,SYM(_ISR_Nest_level) \| Reduce interrupt-nesting count`
205			`bne 1f \| Skip if return to interrupt`
206			`movel (a7),a7 \| Restore task stack pointer`
207			`1:`
208			`movew d0,sr \| Restore status register`
209			`#else`
210			`subql #1,SYM (_ISR_Nest_level) \| one less nest level`
211			`#endif /* CPU_HAS_SOFTWARE_INTERRUPT_STACK == 1 */`
212
213			`subql #1,SYM (_Thread_Dispatch_disable_level)`
214			`\| unnest multitasking`
215			`bne exit \| If dispatch disabled, exit`
216
217			`#if ( M68K_HAS_SEPARATE_STACKS == 1 )`
218			`movew #0xf000,d0 \| isolate format nibble`
219			`andw a7@(SAVED+FVO_OFFSET),d0 \| get F/VO`
220			`cmpiw #0x1000,d0 \| is it a throwaway isf?`
221			`bne exit \| NOT outer level, so branch`
222			`#endif`
223
224			`tstl SYM (_Context_Switch_necessary)`
225			`\| Is thread switch necessary?`
226			`bne bframe \| Yes, invoke dispatcher`
227
228			`tstl SYM (_ISR_Signals_to_thread_executing)`
229			`\| signals sent to Run_thread`
230			`\| while in interrupt handler?`
231			`beq exit \| No, then exit`
232
233
234			`bframe: clrl SYM (_ISR_Signals_to_thread_executing)`
235			`\| If sent, will be processed`
236			`#if ( M68K_HAS_SEPARATE_STACKS == 1 )`
237			`movec msp,a0 \| a0 = master stack pointer`
238			`movew #0,a0@- \| push format word`
239			`movel #SYM(_ISR_Dispatch),a0@- \| push return addr`
240			`movew a0@(6),a0@- \| push saved sr`
241			`movec a0,msp \| set master stack pointer`
242			`#else`
243			`jsr SYM (_Thread_Dispatch) \| Perform context switch`
244			`#endif`
245
246			`#if ( M68K_COLDFIRE_ARCH == 0 )`
247			`exit: moveml a7@+,d0-d1/a0-a1 \| restore d0-d1,a0-a1`
248			`#else`
249			`exit: moveml a7@,d0-d1/a0-a1 \| restore d0-d1,a0-a1`
250			`lea a7@(SAVED),a7`
251			`#endif`
252
253			`#if ( M68K_HAS_VBR == 0 )`
254			`addql #2,a7 \| pop format/id`
255			`#endif /* M68K_HAS_VBR */`
256			`rte \| return to thread`
257			`\| OR _Isr_dispatch`
258
259			`/*PAGE`
260			`* void _ISR_Dispatch()`
261			`*`
262			`* Entry point from the outermost interrupt service routine exit.`
263			`* The current stack is the supervisor mode stack if this processor`
264			`* has separate stacks.`
265			`*`
266			`* 1. save all registers not preserved across C calls.`
267			`* 2. invoke the _Thread_Dispatch routine to switch tasks`
268			`* or a signal to the currently executing task.`
269			`* 3. restore all registers not preserved across C calls.`
270			`* 4. return from interrupt`
271			`*/`
272
273			`.global SYM (_ISR_Dispatch)`
274			`SYM (_ISR_Dispatch):`
275			`#if ( M68K_COLDFIRE_ARCH == 0 )`
276			`movml d0-d1/a0-a1,a7@-`
277			`jsr SYM (_Thread_Dispatch)`
278			`movml a7@+,d0-d1/a0-a1`
279			`#else`
280			`lea a7@(-SAVED),a7`
281			`movml d0-d1/a0-a1,a7@`
282			`jsr SYM (_Thread_Dispatch)`
283			`movml a7@,d0-d1/a0-a1`
284			`lea a7@(SAVED),a7`
285			`#endif`
286
287			`#if ( M68K_HAS_VBR == 0 )`
288			`addql #2,a7 \| pop format/id`
289			`#endif /* M68K_HAS_VBR */`
290			`rte`