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/* m68k.h
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*
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* This include file contains information pertaining to the Motorola
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* m68xxx processor family.
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*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* $Id: m68k.h,v 1.2 2001-09-27 11:59:28 chris Exp $
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*/
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#ifndef __M68k_h
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#define __M68k_h
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* This section contains the information required to build
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* RTEMS for a particular member of the Motorola MC68xxx
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* family. It does this by setting variables to indicate
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* which implementation dependent features are present in
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* a particular member of the family.
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*
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* Currently recognized:
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* -m68000
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* -m68000 -msoft-float
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* -m68020
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* -m68020 -msoft-float
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* -m68030
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* -m68040 -msoft-float
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* -m68040
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* -m68040 -msoft-float
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* -m68060
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* -m68060 -msoft-float
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* -m68302 (no FP) (deprecated, use -m68000)
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* -m68332 (no FP) (deprecated, use -mcpu32)
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* -mcpu32 (no FP)
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* -m5200 (no FP)
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*
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* As of gcc 2.8.1 and egcs 1.1, there is no distinction made between
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* the CPU32 and CPU32+. The option -mcpu32 generates code which can
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* be run on either core. RTEMS distinguishes between these two cores
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* because they have different alignment rules which impact performance.
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* If you are using a CPU32+, then the symbol RTEMS__mcpu32p__ should
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* be defined in your custom file (see make/custom/gen68360.cfg for an
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* example of how to do this. If gcc ever distinguishes between these
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* two cores, then RTEMS__mcpu32p__ usage will be replaced with the
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* appropriate compiler defined predefine.
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*
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* Here is some information on the 040 variants (courtesy of Doug McBride,
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* mcbride@rodin.colorado.edu):
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*
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* "The 68040 is a superset of the 68EC040 and the 68LC040. The
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* 68EC040 and 68LC040 do not have FPU's. The 68LC040 and the
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* 68EC040 have renamed the DLE pin as JS0 which must be tied to
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* Gnd or Vcc. The 68EC040 has renamed the MDIS pin as JS1. The
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* 68EC040 has access control units instead of memory management units.
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* The 68EC040 should not have the PFLUSH or PTEST instructions executed
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* (cause an indeterminate result). The 68EC040 and 68LC040 do not
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* implement the DLE or multiplexed bus modes. The 68EC040 does not
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* implement the output buffer impedance selection mode of operation."
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*
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* M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction
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* which is not available for 68000 or 68ec000 cores (68000, 68001, 68008,
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* 68010, 68302, 68306, 68307). This instruction is available on the 68020
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* up and the cpu32 based models.
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*
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* M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned
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* data access (68020, 68030, 68040, 68060, CPU32+).
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*
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* NOTE:
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* Eventually it would be nice to evaluate doing a lot of this section
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* by having each model specify which core it uses and then go from there.
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*/
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/*
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* Figure out all CPU Model Feature Flags based upon compiler
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* predefines. Notice the only exception to this is that
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* gcc does not distinguish between CPU32 and CPU32+. This
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* feature selection logic is setup such that if RTEMS__mcpu32p__
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* is defined, then CPU32+ rules are used. Otherwise, the safe
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* but less efficient CPU32 rules are used for the CPU32+.
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*/
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#if defined(__mc68020__)
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#define CPU_MODEL_NAME "m68020"
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#define M68K_HAS_VBR 1
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#define M68K_HAS_SEPARATE_STACKS 1
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#define M68K_HAS_BFFFO 1
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#define M68K_HAS_PREINDEXING 1
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#define M68K_HAS_EXTB_L 1
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#define M68K_HAS_MISALIGNED 1
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# if defined (__HAVE_68881__)
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# define M68K_HAS_FPU 1
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# define M68K_HAS_FPSP_PACKAGE 0
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# else
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# define M68K_HAS_FPU 0
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# define M68K_HAS_FPSP_PACKAGE 0
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# endif
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#elif defined(__mc68030__)
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#define CPU_MODEL_NAME "m68030"
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#define M68K_HAS_VBR 1
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#define M68K_HAS_SEPARATE_STACKS 1
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#define M68K_HAS_BFFFO 1
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#define M68K_HAS_PREINDEXING 1
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#define M68K_HAS_EXTB_L 1
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#define M68K_HAS_MISALIGNED 1
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# if defined (__HAVE_68881__)
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# define M68K_HAS_FPU 1
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# define M68K_HAS_FPSP_PACKAGE 0
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# else
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# define M68K_HAS_FPU 0
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# define M68K_HAS_FPSP_PACKAGE 0
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# endif
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#elif defined(__mc68040__)
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#define CPU_MODEL_NAME "m68040"
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#define M68K_HAS_VBR 1
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#define M68K_HAS_SEPARATE_STACKS 1
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#define M68K_HAS_BFFFO 1
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#define M68K_HAS_PREINDEXING 1
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#define M68K_HAS_EXTB_L 1
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#define M68K_HAS_MISALIGNED 1
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# if defined (__HAVE_68881__)
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# define M68K_HAS_FPU 1
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# define M68K_HAS_FPSP_PACKAGE 1
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# else
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# define M68K_HAS_FPU 0
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# define M68K_HAS_FPSP_PACKAGE 0
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# endif
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#elif defined(__mc68060__)
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#define CPU_MODEL_NAME "m68060"
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#define M68K_HAS_VBR 1
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#define M68K_HAS_SEPARATE_STACKS 0
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#define M68K_HAS_BFFFO 1
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#define M68K_HAS_PREINDEXING 1
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#define M68K_HAS_EXTB_L 1
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#define M68K_HAS_MISALIGNED 1
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# if defined (__HAVE_68881__)
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# define M68K_HAS_FPU 1
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# define M68K_HAS_FPSP_PACKAGE 1
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# else
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# define M68K_HAS_FPU 0
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# define M68K_HAS_FPSP_PACKAGE 0
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# endif
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#elif defined(__mc68302__)
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#define CPU_MODEL_NAME "m68302"
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#define M68K_HAS_VBR 0
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#define M68K_HAS_SEPARATE_STACKS 0
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#define M68K_HAS_BFFFO 0
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#define M68K_HAS_PREINDEXING 0
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#define M68K_HAS_EXTB_L 0
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#define M68K_HAS_MISALIGNED 0
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#define M68K_HAS_FPU 0
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#define M68K_HAS_FPSP_PACKAGE 0
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/* gcc and egcs do not distinguish between CPU32 and CPU32+ */
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#elif defined(RTEMS__mcpu32p__)
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#define CPU_MODEL_NAME "mcpu32+"
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#define M68K_HAS_VBR 1
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#define M68K_HAS_SEPARATE_STACKS 0
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#define M68K_HAS_BFFFO 0
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#define M68K_HAS_PREINDEXING 1
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#define M68K_HAS_EXTB_L 1
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#define M68K_HAS_MISALIGNED 1
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#define M68K_HAS_FPU 0
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#define M68K_HAS_FPSP_PACKAGE 0
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#elif defined(__mcpu32__)
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#define CPU_MODEL_NAME "mcpu32"
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#define M68K_HAS_VBR 1
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#define M68K_HAS_SEPARATE_STACKS 0
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#define M68K_HAS_BFFFO 0
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#define M68K_HAS_PREINDEXING 1
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#define M68K_HAS_EXTB_L 1
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#define M68K_HAS_MISALIGNED 0
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#define M68K_HAS_FPU 0
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#define M68K_HAS_FPSP_PACKAGE 0
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#elif defined(__mcf5200__)
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/* Motorola ColdFire V2 core - RISC/68020 hybrid */
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#define CPU_MODEL_NAME "m5200"
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#define M68K_HAS_VBR 1
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#define M68K_HAS_BFFFO 0
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#define M68K_HAS_SEPARATE_STACKS 0
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#define M68K_HAS_PREINDEXING 0
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#define M68K_HAS_EXTB_L 1
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#define M68K_HAS_MISALIGNED 1
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#define M68K_HAS_FPU 0
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#define M68K_HAS_FPSP_PACKAGE 0
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#define M68K_COLDFIRE_ARCH 1
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#elif defined(__mc68000__)
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#define CPU_MODEL_NAME "m68000"
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#define M68K_HAS_VBR 0
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#define M68K_HAS_SEPARATE_STACKS 0
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#define M68K_HAS_BFFFO 0
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#define M68K_HAS_PREINDEXING 0
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#define M68K_HAS_EXTB_L 0
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#define M68K_HAS_MISALIGNED 0
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# if defined (__HAVE_68881__)
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# define M68K_HAS_FPU 1
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# define M68K_HAS_FPSP_PACKAGE 0
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# else
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# define M68K_HAS_FPU 0
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# define M68K_HAS_FPSP_PACKAGE 0
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# endif
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#else
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#error "Unsupported CPU model -- are you sure you're running a 68k compiler?"
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#endif
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/*
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* If the above did not specify a ColdFire architecture, then set
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* this flag to indicate that it is not a ColdFire CPU.
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*/
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#if !defined(M68K_COLDFIRE_ARCH)
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#define M68K_COLDFIRE_ARCH 0
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#endif
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/*
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* Define the name of the CPU family.
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*/
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#if ( M68K_COLDFIRE_ARCH == 1 )
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#define CPU_NAME "Motorola ColdFire"
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#else
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#define CPU_NAME "Motorola MC68xxx"
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#endif
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#ifndef ASM
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#if ( M68K_COLDFIRE_ARCH == 1 )
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#define m68k_disable_interrupts( _level ) \
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do { register unsigned32 _tmpsr = 0x0700; \
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asm volatile ( "move.w %%sr,%0\n\t" \
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"or.l %0,%1\n\t" \
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"move.w %1,%%sr" \
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: "=d" (_level), "=d"(_tmpsr) : "1"(_tmpsr) ); \
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} while( 0 )
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#else
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#define m68k_disable_interrupts( _level ) \
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asm volatile ( "move.w %%sr,%0\n\t" \
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"or.w #0x0700,%%sr" \
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: "=d" (_level))
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#endif
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#define m68k_enable_interrupts( _level ) \
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asm volatile ( "move.w %0,%%sr " : : "d" (_level));
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#if ( M68K_COLDFIRE_ARCH == 1 )
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#define m68k_flash_interrupts( _level ) \
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do { register unsigned32 _tmpsr = 0x0700; \
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asm volatile ( "move.w %2,%%sr\n\t" \
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"or.l %2,%1\n\t" \
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"move.w %1,%%sr" \
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: "=d"(_tmpsr) : "0"(_tmpsr), "d"(_level) ); \
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} while( 0 )
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#else
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#define m68k_flash_interrupts( _level ) \
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asm volatile ( "move.w %0,%%sr\n\t" \
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"or.w #0x0700,%%sr" \
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: : "d" (_level))
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#endif
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| 285 |
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#define m68k_get_interrupt_level( _level ) \
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do { \
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register unsigned32 _tmpsr; \
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\
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asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
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_level = (_tmpsr & 0x0700) >> 8; \
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} while (0)
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| 293 |
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#define m68k_set_interrupt_level( _newlevel ) \
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do { \
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register unsigned32 _tmpsr; \
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\
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asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \
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_tmpsr = (_tmpsr & 0xf8ff) | ((_newlevel) << 8); \
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asm volatile( "move.w %0,%%sr" : : "d" (_tmpsr)); \
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} while (0)
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#if ( M68K_HAS_VBR == 1 && M68K_COLDFIRE_ARCH == 0 )
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#define m68k_get_vbr( vbr ) \
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asm volatile ( "movec %%vbr,%0 " : "=r" (vbr))
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#define m68k_set_vbr( vbr ) \
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asm volatile ( "movec %0,%%vbr " : : "r" (vbr))
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#elif ( M68K_COLDFIRE_ARCH == 1 )
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#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
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#define m68k_set_vbr( _vbr ) \
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asm volatile ("move.l %%a7,%%d1 \n\t" \
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"move.l %0,%%a7\n\t" \
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"movec %%a7,%%vbr\n\t" \
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| 316 |
|
|
"move.l %%d1,%%a7\n\t" \
|
| 317 |
|
|
: : "d" (_vbr) : "d1" );
|
| 318 |
|
|
|
| 319 |
|
|
#else
|
| 320 |
|
|
#define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR
|
| 321 |
|
|
#define m68k_set_vbr( _vbr )
|
| 322 |
|
|
#endif
|
| 323 |
|
|
|
| 324 |
|
|
/*
|
| 325 |
|
|
* The following routine swaps the endian format of an unsigned int.
|
| 326 |
|
|
* It must be static because it is referenced indirectly.
|
| 327 |
|
|
*/
|
| 328 |
|
|
|
| 329 |
|
|
static inline unsigned int m68k_swap_u32(
|
| 330 |
|
|
unsigned int value
|
| 331 |
|
|
)
|
| 332 |
|
|
{
|
| 333 |
|
|
unsigned int swapped = value;
|
| 334 |
|
|
|
| 335 |
|
|
asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) );
|
| 336 |
|
|
asm volatile( "swap %0" : "=d" (swapped) : "0" (swapped) );
|
| 337 |
|
|
asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) );
|
| 338 |
|
|
|
| 339 |
|
|
return( swapped );
|
| 340 |
|
|
}
|
| 341 |
|
|
|
| 342 |
|
|
static inline unsigned int m68k_swap_u16(
|
| 343 |
|
|
unsigned int value
|
| 344 |
|
|
)
|
| 345 |
|
|
{
|
| 346 |
|
|
unsigned short swapped = value;
|
| 347 |
|
|
|
| 348 |
|
|
asm volatile( "rorw #8,%0" : "=d" (swapped) : "0" (swapped) );
|
| 349 |
|
|
|
| 350 |
|
|
return( swapped );
|
| 351 |
|
|
}
|
| 352 |
|
|
|
| 353 |
|
|
/* XXX this is only valid for some m68k family members and should be fixed */
|
| 354 |
|
|
|
| 355 |
|
|
#define m68k_enable_caching() \
|
| 356 |
|
|
{ register unsigned32 _ctl=0x01; \
|
| 357 |
|
|
asm volatile ( "movec %0,%%cacr" \
|
| 358 |
|
|
: "=d" (_ctl) : "0" (_ctl) ); \
|
| 359 |
|
|
}
|
| 360 |
|
|
|
| 361 |
|
|
#define CPU_swap_u32( value ) m68k_swap_u32( value )
|
| 362 |
|
|
#define CPU_swap_u16( value ) m68k_swap_u16( value )
|
| 363 |
|
|
|
| 364 |
|
|
#endif /* !ASM */
|
| 365 |
|
|
|
| 366 |
|
|
#ifdef __cplusplus
|
| 367 |
|
|
}
|
| 368 |
|
|
#endif
|
| 369 |
|
|
|
| 370 |
|
|
#endif
|
| 371 |
|
|
/* end of include file */
|
