OpenCores
URL https://opencores.org/ocsvn/openrisc_me/openrisc_me/trunk

Subversion Repositories openrisc_me

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [mips64orion/] [cpu_asm.h] - Blame information for rev 173

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*
2
 *  cpu_asm.h
3
 *
4
 *  Author:     Craig Lebakken <craigl@transition.com>
5
 *
6
 *  COPYRIGHT (c) 1996 by Transition Networks Inc.
7
 *
8
 *  To anyone who acknowledges that this file is provided "AS IS"
9
 *  without any express or implied warranty:
10
 *      permission to use, copy, modify, and distribute this file
11
 *      for any purpose is hereby granted without fee, provided that
12
 *      the above copyright notice and this notice appears in all
13
 *      copies, and that the name of Transition Networks not be used in
14
 *      advertising or publicity pertaining to distribution of the
15
 *      software without specific, written prior permission.
16
 *      Transition Networks makes no representations about the suitability
17
 *      of this software for any purpose.
18
 *
19
 *  Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.h:
20
 *
21
 *  COPYRIGHT (c) 1989-1999.
22
 *  On-Line Applications Research Corporation (OAR).
23
 *
24
 *  The license and distribution terms for this file may be
25
 *  found in the file LICENSE in this distribution or at
26
 *  http://www.OARcorp.com/rtems/license.html.
27
 *
28
 *  $Id: cpu_asm.h,v 1.2 2001-09-27 11:59:28 chris Exp $
29
 *
30
 */
31
/* @(#)cpu_asm.h       08/20/96     1.2 */
32
 
33
#ifndef __CPU_ASM_h
34
#define __CPU_ASM_h
35
 
36
/* pull in the generated offsets */
37
 
38
/* #include <rtems/score/offsets.h> */
39
 
40
/*
41
 * Hardware General Registers
42
 */
43
 
44
/* put something here */
45
 
46
/*
47
 * Hardware Floating Point Registers
48
 */
49
 
50
#define R_FP0   0
51
#define R_FP1   1
52
#define R_FP2   2
53
#define R_FP3   3
54
#define R_FP4   4
55
#define R_FP5   5
56
#define R_FP6   6
57
#define R_FP7   7
58
#define R_FP8   8
59
#define R_FP9   9
60
#define R_FP10  10
61
#define R_FP11  11
62
#define R_FP12  12
63
#define R_FP13  13
64
#define R_FP14  14
65
#define R_FP15  15
66
#define R_FP16  16
67
#define R_FP17  17
68
#define R_FP18  18
69
#define R_FP19  19
70
#define R_FP20  20
71
#define R_FP21  21
72
#define R_FP22  22
73
#define R_FP23  23
74
#define R_FP24  24
75
#define R_FP25  25
76
#define R_FP26  26
77
#define R_FP27  27
78
#define R_FP28  28
79
#define R_FP29  29
80
#define R_FP30  30
81
#define R_FP31  31
82
 
83
/*
84
 * Hardware Control Registers
85
 */
86
 
87
/* put something here */
88
 
89
/*
90
 * Calling Convention
91
 */
92
 
93
/* put something here */
94
 
95
/*
96
 * Temporary registers
97
 */
98
 
99
/* put something here */
100
 
101
/*
102
 * Floating Point Registers - SW Conventions
103
 */
104
 
105
/* put something here */
106
 
107
/*
108
 * Temporary floating point registers
109
 */
110
 
111
/* put something here */
112
 
113
#endif
114
 
115
/* end of file */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.