OpenCores
URL https://opencores.org/ocsvn/openrisc/openrisc/trunk

Subversion Repositories openrisc

[/] [openrisc/] [trunk/] [rtos/] [rtems/] [c/] [src/] [exec/] [score/] [cpu/] [no_cpu/] [rtems/] [score/] [cpu_asm.h] - Blame information for rev 593

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 30 unneback
/*
2
 *  cpu_asm.h
3
 *
4
 *  Very loose template for an include file for the cpu_asm.? file
5
 *  if it is implemented as a ".S" file (preprocessed by cpp) instead
6
 *  of a ".s" file (preprocessed by gm4 or gasp).
7
 *
8
 *  COPYRIGHT (c) 1989-1999.
9
 *  On-Line Applications Research Corporation (OAR).
10
 *
11
 *  The license and distribution terms for this file may be
12
 *  found in the file LICENSE in this distribution or at
13
 *  http://www.OARcorp.com/rtems/license.html.
14
 *
15
 *  $Id: cpu_asm.h,v 1.2 2001-09-27 11:59:29 chris Exp $
16
 *
17
 */
18
 
19
#ifndef __CPU_ASM_h
20
#define __CPU_ASM_h
21
 
22
/* pull in the generated offsets */
23
 
24
#include <rtems/score/offsets.h>
25
 
26
/*
27
 * Hardware General Registers
28
 */
29
 
30
/* put something here */
31
 
32
/*
33
 * Hardware Floating Point Registers
34
 */
35
 
36
/* put something here */
37
 
38
/*
39
 * Hardware Control Registers
40
 */
41
 
42
/* put something here */
43
 
44
/*
45
 * Calling Convention
46
 */
47
 
48
/* put something here */
49
 
50
/*
51
 * Temporary registers
52
 */
53
 
54
/* put something here */
55
 
56
/*
57
 * Floating Point Registers - SW Conventions
58
 */
59
 
60
/* put something here */
61
 
62
/*
63
 * Temporary floating point registers
64
 */
65
 
66
/* put something here */
67
 
68
#endif
69
 
70
/* end of file */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.