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/*
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* Opencore Or1k CPU Dependent Source
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*
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*
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* COPYRIGHT (c) 1989-1999.
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* On-Line Applications Research Corporation (OAR).
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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*
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* This file adapted from no_bsp board library of the RTEMS distribution.
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* The body has been modified for the Bender Or1k implementation by
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* Chris Ziomkowski. <chris@asics.ws>
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*/
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#include <rtems/system.h>
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#include <rtems/score/isr.h>
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#include <rtems/score/wkspace.h>
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/* _CPU_Initialize
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*
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* This routine performs processor dependent initialization.
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*
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* INPUT PARAMETERS:
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* cpu_table - CPU table to initialize
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* thread_dispatch - address of disptaching routine
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*
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*/
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void _CPU_Initialize(
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rtems_cpu_table *cpu_table,
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void (*thread_dispatch)
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)
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{
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/*
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* The thread_dispatch argument is the address of the entry point
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* for the routine called at the end of an ISR once it has been
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* decided a context switch is necessary. On some compilation
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* systems it is difficult to call a high-level language routine
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* from assembly. This allows us to trick these systems.
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*
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* If you encounter this problem save the entry point in a CPU
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* dependent variable.
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*/
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_CPU_Thread_dispatch_pointer = thread_dispatch;
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/*
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* If there is not an easy way to initialize the FP context
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* during Context_Initialize, then it is usually easier to
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* save an "uninitialized" FP context here and copy it to
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* the task's during Context_Initialize.
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*/
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/* FP context initialization support goes here */
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_CPU_Table = *cpu_table;
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}
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/*PAGE
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*
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* _CPU_ISR_Get_level
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*
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* or1k Specific Information:
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*
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* There are only 2 interrupt levels for the or1k architecture.
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* Either interrupts are enabled or disabled. They are considered
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* enabled if both exceptions are enabled (SR_EXR) and interrupts
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* are enabled (SR_EIR). If either of these conditions are not
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* met, interrupts are disabled, and a level of 1 is returned.
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*/
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inline unsigned32 _CPU_ISR_Get_level( void )
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{
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register unsigned32 sr;
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asm("l.mfspr %0,r0,0x17" : "=r" (sr));
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return !((sr & SR_EXR) && (sr & SR_EIR));
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}
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/*PAGE
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*
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* _CPU_ISR_install_raw_handler
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*
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* or1k Specific Information:
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*
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* As a general rule the following is done for interrupts:
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*
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* For normal exceptions, exceptions are immediately reenabled
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* by setting the SR_EXR bit. For interrupt exceptions, the
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* SR_EIR bit is first cleared, and then exceptions are reenabled.
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*/
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void _CPU_ISR_install_raw_handler(
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unsigned32 vector,
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proc_ptr new_handler,
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proc_ptr *old_handler
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)
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{
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register unsigned32 sr;
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register unsigned32 tmp;
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extern unsigned32 Or1k_Interrupt_Vectors[];
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asm volatile ("l.mfspr %0,r0,0x11\n\t"
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"l.addi %1,r0,-5\n\t"
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"l.and %1,%1,%0\n\t": "=r" (sr) : "r" (tmp));
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*old_handler = *((proc_ptr*)&Or1k_Interrupt_Vectors[vector]);
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*((proc_ptr*)&Or1k_Interrupt_Vectors[vector]) = new_handler;
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asm volatile ("l.mtspr r0,%0,0x11\n\t":: "r" (sr));
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}
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/*PAGE
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*
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* _CPU_ISR_install_vector
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*
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* This kernel routine installs the RTEMS handler for the
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* specified vector.
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*
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* Input parameters:
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* vector - interrupt vector number
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* old_handler - former ISR for this vector number
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* new_handler - replacement ISR for this vector number
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*
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* Output parameters: NONE
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*
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*
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* NO_CPU Specific Information:
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*
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* XXX document implementation including references if appropriate
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*/
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void _CPU_ISR_install_vector(
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unsigned32 vector,
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proc_ptr new_handler,
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proc_ptr *old_handler
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)
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{
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*old_handler = _ISR_Vector_table[ vector ];
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/*
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* If the interrupt vector table is a table of pointer to isr entry
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* points, then we need to install the appropriate RTEMS interrupt
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* handler for this vector number.
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*/
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_CPU_ISR_install_raw_handler( vector, new_handler, old_handler );
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/*
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* We put the actual user ISR address in '_ISR_vector_table'. This will
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* be used by the _ISR_Handler so the user gets control.
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*/
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_ISR_Vector_table[ vector ] = new_handler;
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}
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/*PAGE
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*
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* _CPU_Install_interrupt_stack
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*
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* We don't use a separate interrupt stack.
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*
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*/
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void _CPU_Install_interrupt_stack( void )
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{
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}
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/*PAGE
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*
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* _CPU_Thread_Idle_body
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*
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* NOTES:
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*
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* 1. This is the same as the regular CPU independent algorithm.
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*
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* 2. If you implement this using a "halt", "idle", or "shutdown"
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* instruction, then don't forget to put it in an infinite loop.
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*
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* 3. Be warned. Some processors with onboard DMA have been known
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* to stop the DMA if the CPU were put in IDLE mode. This might
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* also be a problem with other on-chip peripherals. So use this
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* hook with caution.
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*
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*/
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void _CPU_Thread_Idle_body( void )
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{
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for( ; ; )
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/* insert your "halt" instruction here */ ;
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}
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